Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539874
Efe Öztürk, D. Genschow, U. Yodprasit, Berk Yilmaz, D. Kissinger, W. Debski, W. Winkler
This paper focuses on the design and measurement results of a 120 GHz monostatic transceiver system for FMCW radar applications. The fully integrated chip is fabricated using 0.13 μm SiGe BiCMOS technology with fT/fmax of 250/340 GHz and occupies only an area of 1.33×0.73mm2, With a current consumption of 270 mA from a 3.3 V single supply, this fully differential transceiver is composed of an I/Q receiver, which has 11.8 dB of conversion gain and −16.6 dBm of input referred P1dB, and a transmitter with 2.6 dBm saturated output power having a 4-bit push-push type VCO integrated to a divide-by-32 block. Furthermore, TX and RX channels are isolated with a very compact front coupler so that the monostatic operation is possible with a single antenna input. As a built-in-self-test block, the transmitted power on transmitter chain is monitored through a two stage power detector by a branch-line-coupler. With the help of a small sized 3×3 cm2 HDPE lens and a compact antenna, the proposed fully integrated monostatic transceiver could detect obstacles above 100 m and proves its suitability for ISM band 120 GHz FMCW radar applications.
{"title":"A 120 GHz SiGe BiCMOS Monostatic Transceiver for Radar Applications","authors":"Efe Öztürk, D. Genschow, U. Yodprasit, Berk Yilmaz, D. Kissinger, W. Debski, W. Winkler","doi":"10.23919/EUMIC.2018.8539874","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539874","url":null,"abstract":"This paper focuses on the design and measurement results of a 120 GHz monostatic transceiver system for FMCW radar applications. The fully integrated chip is fabricated using 0.13 μm SiGe BiCMOS technology with fT/fmax of 250/340 GHz and occupies only an area of 1.33×0.73mm2, With a current consumption of 270 mA from a 3.3 V single supply, this fully differential transceiver is composed of an I/Q receiver, which has 11.8 dB of conversion gain and −16.6 dBm of input referred P1dB, and a transmitter with 2.6 dBm saturated output power having a 4-bit push-push type VCO integrated to a divide-by-32 block. Furthermore, TX and RX channels are isolated with a very compact front coupler so that the monostatic operation is possible with a single antenna input. As a built-in-self-test block, the transmitted power on transmitter chain is monitored through a two stage power detector by a branch-line-coupler. With the help of a small sized 3×3 cm2 HDPE lens and a compact antenna, the proposed fully integrated monostatic transceiver could detect obstacles above 100 m and proves its suitability for ISM band 120 GHz FMCW radar applications.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126223947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539905
V. Di Giacomo-Brunel, E. Byk, C. Chang, J. Grünenpütt, B. Lambert, G. Mouginot, D. Sommer, H. Jung, M. Camiade, P. Fellon, D. Floriot, H. Blanck, J. Viaud
This paper describes the main characteristics of the new GaN-on-SiC technology in development at UMS. This technology is based on a $0.15 - mu mathrm{m}$ gate-length and it is in the phase of industrial qualification for a target release by the end of the year. The results of two out of four demonstrators already successfully designed on the new technology are also reported: a 29.5–36 Ghz 9W HPA and a 15.5–18.5 GHz 20W HPA.
{"title":"Industrial 0.15-μm AlGaN/GaN on SiC Technology for Applications up to Ka Band","authors":"V. Di Giacomo-Brunel, E. Byk, C. Chang, J. Grünenpütt, B. Lambert, G. Mouginot, D. Sommer, H. Jung, M. Camiade, P. Fellon, D. Floriot, H. Blanck, J. Viaud","doi":"10.23919/EUMIC.2018.8539905","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539905","url":null,"abstract":"This paper describes the main characteristics of the new GaN-on-SiC technology in development at UMS. This technology is based on a $0.15 - mu mathrm{m}$ gate-length and it is in the phase of industrial qualification for a target release by the end of the year. The results of two out of four demonstrators already successfully designed on the new technology are also reported: a 29.5–36 Ghz 9W HPA and a 15.5–18.5 GHz 20W HPA.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125704457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539876
Xiao Xu, T. Sugiura, T. Yoshimasu
This paper presents a 14-GHz band ultra-low-power low-phase-noise VCO IC with a novel harmonic tuned LC tank consisting of a conventional LC tank and additional series inductors. The additional inductor is connected between the drain of the cross-coupled pMOSFET and the conventional LC tank circuit to adjust the harmonic impedance and to shape the drain voltage waveform rectangular. The adjusted load impedance improves the phase noise of the VCO IC. The conventional and proposed VCOs are designed, fabricated and fully measured on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase-noise of − 125.7 dBc/Hz at 10 MHz offset from the 13.46 GHz carrier frequency at a supply voltage of only 0.3 V. The power consumption of the VCO IC core is 0.63 mW and the FoM is − 190.2 dBc/Hz.
{"title":"A 0.3 V −190.2 dBc/Hz FoM 14-GHz Band LC-VCO IC with Harmonic Tuned LC Tank in 56-nm SOI CMOS","authors":"Xiao Xu, T. Sugiura, T. Yoshimasu","doi":"10.23919/EUMIC.2018.8539876","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539876","url":null,"abstract":"This paper presents a 14-GHz band ultra-low-power low-phase-noise VCO IC with a novel harmonic tuned LC tank consisting of a conventional LC tank and additional series inductors. The additional inductor is connected between the drain of the cross-coupled pMOSFET and the conventional LC tank circuit to adjust the harmonic impedance and to shape the drain voltage waveform rectangular. The adjusted load impedance improves the phase noise of the VCO IC. The conventional and proposed VCOs are designed, fabricated and fully measured on-wafer in 56-nm SOI CMOS technology. The fabricated VCO IC has exhibited a measured phase-noise of − 125.7 dBc/Hz at 10 MHz offset from the 13.46 GHz carrier frequency at a supply voltage of only 0.3 V. The power consumption of the VCO IC core is 0.63 mW and the FoM is − 190.2 dBc/Hz.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122939223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539941
M. Bouslama, A. Al Hajjar, R. Sommet, F. Medjdoub, J. Nallatamby
This paper reports the full characterization and modeling of novel AlN/GaN HEMTs on silicon using a short gate length. This device has been optimized for high frequency analog circuits applications. The presented model includes DC and small-signal modeling steps taking into account the trapping effects. It contains a trap model inside the current source which allows to accurately predict gate-lag transient response and low frequency dispersion of the output admittance. The model is validated by comparing the 4 GHz load-pull measurement results with the simulation ones.
{"title":"Characterization and Electrical Modeling Including Trapping Effects of AIN/GaN HEMT 4×50μm on Silicon Substrate","authors":"M. Bouslama, A. Al Hajjar, R. Sommet, F. Medjdoub, J. Nallatamby","doi":"10.23919/EUMIC.2018.8539941","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539941","url":null,"abstract":"This paper reports the full characterization and modeling of novel AlN/GaN HEMTs on silicon using a short gate length. This device has been optimized for high frequency analog circuits applications. The presented model includes DC and small-signal modeling steps taking into account the trapping effects. It contains a trap model inside the current source which allows to accurately predict gate-lag transient response and low frequency dispersion of the output admittance. The model is validated by comparing the 4 GHz load-pull measurement results with the simulation ones.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134608680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539867
A. Issaoun, P. Hammes, M. Fagerlind, F. Chai, T. Roedle
Highly optimized multi-finger GaN HEMT's are prone to internal oscillations or odd-modes. Developing tools to detect and suppress these oscillations is of great help for GaN device designers. This manuscript proposes an internal oscillations detection technique based on a FET small-signal equivalent circuit coupled to Electromagnetic (EM) simulations. Then, a stability analysis technique is applied on the developed transfer function. The approach is demonstrated on three 8-finger cells using three different stability analysis techniques. All outcomes of the used stability techniques align which proves the accuracy of the developed approach.
{"title":"On Stability Analysis and Loop Oscillation of Multi-Finger GaN FET Cells for High Power Amplifiers","authors":"A. Issaoun, P. Hammes, M. Fagerlind, F. Chai, T. Roedle","doi":"10.23919/EUMIC.2018.8539867","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539867","url":null,"abstract":"Highly optimized multi-finger GaN HEMT's are prone to internal oscillations or odd-modes. Developing tools to detect and suppress these oscillations is of great help for GaN device designers. This manuscript proposes an internal oscillations detection technique based on a FET small-signal equivalent circuit coupled to Electromagnetic (EM) simulations. Then, a stability analysis technique is applied on the developed transfer function. The approach is demonstrated on three 8-finger cells using three different stability analysis techniques. All outcomes of the used stability techniques align which proves the accuracy of the developed approach.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117187523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539915
M. Hossain, M. Eissa, M. Hrobak, D. Stoppel, N. Weimann, A. Malignaggi, A. Mai, D. Kissinger, W. Heinrich, V. Krozer
This paper presents a W -band hetero-integrated transmitter module using InP-on-BiCMOS technology. It consists of a Phase Locked Loop (PLL) in 0.25 μm BiCMOS technology and a frequency multiplier followed by a double-balanced Gilbert mixer cell in 0.8 μm InP-HBT technology, which is integrated on top of the BiCMOS MMIC in a wafer-level BCB bonding process. The PLL operates from 45 GHz to 47 GHz and the module achieves a measured single sideband (SSB) power conversion loss of 20 dB and 22 dB at 88 GHz and 95 GHz, respectively, limited by the output power from the PLL source. The entire circuit consumes 434 mW DC power. The chip area of the module is 2.5×1.3 mm2, To the knowledge of the authors, this is the first complex hetero-Integrated module reported so far.
{"title":"A Hetero-Integrated W-Band Transmitter Module in InP-on-BiCMOS Technology","authors":"M. Hossain, M. Eissa, M. Hrobak, D. Stoppel, N. Weimann, A. Malignaggi, A. Mai, D. Kissinger, W. Heinrich, V. Krozer","doi":"10.23919/EUMIC.2018.8539915","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539915","url":null,"abstract":"This paper presents a W -band hetero-integrated transmitter module using InP-on-BiCMOS technology. It consists of a Phase Locked Loop (PLL) in 0.25 μm BiCMOS technology and a frequency multiplier followed by a double-balanced Gilbert mixer cell in 0.8 μm InP-HBT technology, which is integrated on top of the BiCMOS MMIC in a wafer-level BCB bonding process. The PLL operates from 45 GHz to 47 GHz and the module achieves a measured single sideband (SSB) power conversion loss of 20 dB and 22 dB at 88 GHz and 95 GHz, respectively, limited by the output power from the PLL source. The entire circuit consumes 434 mW DC power. The chip area of the module is 2.5×1.3 mm2, To the knowledge of the authors, this is the first complex hetero-Integrated module reported so far.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"371 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541760
Sefa Özbek, M. Grözing, G. Alavi, J. Burghartz, M. Berroth
This paper reports on a design methodology and measurement results of a fully integrated low noise amplifier (LNA) on a thinned substrate for Internet of Things (IoT) applications. Several key RF performance parameters of the LNA with different substrate thickness are evaluated through full-wave electromagnetic (EM) simulations. The proposed LNA operating at 5.5 GHz is fabricated in a cost-effective 0.25 μm SiGe BiCMOS technology (IHP process SGB25V; ft = 75 GHz). The Si chip is thinned to ~38 μm in order to be embedded seamlessly into a flexible foil system. The small-signal gain of the LNA, measured on the chuck is 14.32 dB before thinning. The measured center frequency on the thin silicon (thickness of 38 μm) is shifted about 700 MHz towards higher frequencies compared to the thick silicon due to the image mirror currents within the conducting material at the backside of the chip. The measured noise figure (NF) with the thick and thin substrate on the conducting material is around 3.36 dB at 5.5 GHz and 3.74 dB at 6.3 GHz., respectively.
{"title":"Three-Path SiGe BiCMOS LNA on Thinned Silicon Substrate for IoT Applications","authors":"Sefa Özbek, M. Grözing, G. Alavi, J. Burghartz, M. Berroth","doi":"10.23919/eumc.2018.8541760","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541760","url":null,"abstract":"This paper reports on a design methodology and measurement results of a fully integrated low noise amplifier (LNA) on a thinned substrate for Internet of Things (IoT) applications. Several key RF performance parameters of the LNA with different substrate thickness are evaluated through full-wave electromagnetic (EM) simulations. The proposed LNA operating at 5.5 GHz is fabricated in a cost-effective 0.25 μm SiGe BiCMOS technology (IHP process SGB25V; ft = 75 GHz). The Si chip is thinned to ~38 μm in order to be embedded seamlessly into a flexible foil system. The small-signal gain of the LNA, measured on the chuck is 14.32 dB before thinning. The measured center frequency on the thin silicon (thickness of 38 μm) is shifted about 700 MHz towards higher frequencies compared to the thick silicon due to the image mirror currents within the conducting material at the backside of the chip. The measured noise figure (NF) with the thick and thin substrate on the conducting material is around 3.36 dB at 5.5 GHz and 3.74 dB at 6.3 GHz., respectively.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539935
S. Duffy, B. Benbakhti, W. Zhang, K. Kalna, K. Ahmeda, M. Boucherta, N. Bourzgui, H. Maher, A. Soltani
The source/drain and gate induced charge trapping within an AIGaN/GaN high electron mobility transistor is studied, under normal device operation, by excluding self-heating effects, for the first time. Through direct measurement of current transients of both source and drain terminals, a characterisation technique has been developed to: (i) analyse the transient current degradations from μS to seconds, and (ii) evaluate the drain and gate induced charge trapping mechanisms. Two degradation mechanisms of current are observed: bulk trapping at a short time <1ms); and surface trapping and redistribution (>lms). The bulk charge trapping is found to occur during both ON and OFF states of the device when Vns>0V; where its trapping time constant is independent of bias conditions. In addition, the time constant of the slower current degradation is found to be mainly dependent on surface trapping and redistribution, not by the second heat transient.
{"title":"A Source and Drain Transient Currents Technique for Trap Characterisation in AIGaN/GaN HEMTs","authors":"S. Duffy, B. Benbakhti, W. Zhang, K. Kalna, K. Ahmeda, M. Boucherta, N. Bourzgui, H. Maher, A. Soltani","doi":"10.23919/EUMIC.2018.8539935","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539935","url":null,"abstract":"The source/drain and gate induced charge trapping within an AIGaN/GaN high electron mobility transistor is studied, under normal device operation, by excluding self-heating effects, for the first time. Through direct measurement of current transients of both source and drain terminals, a characterisation technique has been developed to: (i) analyse the transient current degradations from μS to seconds, and (ii) evaluate the drain and gate induced charge trapping mechanisms. Two degradation mechanisms of current are observed: bulk trapping at a short time <1ms); and surface trapping and redistribution (>lms). The bulk charge trapping is found to occur during both ON and OFF states of the device when Vns>0V; where its trapping time constant is independent of bias conditions. In addition, the time constant of the slower current degradation is found to be mainly dependent on surface trapping and redistribution, not by the second heat transient.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121780691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/eumc.2018.8541657
Cheng Guo, J. Powell, X. Shang, M. Lancaster, Jun Xu, C. Viegas
A W-band Schottky diode based frequency tripler which uses waveguide resonator filters for low loss impedance matching is presented in this paper. Impedance matching of the diodes is achieved by scaling the external quality factors and adjusting the resonant frequencies of the filter cavities. This removes most of the matching structures from the high loss microstrip circuit to the lower loss waveguide resonators. Here the output frequency of the tripler is set to be 90 GHz with a 10% bandwidth. The simulation shows a conversion loss of 13-13.8 dB in the pass-band with an input power of 13–20 dBm. The measured conversion loss over the pass-band is 13.6 −15.8 dB for 17 dBm input power and better than 14 dB at 90 GHz for 13–20 dBm input power.
{"title":"A W-Band Frequency Tripler with Integrated Waveguide Filter Matching","authors":"Cheng Guo, J. Powell, X. Shang, M. Lancaster, Jun Xu, C. Viegas","doi":"10.23919/eumc.2018.8541657","DOIUrl":"https://doi.org/10.23919/eumc.2018.8541657","url":null,"abstract":"A W-band Schottky diode based frequency tripler which uses waveguide resonator filters for low loss impedance matching is presented in this paper. Impedance matching of the diodes is achieved by scaling the external quality factors and adjusting the resonant frequencies of the filter cavities. This removes most of the matching structures from the high loss microstrip circuit to the lower loss waveguide resonators. Here the output frequency of the tripler is set to be 90 GHz with a 10% bandwidth. The simulation shows a conversion loss of 13-13.8 dB in the pass-band with an input power of 13–20 dBm. The measured conversion loss over the pass-band is 13.6 −15.8 dB for 17 dBm input power and better than 14 dB at 90 GHz for 13–20 dBm input power.","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121872349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.23919/EUMIC.2018.8539940
D. Schwantuschke, P. Brückner, R. Amirpour, A. Tessmann, M. Kuri, M. Riessle, H. Massler, R. Quay
This work presents a balanced GaN-based power amplifier targeting the entire V-band frequency range. The fabricated chip was packaged in a split block WR-15 waveguide environment to make it applicable for high-power measurement applications. The designed GaN MMIC provides a high small-signal gain of more than 20 dB within a frequency range of 49 GHz up to 83 GHz. On-wafer large-signal measurements of the MMIC at 75 GHz demonstrate a linear gain of 26.3 dB, along with a saturated output power of 29.3 dBm (850 mW) and a maximum power added efficiency of 13.5 % For the assembled module, an average saturated output power of 28.1 dBm (645 mW) within a variance of ±0.4 dB has been measured for the entire V-band (50–75 GHz).
{"title":"Broadband GaN-Based Power Amplifier MMIC and Module for V-Band Measurement Applications","authors":"D. Schwantuschke, P. Brückner, R. Amirpour, A. Tessmann, M. Kuri, M. Riessle, H. Massler, R. Quay","doi":"10.23919/EUMIC.2018.8539940","DOIUrl":"https://doi.org/10.23919/EUMIC.2018.8539940","url":null,"abstract":"This work presents a balanced GaN-based power amplifier targeting the entire V-band frequency range. The fabricated chip was packaged in a split block WR-15 waveguide environment to make it applicable for high-power measurement applications. The designed GaN MMIC provides a high small-signal gain of more than 20 dB within a frequency range of 49 GHz up to 83 GHz. On-wafer large-signal measurements of the MMIC at 75 GHz demonstrate a linear gain of 26.3 dB, along with a saturated output power of 29.3 dBm (850 mW) and a maximum power added efficiency of 13.5 % For the assembled module, an average saturated output power of 28.1 dBm (645 mW) within a variance of ±0.4 dB has been measured for the entire V-band (50–75 GHz).","PeriodicalId":248339,"journal":{"name":"2018 13th European Microwave Integrated Circuits Conference (EuMIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129898452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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