Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156580
D. Maeding, C. Austin, P. Maimone
This report will cover a phoneme speech synthesizer IC intended to be interfaced to a microprocessor. The IC operates on a single 5V supply and features 64 selectable phonemes, 4096 pitch frequencies and eight articulation rates.
{"title":"An integrated phoneme speech synthesizer","authors":"D. Maeding, C. Austin, P. Maimone","doi":"10.1109/ISSCC.1984.1156580","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156580","url":null,"abstract":"This report will cover a phoneme speech synthesizer IC intended to be interfaced to a microprocessor. The IC operates on a single 5V supply and features 64 selectable phonemes, 4096 pitch frequencies and eight articulation rates.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115703294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156625
J. Berger, L. Brissot, Y. Cazaux, P. Descure
An image sensor that uses pixel elements consisting of both photodiodes and MOS capacitor storage, and incorporates blooming suppression, will be discussed.
将讨论一种图像传感器，它使用由光电二极管和MOS电容存储组成的像素元素，并结合了盛开抑制。
{"title":"A line transfer color image sensor with 576×462 pixels","authors":"J. Berger, L. Brissot, Y. Cazaux, P. Descure","doi":"10.1109/ISSCC.1984.1156625","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156625","url":null,"abstract":"An image sensor that uses pixel elements consisting of both photodiodes and MOS capacitor storage, and incorporates blooming suppression, will be discussed.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"531 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156616
Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi
A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.
{"title":"A 45ns 16×16 CMOS multiplier","authors":"Y. Kaji, N. Sugiyama, Y. Kitamura, S. Ohya, M. Kikuchi","doi":"10.1109/ISSCC.1984.1156616","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156616","url":null,"abstract":"A 16 × 16 parallel multiplier, using 1.5μm design rule N-well CMOS technology, will be covered. A multiply time of 45ns has been achieved by using Booth's algorithm and Wallace tree reduction. The typical power dissipation is 100mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115284484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156588
W. Davis, R. Vyne
A 10MHz amplifier with a 45V/μs slew rate, and 1.8μs settling time to 1/2LSB of 12b (10V step), will be covered. An NPN output stage and compensated Miller amplifier provides 500pF drive, 55° phase and 5dB gain margins over (+14/-14.7) V output swing.
{"title":"A monolithic P-channel JFET QUAD operational amplifier","authors":"W. Davis, R. Vyne","doi":"10.1109/ISSCC.1984.1156588","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156588","url":null,"abstract":"A 10MHz amplifier with a 45V/μs slew rate, and 1.8μs settling time to 1/2LSB of 12b (10V step), will be covered. An NPN output stage and compensated Miller amplifier provides 500pF drive, 55° phase and 5dB gain margins over (+14/-14.7) V output swing.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126436250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156634
P. Reutz, S. Pope, B. Solberg, R. Brodersen
This paper will cover a 16-channel filter bank for speech recognition and a single filter generated by computer programs from filter descriptions. The dynamic range in the filter bank (112 pole) is 68dB and the area is 32 sq. mm.
{"title":"Computer generation of digital filter banks","authors":"P. Reutz, S. Pope, B. Solberg, R. Brodersen","doi":"10.1109/ISSCC.1984.1156634","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156634","url":null,"abstract":"This paper will cover a 16-channel filter bank for speech recognition and a single filter generated by computer programs from filter descriptions. The dynamic range in the filter bank (112 pole) is 68dB and the area is 32 sq. mm.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131212403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156617
B. Bynum, D. Cave
The design of a driver IC featuring a power vertical PNP combined with bipolar/CMOS control circuitry will be discussed. Trqe circuit provides 1.0A output current with 0.5V input-output voltage and 25mA control current. It accepts 4.5 to 36V supply voltage with ±125V transients.
{"title":"A power BiMOS with integral high current PNP transistor","authors":"B. Bynum, D. Cave","doi":"10.1109/ISSCC.1984.1156617","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156617","url":null,"abstract":"The design of a driver IC featuring a power vertical PNP combined with bipolar/CMOS control circuitry will be discussed. Trqe circuit provides 1.0A output current with 0.5V input-output voltage and 25mA control current. It accepts 4.5 to 36V supply voltage with ±125V transients.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133215101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156660
F. Masuoka, S. Ariizumi, T. Iwase, M. Ono, Norio Endo
This paper will describe a 1Mb programmable ROM incorporating a through-hole programmed mask ROM cell and a CMOS fully static sense amp. The ROM has been fabricated using a double poly-Si P-well CMOS technology, achieving a cell size of 33μm2.
{"title":"An 80ns 1Mb ROM","authors":"F. Masuoka, S. Ariizumi, T. Iwase, M. Ono, Norio Endo","doi":"10.1109/ISSCC.1984.1156660","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156660","url":null,"abstract":"This paper will describe a 1Mb programmable ROM incorporating a through-hole programmed mask ROM cell and a CMOS fully static sense amp. The ROM has been fabricated using a double poly-Si P-well CMOS technology, achieving a cell size of 33μm2.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133837092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156596
D. Patterson, S. Seccombe
With lowering defect densities in LSI fabrication technologies interest in wafer scale integration has revived. The process holds the promise of higher performance, lower cost, and increased packing density, particularly at the system level. However, it is necessary to consider if recent advances are sufficient to outweigh problems in testing, repairability and system configuration, ancl flexibility. To be assessed too are the problems that limited early implementations in the 60s and if they can be overcome; and if wafer scale integration will provide new opportunities such as systolic arrays, connection-oriented architectures and other related disciplines . . . Panelists will discuss unique technological approaches and the future potentials along with limitations that may arise.
{"title":"Wafer scale integration","authors":"D. Patterson, S. Seccombe","doi":"10.1109/ISSCC.1984.1156596","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156596","url":null,"abstract":"With lowering defect densities in LSI fabrication technologies interest in wafer scale integration has revived. The process holds the promise of higher performance, lower cost, and increased packing density, particularly at the system level. However, it is necessary to consider if recent advances are sufficient to outweigh problems in testing, repairability and system configuration, ancl flexibility. To be assessed too are the problems that limited early implementations in the 60s and if they can be overcome; and if wafer scale integration will provide new opportunities such as systolic arrays, connection-oriented architectures and other related disciplines . . . Panelists will discuss unique technological approaches and the future potentials along with limitations that may arise.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134473274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156631
C. Erdelyi, R. Bechade, M. Concannon, W. Hoffman
This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.
{"title":"A comparison of mixed gate array and custom IC design methods","authors":"C. Erdelyi, R. Bechade, M. Concannon, W. Hoffman","doi":"10.1109/ISSCC.1984.1156631","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156631","url":null,"abstract":"This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131415233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156664
Te-Long Chiu, Tsung-Ching Wu, G. Perlegos
A 125ns, 50mW 256Kb EPROM featuring 12V-16V programming will be described. The design utilizes a 1.5μm N-well CMOS on epi technology resulting In a cell size of 37.5μm2and a die size of 180 mil ×180 mil.
一个125ns, 50mW 256Kb EPROM，具有12V-16V编程。该设计采用1.5μm n阱CMOS on epi技术，电池尺寸为37.5μm2，芯片尺寸为180 mil ×180 mil。
{"title":"256Kb CMNOS EPROM","authors":"Te-Long Chiu, Tsung-Ching Wu, G. Perlegos","doi":"10.1109/ISSCC.1984.1156664","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156664","url":null,"abstract":"A 125ns, 50mW 256Kb EPROM featuring 12V-16V programming will be described. The design utilizes a 1.5μm N-well CMOS on epi technology resulting In a cell size of 37.5μm<sup>2</sup>and a die size of 180 mil ×180 mil.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121324904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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