Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156702
K. Hardee, M. Griffus, R. Galvas
This paper will describe a 30ns 64K×1 CMOS SRAM using analog circuit techniques, multistage decoding, and a single polysilicon memory cell with a buried vss line.
{"title":"A 30ns 64K CMOS RAM","authors":"K. Hardee, M. Griffus, R. Galvas","doi":"10.1109/ISSCC.1984.1156702","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156702","url":null,"abstract":"This paper will describe a 30ns 64K×1 CMOS SRAM using analog circuit techniques, multistage decoding, and a single polysilicon memory cell with a buried vss line.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130264197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156603
S. Pope, B. Solberg, R. Brodersen
A DIGITAL MOS-LSI circuit which implements a full-duplcx speech analysis/synthcsis system will be reported. This vocodcr IC analyzes speech in realtime, generating a low-bit-rate digital data stream suitable for transmission or storage. Simultaneously, syntllesized spccch can be generated from an incoming data stream. Vocoders transmit two types of informalion: spectral parameters and excitation parameters. The vocodcr IC uses linear predictive coding(LPC) to reprcsent the spectrum. The excitation is represented by its energy, a voiced/unvoiced decision, and the period of the pitch fundamental.
{"title":"A single chip LPC vocoder","authors":"S. Pope, B. Solberg, R. Brodersen","doi":"10.1109/ISSCC.1984.1156603","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156603","url":null,"abstract":"A DIGITAL MOS-LSI circuit which implements a full-duplcx speech analysis/synthcsis system will be reported. This vocodcr IC analyzes speech in realtime, generating a low-bit-rate digital data stream suitable for transmission or storage. Simultaneously, syntllesized spccch can be generated from an incoming data stream. Vocoders transmit two types of informalion: spectral parameters and excitation parameters. The vocodcr IC uses linear predictive coding(LPC) to reprcsent the spectrum. The excitation is represented by its energy, a voiced/unvoiced decision, and the period of the pitch fundamental.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122000666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/isscc.1984.1156701
Provides a listing of current committee members.
提供当前委员会成员的列表。
{"title":"Program committee 1984 ISSCC","authors":"","doi":"10.1109/isscc.1984.1156701","DOIUrl":"https://doi.org/10.1109/isscc.1984.1156701","url":null,"abstract":"Provides a listing of current committee members.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156570
S. Gross, J. Shott, J. Meindl
A chip with selectable command rates up to 200 per second with error checking and command acknowledgment, using analog and I2L digital circuity, will be described. Backside argon gettering and a stratfied epitaxial layer have been used to provide 3μA operation.
{"title":"A digital radio command link for implantable biotelemetry applications","authors":"S. Gross, J. Shott, J. Meindl","doi":"10.1109/ISSCC.1984.1156570","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156570","url":null,"abstract":"A chip with selectable command rates up to 200 per second with error checking and command acknowledgment, using analog and I2L digital circuity, will be described. Backside argon gettering and a stratfied epitaxial layer have been used to provide 3μA operation.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130768235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156643
Y. Fujita, E. Masuda, S. Sakamoto, T. Sakaue, Y. Sato
A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.
{"title":"A bulk CMOS 20MS/s 7b flash ADC","authors":"Y. Fujita, E. Masuda, S. Sakamoto, T. Sakaue, Y. Sato","doi":"10.1109/ISSCC.1984.1156643","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156643","url":null,"abstract":"A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134288758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156578
A. Chiang, R. Mountain, D. Silversmith, B. Felton
The design of a CCD matrix-matrix device operating up to 10MHz clock rates, performing the serial-in parallel-out and Fourier transform functions required in radar doppler filtering, will be reported. The chip contains 32 multipliers and 1024 accumulators.
{"title":"A CCD matrix matrix product parallel processor","authors":"A. Chiang, R. Mountain, D. Silversmith, B. Felton","doi":"10.1109/ISSCC.1984.1156578","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156578","url":null,"abstract":"The design of a CCD matrix-matrix device operating up to 10MHz clock rates, performing the serial-in parallel-out and Fourier transform functions required in radar doppler filtering, will be reported. The chip contains 32 multipliers and 1024 accumulators.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156649
R. Schumann, W. Parker
This report will cover a bus interface chip providing 600ns data access time, 13Mb bandwidth and error detection. The crip (265 × 265mils) is mounted in a 132 pin ceramic pin grid array and dissipates 3.5W.
{"title":"A 32b bus interface chip","authors":"R. Schumann, W. Parker","doi":"10.1109/ISSCC.1984.1156649","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156649","url":null,"abstract":"This report will cover a bus interface chip providing 600ns data access time, 13Mb bandwidth and error detection. The crip (265 × 265mils) is mounted in a 132 pin ceramic pin grid array and dissipates 3.5W.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156622
Hae-Sung Lee, D. Hodges, P. Gray
Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.
{"title":"A self calibrating 12b 12µs CMOS ADC","authors":"Hae-Sung Lee, D. Hodges, P. Gray","doi":"10.1109/ISSCC.1984.1156622","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156622","url":null,"abstract":"Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156684
W. Rosenweig, H. Kirsch
Since 1970, DRAMs have grown from 1K to 256K. They have been the technology leaders which helped push design rules from 10μm down to under 2μm. Since the 4K generation, the leaders have been the address multiplexed ×1 DRAMs in 16Pin, 300mil DIPs. The power supply has become a standard 5V... There are many possibilities at the 1M level. The x4 or x8 organizations preferred by small system designers may begin to dominate the market. Video RAMs and other smart memories may become much more pervasive. New packing alternatives may prove to be the most effective. The 5V power supply may no longer be viable. New technological innovations may be needed to provide the required packing densities, while retaining adequate margins and levels of reliability. New procedures may be needed to test such large memories.
{"title":"1Mb DRAM alternatives","authors":"W. Rosenweig, H. Kirsch","doi":"10.1109/ISSCC.1984.1156684","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156684","url":null,"abstract":"Since 1970, DRAMs have grown from 1K to 256K. They have been the technology leaders which helped push design rules from 10μm down to under 2μm. Since the 4K generation, the leaders have been the address multiplexed ×1 DRAMs in 16Pin, 300mil DIPs. The power supply has become a standard 5V... There are many possibilities at the 1M level. The x4 or x8 organizations preferred by small system designers may begin to dominate the market. Video RAMs and other smart memories may become much more pervasive. New packing alternatives may prove to be the most effective. The 5V power supply may no longer be viable. New technological innovations may be needed to provide the required packing densities, while retaining adequate margins and levels of reliability. New procedures may be needed to test such large memories.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125976349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156677
B. Ahuja, W. Baxter, P. Gray
A per subcriber low-voltage CMOS chip with 30 programmable features will be described. A 33mm2, 100mW two-channel CODEC filter includes a 40PPM/°C bandgap, a 300- ohm line driver and on-chip balance networks.
{"title":"A programmable CMOS dual channel interface processor","authors":"B. Ahuja, W. Baxter, P. Gray","doi":"10.1109/ISSCC.1984.1156677","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156677","url":null,"abstract":"A per subcriber low-voltage CMOS chip with 30 programmable features will be described. A 33mm2, 100mW two-channel CODEC filter includes a 40PPM/°C bandgap, a 300- ohm line driver and on-chip balance networks.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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