Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156620
N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada
This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.
{"title":"A 16ns 2K×8b CMOS SRAM","authors":"N. Okazaki, T. Komatsu, N. Hoshi, K. Tsuboi, T. Shimada","doi":"10.1109/ISSCC.1984.1156620","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156620","url":null,"abstract":"This report will cover a 2K × 8b SRAM using 1.5μm CMOS technology with platinum silicide gate electrodes and single layer aluminum. Typical access time is 16ns, and power dissipation is 150mW at 1MHz.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115323495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156600
M. Taguchi, S. Audo, S. Hijiya, T. Nakamura, S. Economo, T. Yabu
CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __
{"title":"A capacitance coupled bit line cell for Mb level DRAMs","authors":"M. Taguchi, S. Audo, S. Hijiya, T. Nakamura, S. Economo, T. Yabu","doi":"10.1109/ISSCC.1984.1156600","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156600","url":null,"abstract":"CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156570
S. Gross, J. Shott, J. Meindl
A chip with selectable command rates up to 200 per second with error checking and command acknowledgment, using analog and I2L digital circuity, will be described. Backside argon gettering and a stratfied epitaxial layer have been used to provide 3μA operation.
{"title":"A digital radio command link for implantable biotelemetry applications","authors":"S. Gross, J. Shott, J. Meindl","doi":"10.1109/ISSCC.1984.1156570","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156570","url":null,"abstract":"A chip with selectable command rates up to 200 per second with error checking and command acknowledgment, using analog and I2L digital circuity, will be described. Backside argon gettering and a stratfied epitaxial layer have been used to provide 3μA operation.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130768235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156702
K. Hardee, M. Griffus, R. Galvas
This paper will describe a 30ns 64K×1 CMOS SRAM using analog circuit techniques, multistage decoding, and a single polysilicon memory cell with a buried vss line.
{"title":"A 30ns 64K CMOS RAM","authors":"K. Hardee, M. Griffus, R. Galvas","doi":"10.1109/ISSCC.1984.1156702","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156702","url":null,"abstract":"This paper will describe a 30ns 64K×1 CMOS SRAM using analog circuit techniques, multistage decoding, and a single polysilicon memory cell with a buried vss line.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130264197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156606
H. Bakoglu, J. Meindl
{"title":"Optimal interconnect circuits for VLSI","authors":"H. Bakoglu, J. Meindl","doi":"10.1109/ISSCC.1984.1156606","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156606","url":null,"abstract":"","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156578
A. Chiang, R. Mountain, D. Silversmith, B. Felton
The design of a CCD matrix-matrix device operating up to 10MHz clock rates, performing the serial-in parallel-out and Fourier transform functions required in radar doppler filtering, will be reported. The chip contains 32 multipliers and 1024 accumulators.
{"title":"A CCD matrix matrix product parallel processor","authors":"A. Chiang, R. Mountain, D. Silversmith, B. Felton","doi":"10.1109/ISSCC.1984.1156578","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156578","url":null,"abstract":"The design of a CCD matrix-matrix device operating up to 10MHz clock rates, performing the serial-in parallel-out and Fourier transform functions required in radar doppler filtering, will be reported. The chip contains 32 multipliers and 1024 accumulators.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122398472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156649
R. Schumann, W. Parker
This report will cover a bus interface chip providing 600ns data access time, 13Mb bandwidth and error detection. The crip (265 × 265mils) is mounted in a 132 pin ceramic pin grid array and dissipates 3.5W.
{"title":"A 32b bus interface chip","authors":"R. Schumann, W. Parker","doi":"10.1109/ISSCC.1984.1156649","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156649","url":null,"abstract":"This report will cover a bus interface chip providing 600ns data access time, 13Mb bandwidth and error detection. The crip (265 × 265mils) is mounted in a 132 pin ceramic pin grid array and dissipates 3.5W.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156622
Hae-Sung Lee, D. Hodges, P. Gray
Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.
{"title":"A self calibrating 12b 12µs CMOS ADC","authors":"Hae-Sung Lee, D. Hodges, P. Gray","doi":"10.1109/ISSCC.1984.1156622","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156622","url":null,"abstract":"Linearity errors of a weighted-capacitor ADC have been corrected, using a simple digital algorithm. A CMOS comparator which resolves 50μV in 500ns, allows this approach to yield a 12b accurate conversion in 22us. Chip area is under 7mm2.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117071426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156684
W. Rosenweig, H. Kirsch
Since 1970, DRAMs have grown from 1K to 256K. They have been the technology leaders which helped push design rules from 10μm down to under 2μm. Since the 4K generation, the leaders have been the address multiplexed ×1 DRAMs in 16Pin, 300mil DIPs. The power supply has become a standard 5V... There are many possibilities at the 1M level. The x4 or x8 organizations preferred by small system designers may begin to dominate the market. Video RAMs and other smart memories may become much more pervasive. New packing alternatives may prove to be the most effective. The 5V power supply may no longer be viable. New technological innovations may be needed to provide the required packing densities, while retaining adequate margins and levels of reliability. New procedures may be needed to test such large memories.
{"title":"1Mb DRAM alternatives","authors":"W. Rosenweig, H. Kirsch","doi":"10.1109/ISSCC.1984.1156684","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156684","url":null,"abstract":"Since 1970, DRAMs have grown from 1K to 256K. They have been the technology leaders which helped push design rules from 10μm down to under 2μm. Since the 4K generation, the leaders have been the address multiplexed ×1 DRAMs in 16Pin, 300mil DIPs. The power supply has become a standard 5V... There are many possibilities at the 1M level. The x4 or x8 organizations preferred by small system designers may begin to dominate the market. Video RAMs and other smart memories may become much more pervasive. New packing alternatives may prove to be the most effective. The 5V power supply may no longer be viable. New technological innovations may be needed to provide the required packing densities, while retaining adequate margins and levels of reliability. New procedures may be needed to test such large memories.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125976349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156677
B. Ahuja, W. Baxter, P. Gray
A per subcriber low-voltage CMOS chip with 30 programmable features will be described. A 33mm2, 100mW two-channel CODEC filter includes a 40PPM/°C bandgap, a 300- ohm line driver and on-chip balance networks.
{"title":"A programmable CMOS dual channel interface processor","authors":"B. Ahuja, W. Baxter, P. Gray","doi":"10.1109/ISSCC.1984.1156677","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156677","url":null,"abstract":"A per subcriber low-voltage CMOS chip with 30 programmable features will be described. A 33mm2, 100mW two-channel CODEC filter includes a 40PPM/°C bandgap, a 300- ohm line driver and on-chip balance networks.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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