Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156614
R. Tuyl, A. Podell
Once the exclusive province of the silicon bipolar transistor, analog circuits with 50MHz to 5GHz bandwidths are now being fabricated with traditionally slower MOS and traditionally faster GaAs technologies. The current concern is a choice of these technologies as the best for these circuits. One might even ponder if there is a best technology...Panelists will assess the virtues of each technologies.
{"title":"High speed analog ICs","authors":"R. Tuyl, A. Podell","doi":"10.1109/ISSCC.1984.1156614","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156614","url":null,"abstract":"Once the exclusive province of the silicon bipolar transistor, analog circuits with 50MHz to 5GHz bandwidths are now being fabricated with traditionally slower MOS and traditionally faster GaAs technologies. The current concern is a choice of these technologies as the best for these circuits. One might even ponder if there is a best technology...Panelists will assess the virtues of each technologies.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156637
Y. Matsunaga, N. Suzuki
This paper will report on the developmemt of a 492 × 398 element interline transfer CCD imager with a large capacity phOtodiode structure for a single chip 1/2" color camera. The imager has a dynamic range of 75dB.
{"title":"An interline transfer CCD imager","authors":"Y. Matsunaga, N. Suzuki","doi":"10.1109/ISSCC.1984.1156637","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156637","url":null,"abstract":"This paper will report on the developmemt of a 492 × 398 element interline transfer CCD imager with a large capacity phOtodiode structure for a single chip 1/2\" color camera. The imager has a dynamic range of 75dB.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128850395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated 84ps ECL with I2L","authors":"T. Nakamura, K. Nakazato, T. Miyazaki, T. Okabe, M. Naga","doi":"10.1109/ISSCC.1984.1156658","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156658","url":null,"abstract":"A side wall base contact structure used to fabricate 84ps ECL and 320ps I<sup>2</sup>L circuits with gate areas of 3500μm<sup>2</sup>and 112μm<sup>2</sup>will be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156569
H. Veendrick, L. Pfennings, M. Annegarn, H. Harwig, M. Pelgrom, H. Peuscher, J. Raven, A. Slob, J. Slotboom
This report will describe a 34.8mm2serial digital field store chip dissipating 350mW and fabricated in a 2μm NMOS modified with one extra mask. Programmable I/O control and 20ms refresh time provide application flexibility.
{"title":"A 40MHz 308Kb CCD video memory","authors":"H. Veendrick, L. Pfennings, M. Annegarn, H. Harwig, M. Pelgrom, H. Peuscher, J. Raven, A. Slob, J. Slotboom","doi":"10.1109/ISSCC.1984.1156569","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156569","url":null,"abstract":"This report will describe a 34.8mm2serial digital field store chip dissipating 350mW and fabricated in a 2μm NMOS modified with one extra mask. Programmable I/O control and 20ms refresh time provide application flexibility.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120959274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156602
J. Yamada, T. Mano, J. Inoue, S. Nakajima, T. Matsuda
THIS PAPER WILL REPORT ON AN experimental 1Mb dynamic memory, utilizing a 4 bit-at-a-time Error Checking and Correcting (ECC) circuit, and a high-sensitivity distributed sense circuit. A 1Mb DRAM using a 2 0 ~ 2 cell was designed and fabricated with an 0 . 8 ~ CMOS process. An on-chip ECC is essential for megabit level dynamic RAMs to reduce an alpha particle-induced soft error rate. For practical use, a small-sized ECC circuit applicable to multi-bit devices is required instead of one applicable to single-bit devices'. Figure 1 shows the principle of the proposed 4b-at-a-time ECC using a bi-directional parity code. An HV-parity cell is connected with each word line as well as Hand V-parity cells to check all of the data in the memory and parity cells. Each data in the HI-, HZ-, Vi-, and V2-groups are selected to carry out four types of parity checking. By combining the parity-checked result of each Hgroup data, with that of each V-group data, four correcting signals are acquired simultaneously. In applying this 4b-at-a-time ECC to megabit level RAMs, selector design is most important in reducing its size. The best configuration of a selector is obtained by minimizing the number of selector lines, as shown in Figure 2. Parity check circuits are arranged on the upper and lower sides of the selector. The II1-group data are transferred upward to check the data in the upper half of the memory cell array. The Vi-group data, however, are transferred upward and downward to check the data in the upper-left and lower-left quarters of the array. With such a configuration, the selector size for this 4b-at-a-time ECC is reduced so that it is as small as that required for a single bit ECC. In addition, since the ECC incorporates a self-checking function, the size of a parity cell can be made the same as that of the memory cell, maintaining the reduced soft error rate. As a result, the ECC circuit occupied about 12% of the entire chip area. To overcome the problem of a small storage node capacitance (CS) in megabit level dynamic RAMs, it is necessary to realize a high-sensitivity sense circuit. The distributed sense circuit proposed achieves this result by reducing the effective bit-line capacitance (CB). As shown in Figure 3, the sense circuit is composed of a main amplifier and distributively arranged preamplifiers, each of which has an address controlled switch. In pre-sensing, since all the switches are turned off, the ratio of CB/CS becomes smaller and the pre-sensed signal can be obtained by the selected preamplifier. After pre-sensing, all of the switches are turned on to transfer the pre-sensed signal to the main amplifier. After this operation, a high-speed sensing is performed in cooperation with the main amplifier and all of the preamplifiers combined. Since the pre-sensed signal is transferred through __
{"title":"A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit","authors":"J. Yamada, T. Mano, J. Inoue, S. Nakajima, T. Matsuda","doi":"10.1109/ISSCC.1984.1156602","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156602","url":null,"abstract":"THIS PAPER WILL REPORT ON AN experimental 1Mb dynamic memory, utilizing a 4 bit-at-a-time Error Checking and Correcting (ECC) circuit, and a high-sensitivity distributed sense circuit. A 1Mb DRAM using a 2 0 ~ 2 cell was designed and fabricated with an 0 . 8 ~ CMOS process. An on-chip ECC is essential for megabit level dynamic RAMs to reduce an alpha particle-induced soft error rate. For practical use, a small-sized ECC circuit applicable to multi-bit devices is required instead of one applicable to single-bit devices'. Figure 1 shows the principle of the proposed 4b-at-a-time ECC using a bi-directional parity code. An HV-parity cell is connected with each word line as well as Hand V-parity cells to check all of the data in the memory and parity cells. Each data in the HI-, HZ-, Vi-, and V2-groups are selected to carry out four types of parity checking. By combining the parity-checked result of each Hgroup data, with that of each V-group data, four correcting signals are acquired simultaneously. In applying this 4b-at-a-time ECC to megabit level RAMs, selector design is most important in reducing its size. The best configuration of a selector is obtained by minimizing the number of selector lines, as shown in Figure 2. Parity check circuits are arranged on the upper and lower sides of the selector. The II1-group data are transferred upward to check the data in the upper half of the memory cell array. The Vi-group data, however, are transferred upward and downward to check the data in the upper-left and lower-left quarters of the array. With such a configuration, the selector size for this 4b-at-a-time ECC is reduced so that it is as small as that required for a single bit ECC. In addition, since the ECC incorporates a self-checking function, the size of a parity cell can be made the same as that of the memory cell, maintaining the reduced soft error rate. As a result, the ECC circuit occupied about 12% of the entire chip area. To overcome the problem of a small storage node capacitance (CS) in megabit level dynamic RAMs, it is necessary to realize a high-sensitivity sense circuit. The distributed sense circuit proposed achieves this result by reducing the effective bit-line capacitance (CB). As shown in Figure 3, the sense circuit is composed of a main amplifier and distributively arranged preamplifiers, each of which has an address controlled switch. In pre-sensing, since all the switches are turned off, the ratio of CB/CS becomes smaller and the pre-sensed signal can be obtained by the selected preamplifier. After pre-sensing, all of the switches are turned on to transfer the pre-sensed signal to the main amplifier. After this operation, a high-speed sensing is performed in cooperation with the main amplifier and all of the preamplifiers combined. Since the pre-sensed signal is transferred through __","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126907213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156718
S. Schuster, B. Chappell, V. DiLionardo, P. Britton
A 32.6mm24K×16 NMOS SRAM having a 20ns access time and 30ns cycle time will be covered. The SRAM utilizes a 4 transistor dynamic refresh memory cell with 1.7μm features and single level polycide.
{"title":"A 20ns 64K NMOS RAM","authors":"S. Schuster, B. Chappell, V. DiLionardo, P. Britton","doi":"10.1109/ISSCC.1984.1156718","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156718","url":null,"abstract":"A 32.6mm24K×16 NMOS SRAM having a 20ns access time and 30ns cycle time will be covered. The SRAM utilizes a 4 transistor dynamic refresh memory cell with 1.7μm features and single level polycide.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124060095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156697
Haw-Ming Haung, D. Banatao, G. Perlegos, Tsing-Ching Wu, Te-Long Chiu
A 10MHz CMOS Ethernet Manchester encoder/decoder will be described. By using a PLL, the device can decode data having 18ns of jitter. The transmitter drives a 78-ohm transceiver cable directly with less than a 0.5ns skew. The chip (2μm/N-well) is 99 × 115mil2and consumes 150mW.
{"title":"A CMOS ethernet serial interface chip","authors":"Haw-Ming Haung, D. Banatao, G. Perlegos, Tsing-Ching Wu, Te-Long Chiu","doi":"10.1109/ISSCC.1984.1156697","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156697","url":null,"abstract":"A 10MHz CMOS Ethernet Manchester encoder/decoder will be described. By using a PLL, the device can decode data having 18ns of jitter. The transmitter drives a 78-ohm transceiver cable directly with less than a 0.5ns skew. The chip (2μm/N-well) is 99 × 115mil2and consumes 150mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156615
A. Grebene
The impact of semi-custom design methodologies in the digital LSI field is obvious. A similar trend is now beginning to emerge in the field of analog LSI. The new trends and developments in the areas of design methodologies, CAD tools and software for low-cost, quick turnaround development of both bipolar and MOS analog LSI will be appraised, with specific areas of discussion on such key topics as mask-programmable analog and analog/digital arrays, analog standard cells, customer-interactive design methodologies and CAD tools, future trends towards user-designed analog LSI and if there will ever be an analog-silicon compiler.
{"title":"Semi-custom analog LSI design trends and directions","authors":"A. Grebene","doi":"10.1109/ISSCC.1984.1156615","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156615","url":null,"abstract":"The impact of semi-custom design methodologies in the digital LSI field is obvious. A similar trend is now beginning to emerge in the field of analog LSI. The new trends and developments in the areas of design methodologies, CAD tools and software for low-cost, quick turnaround development of both bipolar and MOS analog LSI will be appraised, with specific areas of discussion on such key topics as mask-programmable analog and analog/digital arrays, analog standard cells, customer-interactive design methodologies and CAD tools, future trends towards user-designed analog LSI and if there will ever be an analog-silicon compiler.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156629
L. Heller, W. R. Griffin, James W Davis, Nandor G Thorna
A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.
{"title":"Cascode voltage switch logic: A differential CMOS logic family","authors":"L. Heller, W. R. Griffin, James W Davis, Nandor G Thorna","doi":"10.1109/ISSCC.1984.1156629","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156629","url":null,"abstract":"A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122736203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156695
K. Fukahori, T. Glad, L. Engh
A circuit to extract digital signaling information from its associated voice channel in frequency division multiplexing will be presented. Frequency translation using switched capacitor techniques has been employed to achieve a 112 × 130mil2die in metal gate CMOS technology.
{"title":"Signaling pickoff filter for FDM","authors":"K. Fukahori, T. Glad, L. Engh","doi":"10.1109/ISSCC.1984.1156695","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156695","url":null,"abstract":"A circuit to extract digital signaling information from its associated voice channel in frequency division multiplexing will be presented. Frequency translation using switched capacitor techniques has been employed to achieve a 112 × 130mil2die in metal gate CMOS technology.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129907981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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