Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156630
R. Kasai, K. Fukami, K. Tansho, H. Kitazawa, S. Horiguchi
An integrated method which combines modular and standard -cell techniques with automated PLA design to implement a 16b microcomputer will be reported. A CAD system was used to achieve less than 20 man-month design time.
{"title":"An integrated modular and standard cell IC design method","authors":"R. Kasai, K. Fukami, K. Tansho, H. Kitazawa, S. Horiguchi","doi":"10.1109/ISSCC.1984.1156630","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156630","url":null,"abstract":"An integrated method which combines modular and standard -cell techniques with automated PLA design to implement a 16b microcomputer will be reported. A CAD system was used to achieve less than 20 man-month design time.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126952981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156682
E. Swartzlander, W. Young, S. Joseph
The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.
{"title":"A VLSI delay commutator for FFT implementation","authors":"E. Swartzlander, W. Young, S. Joseph","doi":"10.1109/ISSCC.1984.1156682","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156682","url":null,"abstract":"The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115430319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156623
N. Yokoyama, H. Onodera, T. Shinoki, H. Ohnishi, H. Nishi, A. Shibatomi
A 3ns 700mW GaAs 4K × 1b SRAM using tungsten-silicide gate, self-aligned technology, will be described. The development uses 1.5μm gates, E/D direct coupled FET logic and 2μm line-width metalization.
{"title":"A 3ns GaAs 4K×1b SRAM","authors":"N. Yokoyama, H. Onodera, T. Shinoki, H. Ohnishi, H. Nishi, A. Shibatomi","doi":"10.1109/ISSCC.1984.1156623","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156623","url":null,"abstract":"A 3ns 700mW GaAs 4K × 1b SRAM using tungsten-silicide gate, self-aligned technology, will be described. The development uses 1.5μm gates, E/D direct coupled FET logic and 2μm line-width metalization.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156638
Hen Yuan, W. Mclevige, Hung Shih, A. Hearn
This report will discuss the design, fabrication and performance of a 1K heterojunction I2L gate array with a base bar size of 3.55 × 3.80mm2, containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.
{"title":"GaAs heterojunction bipolar 1K gate array","authors":"Hen Yuan, W. Mclevige, Hung Shih, A. Hearn","doi":"10.1109/ISSCC.1984.1156638","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156638","url":null,"abstract":"This report will discuss the design, fabrication and performance of a 1K heterojunction I2L gate array with a base bar size of 3.55 × 3.80mm2, containing 1024 internal gates, 64 programmable I/O buffers and 8 pads for the power supply. For general circuit applications the layout provides 300 global wire channels: 150 each in the horizontal and vertical directions.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156696
W. Herndon
Several design approaches and technologies have shown impressive abilities to produce SRAMs with densities greater than 1Kb and access times less than 25ns. Panelists will examine opportunities to develop further these technologies and produce a density of ≥64Kb and access time of ≤5ns. Issues to be probed include the access time of merged bipolar memories and the cell sizes and economics of GaAs memories.
{"title":"Opportunities and limitations in ultra high speed SRAMs","authors":"W. Herndon","doi":"10.1109/ISSCC.1984.1156696","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156696","url":null,"abstract":"Several design approaches and technologies have shown impressive abilities to produce SRAMs with densities greater than 1Kb and access times less than 25ns. Panelists will examine opportunities to develop further these technologies and produce a density of ≥64Kb and access time of ≤5ns. Issues to be probed include the access time of merged bipolar memories and the cell sizes and economics of GaAs memories.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121565365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156686
K. Itoh, R. Hori, Jun Etoh, S. Asai, N. Hashimoto, K. Yagi, H. Sunami
This paper will report on an experimental 21μm2cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm2
{"title":"An experimental 1Mb DRAM with on-chip voltage limiter","authors":"K. Itoh, R. Hori, Jun Etoh, S. Asai, N. Hashimoto, K. Yagi, H. Sunami","doi":"10.1109/ISSCC.1984.1156686","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156686","url":null,"abstract":"This paper will report on an experimental 21μm<sup>2</sup>cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm<sup>2</sup>","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114326955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156595
P. Asbeck, D. Miller, R. Anderson, R. Deming, L. Hou, C. Liechti, F. Eisen
THIS PAPER WILL DESCRIBE the design of frequency dividers implemented with GaAs/(GaAl)As heterojunction bipolar transistors (HBTs) in an emitter-coupled logic circuit configuration. Frequency division (+ 2 and + 4) was obtained with input frequencies as high as 4.5GHz, using devices with emitter dimensions of 1 . 6 ~ x 5 ~ . Interest in GaAs/(GaAl)As HBTs derives from their potential for higher cutoff frequency, lower base resistance and lower emitter-base capacitance than obtained with Si bipolar transistors'. At the same time, they are expected to provide higher current drive capability, higher transconductance, and lower sensitivity to process parameters than GaAs FETs'. I2L circuits employing HBTs have been described'. Recently, prototype ECL ringoscillators using HBTs have also been reported3. The ECL approach is oriented towards high frequency operation. At the same time, its differential structure reduces circuit sensitivity to supply voltage, temperature and device variations, and its constant supply current characteristic reduces noise generation due to parasitic inductances during high frequency operation. The divider circuits were based on master-slave flipflops constructed from D-latches of the type shown in Figure 1. Divide-by-2 operation was obtained by feeding the M/S flipflop output back to the D input. Divide-by-4 operation was obtained by combining two divide-by-2 sections on the same chip, with the output of the first providing the clock input of the second (after an emitter-follower stage for buffering and level-shifting). Both types of dividers were provided with output buffer amplifiers and emitter-follower output drivers. Divide-by-4 circuits utilized 32 transistors. A microphotograph of a completed chip is shown in Figure 2. Exclusive of pads, the chip occupies an area of 2 1 0 p x 450W. The structure of the transistors is shown schematically in Figure 3. MBE growth was utilized to deposit the device layers on a semi-insulating GaAs substrate. Base layers approximately 1000Athick doped to 3x1018,-3 with Be were utilized. Implanted Be was also used to make contact to the base. Device isolation was provided by boron bombardment. Resistors were made with evaporated Ni-Cr. Further details of the process have been reported3. Transistors (with the exception of output drivers) had emitter dimensions of 1 . 6 ~ x 5m and emitter-base contact separations of 1.6/un. The maximum current of the devices is 6-8mA. -
本文将描述在发射体耦合逻辑电路配置中采用GaAs/(GaAl)As异质结双极晶体管(HBTs)实现的分频器的设计。使用发射器尺寸为1的器件，在输入频率高达4.5GHz时获得分频(+ 2和+ 4)。6 ~ x 5 ~。对GaAs/(GaAl)As双极晶体管的兴趣源于它们比Si双极晶体管具有更高的截止频率、更低的基极电阻和更低的发射极-基极电容的潜力。与此同时，与GaAs fet相比，它们有望提供更高的电流驱动能力、更高的跨导性和更低的工艺参数灵敏度。已经描述了采用hbt的I2L电路。最近，使用HBTs的ECL环形振荡器原型也被报道了3。ECL方法面向高频操作。同时，其差分结构降低了电路对电源电压、温度和器件变化的灵敏度，其恒定的电源电流特性降低了高频工作时寄生电感产生的噪声。分频电路基于主从触发器，由图1所示的d型锁存器构成。通过将M/S触发器输出馈送回D输入，获得除2运算。除4运算是通过在同一芯片上组合两个除2部分来获得的，第一个部分的输出提供第二个部分的时钟输入(经过一个用于缓冲和电平移位的发射器-跟随器阶段)。两种类型的分频器都配备了输出缓冲放大器和发射器跟随器输出驱动器。除4电路使用32个晶体管。完成芯片的显微照片如图2所示。除去焊盘，该芯片的面积为210p × 450W。晶体管的结构示意图如图3所示。利用MBE生长将器件层沉积在半绝缘的GaAs衬底上。使用了约1000厚的基材层，掺杂到3x1018，-3与Be。植入的Be也被用来与基地联系。硼轰击装置隔离。电阻器是用蒸发镍铬制成的。该过程的进一步细节已被报道。晶体管(输出驱动器除外)的发射极尺寸为1。6 ~ x 5m，发射架-底座接触距离1.6/un。设备的最大电流为6 ~ 8ma。-
{"title":"4.5GHz frequency dividers using GaAs/(Ga,AI) as heterojunction bipolar transistors","authors":"P. Asbeck, D. Miller, R. Anderson, R. Deming, L. Hou, C. Liechti, F. Eisen","doi":"10.1109/ISSCC.1984.1156595","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156595","url":null,"abstract":"THIS PAPER WILL DESCRIBE the design of frequency dividers implemented with GaAs/(GaAl)As heterojunction bipolar transistors (HBTs) in an emitter-coupled logic circuit configuration. Frequency division (+ 2 and + 4) was obtained with input frequencies as high as 4.5GHz, using devices with emitter dimensions of 1 . 6 ~ x 5 ~ . Interest in GaAs/(GaAl)As HBTs derives from their potential for higher cutoff frequency, lower base resistance and lower emitter-base capacitance than obtained with Si bipolar transistors'. At the same time, they are expected to provide higher current drive capability, higher transconductance, and lower sensitivity to process parameters than GaAs FETs'. I2L circuits employing HBTs have been described'. Recently, prototype ECL ringoscillators using HBTs have also been reported3. The ECL approach is oriented towards high frequency operation. At the same time, its differential structure reduces circuit sensitivity to supply voltage, temperature and device variations, and its constant supply current characteristic reduces noise generation due to parasitic inductances during high frequency operation. The divider circuits were based on master-slave flipflops constructed from D-latches of the type shown in Figure 1. Divide-by-2 operation was obtained by feeding the M/S flipflop output back to the D input. Divide-by-4 operation was obtained by combining two divide-by-2 sections on the same chip, with the output of the first providing the clock input of the second (after an emitter-follower stage for buffering and level-shifting). Both types of dividers were provided with output buffer amplifiers and emitter-follower output drivers. Divide-by-4 circuits utilized 32 transistors. A microphotograph of a completed chip is shown in Figure 2. Exclusive of pads, the chip occupies an area of 2 1 0 p x 450W. The structure of the transistors is shown schematically in Figure 3. MBE growth was utilized to deposit the device layers on a semi-insulating GaAs substrate. Base layers approximately 1000Athick doped to 3x1018,-3 with Be were utilized. Implanted Be was also used to make contact to the base. Device isolation was provided by boron bombardment. Resistors were made with evaporated Ni-Cr. Further details of the process have been reported3. Transistors (with the exception of output drivers) had emitter dimensions of 1 . 6 ~ x 5m and emitter-base contact separations of 1.6/un. The maximum current of the devices is 6-8mA. -","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131275417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156700
O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida
A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.
{"title":"A 20ns 64K CMOS SRAM","authors":"O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida","doi":"10.1109/ISSCC.1984.1156700","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156700","url":null,"abstract":"A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133901836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156641
Ping Wai, M. Chin, P. Gray, R. Castello
This paper will describe the development of a capacitor-ratio-independent algorithmic conversion technique, which achieves a 0.6LSB integral linearity at 11b and a conversion time of 80μs in a 5μm CMOS process.
{"title":"A ratio independent algorithmic A/D conversion technique","authors":"Ping Wai, M. Chin, P. Gray, R. Castello","doi":"10.1109/ISSCC.1984.1156641","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156641","url":null,"abstract":"This paper will describe the development of a capacitor-ratio-independent algorithmic conversion technique, which achieves a 0.6LSB integral linearity at 11b and a conversion time of 80μs in a 5μm CMOS process.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"410 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133621685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156712
E. Baier, R. Clemen, W. Haug, W. Fischer, R. Mueller, W. Loehlein, H. Barsuhn
A 80ns 256K n-channel metal-gate DRAM with tour selectable data I/O buffers which permit the chip to be used as 64K×4, 128 × 2, or 256 × 1, with either parallel or serial data transfer at 20ns data rate, will be discussed.
{"title":"A 256K NMOS DRAM","authors":"E. Baier, R. Clemen, W. Haug, W. Fischer, R. Mueller, W. Loehlein, H. Barsuhn","doi":"10.1109/ISSCC.1984.1156712","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156712","url":null,"abstract":"A 80ns 256K n-channel metal-gate DRAM with tour selectable data I/O buffers which permit the chip to be used as 64K×4, 128 × 2, or 256 × 1, with either parallel or serial data transfer at 20ns data rate, will be discussed.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133813255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：