Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156613
H. Mussman, M. Foster
The volume of data to be transported in an office environment is growing as more terminals are required to realize office automation systems. Such data can be transported by Private Branch Exchanges (PBX) and/or by Local Area Networks (LANs) . . . With PBX, data from each terminal are typically carried to the PBX on a Digital Subscriber Loop (DSL). With an LSN, data from each terminal are typically carried on a passive bus after being formatted by an interface circuit. . . Initially, panelists will review the present and future technologies available to implement a DSL for a PBX using the 'ping-pong' method of continuous full duplex transmission, an interface circuit for an LAN using a base-band coaxial cable bus, an interface circuit for an LAN using a broadband coaxial cable bus, and an interface circuit for an LAN using an optical fiber bus...In conclusion, the panelists will compare these technologies for availability and costs.
{"title":"Technology for data transport in an office environment","authors":"H. Mussman, M. Foster","doi":"10.1109/ISSCC.1984.1156613","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156613","url":null,"abstract":"The volume of data to be transported in an office environment is growing as more terminals are required to realize office automation systems. Such data can be transported by Private Branch Exchanges (PBX) and/or by Local Area Networks (LANs) . . . With PBX, data from each terminal are typically carried to the PBX on a Digital Subscriber Loop (DSL). With an LSN, data from each terminal are typically carried on a passive bus after being formatted by an interface circuit. . . Initially, panelists will review the present and future technologies available to implement a DSL for a PBX using the 'ping-pong' method of continuous full duplex transmission, an interface circuit for an LAN using a base-band coaxial cable bus, an interface circuit for an LAN using a broadband coaxial cable bus, and an interface circuit for an LAN using an optical fiber bus...In conclusion, the panelists will compare these technologies for availability and costs.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125494218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156632
J. Jensen, K. Martin
An E-beam that was used both to inject and read digital signals for diagnostic test of NMOS and CMOS ICs will be discussed. E-beam programmable master-slave flip-flops, which add less than 0.25pF circuit load, were included for signal injection purposes.
{"title":"Use of E-beam for random access read and write of digital test signals","authors":"J. Jensen, K. Martin","doi":"10.1109/ISSCC.1984.1156632","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156632","url":null,"abstract":"An E-beam that was used both to inject and read digital signals for diagnostic test of NMOS and CMOS ICs will be discussed. E-beam programmable master-slave flip-flops, which add less than 0.25pF circuit load, were included for signal injection purposes.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123092634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156714
T. Yoshino, T. Takamizawa, A. Henderson, S. Abiko, M. Hashizume, T. Satoh, K. Katoh
A speech synthesizer which contains an 8b microprocessor, 65Kbits of ROM, an LPC-10 filter, 256bits of RAM and an ADC, will be described. Algorithms for both speech synthesis using linear prediction and speaker independent voice recognition can be implemented.
{"title":"A monolithic programmable speech synthesizer with voice recognition","authors":"T. Yoshino, T. Takamizawa, A. Henderson, S. Abiko, M. Hashizume, T. Satoh, K. Katoh","doi":"10.1109/ISSCC.1984.1156714","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156714","url":null,"abstract":"A speech synthesizer which contains an 8b microprocessor, 65Kbits of ROM, an LPC-10 filter, 256bits of RAM and an ADC, will be described. Algorithms for both speech synthesis using linear prediction and speaker independent voice recognition can be implemented.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115028172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156650
F. Welten, J. Lohstroh, A. Linssen
A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW.
{"title":"A 25/50MHz dual-mode parallel multiplier/accumulator","authors":"F. Welten, J. Lohstroh, A. Linssen","doi":"10.1109/ISSCC.1984.1156650","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156650","url":null,"abstract":"A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133524514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156666
B. Chappell, S. Schuster, G. Sai-Halasz
Graphical techniques for analyzing the impact of device sizes, threshold tracking, load resistor values and other design parameters on the stability and soft error rate of SRAMs, illustrated via applicat)ons to a high-speed 64K RAM, will be presented.
{"title":"Stability and soft error rates of SRAM cells","authors":"B. Chappell, S. Schuster, G. Sai-Halasz","doi":"10.1109/ISSCC.1984.1156666","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156666","url":null,"abstract":"Graphical techniques for analyzing the impact of device sizes, threshold tracking, load resistor values and other design parameters on the stability and soft error rate of SRAMs, illustrated via applicat)ons to a high-speed 64K RAM, will be presented.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132946279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 3456-element CCD sensor with serpentine shift registers","authors":"S. Onishi, D. Wen, D. Reaves, J. Pendelton","doi":"10.1109/ISSCC.1984.1156590","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156590","url":null,"abstract":"An image sensor incorporating a serpentine shift register structure that allows a 7μm pitch, using a 2-poly, 2-metal process, will be reported.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116060430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156607
C. Rowen, S. Przbylski, N. Jouppi, T. Gross, J. Shott, J. Hennessy
{"title":"A pipelined 32b NMOS microprocessor","authors":"C. Rowen, S. Przbylski, N. Jouppi, T. Gross, J. Shott, J. Hennessy","doi":"10.1109/ISSCC.1984.1156607","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156607","url":null,"abstract":"","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116432500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/isscc.1984.1156640
Y. Ikawa, N. Toyoda, M. Mochisuki, T. Terada, K. Kanazawa, M. Hirose, T. Mizoguchi, A. Hojo
A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.
{"title":"A 1K-gate GaAs gate array","authors":"Y. Ikawa, N. Toyoda, M. Mochisuki, T. Terada, K. Kanazawa, M. Hirose, T. Mizoguchi, A. Hojo","doi":"10.1109/isscc.1984.1156640","DOIUrl":"https://doi.org/10.1109/isscc.1984.1156640","url":null,"abstract":"A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134590238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156709
J. Miyamoto, S. Saitoh, H. Momose, H. Shibata, K. Kanzaki, T. Iizuka
This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nA standby mode.
{"title":"A 28ns CMOS SRAM with bipolar sense amplifiers","authors":"J. Miyamoto, S. Saitoh, H. Momose, H. Shibata, K. Kanzaki, T. Iizuka","doi":"10.1109/ISSCC.1984.1156709","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156709","url":null,"abstract":"This report will discuss a 64K×1 SRAM with bipolar sense amplifiers, utilizing both CMOS and bipolar devices with double poly 1.2μm MoSi processing. The SRAM typically accesses in 28ns and has a 20nA standby mode.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134055491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156644
Y. Yoshii, K. Asano, M. Nakamura, C. Yamada
This paper will describe an 8b flash ADC which achieves a conversion rate of 100MHz arid an input bandwidth of 30MHz at a power dissipation of 1200mW. The circuit is realized in an epitaxial-LOCOS process with a minimum line width of 2.5μm and a transistor fTof 4GHz at 45μA collector current.
{"title":"An 8b 100MS/s flash ADC","authors":"Y. Yoshii, K. Asano, M. Nakamura, C. Yamada","doi":"10.1109/ISSCC.1984.1156644","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156644","url":null,"abstract":"This paper will describe an 8b flash ADC which achieves a conversion rate of 100MHz arid an input bandwidth of 30MHz at a power dissipation of 1200mW. The circuit is realized in an epitaxial-LOCOS process with a minimum line width of 2.5μm and a transistor fTof 4GHz at 45μA collector current.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：