Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156626
C. Laber, P. Lemaitre
This Paper will discuss an IC that performs all of the modulation, demodulation, filtering and handshake required to implement a MODEM that complies with the Bell 202 and CCITT 23 standards. The chip (double poly CMOS) uses switched capacitor techniques to operate at rates up to 1200b/s.
{"title":"A 1200 baud FSK CMOS MODEM","authors":"C. Laber, P. Lemaitre","doi":"10.1109/ISSCC.1984.1156626","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156626","url":null,"abstract":"This Paper will discuss an IC that performs all of the modulation, demodulation, filtering and handshake required to implement a MODEM that complies with the Bell 202 and CCITT 23 standards. The chip (double poly CMOS) uses switched capacitor techniques to operate at rates up to 1200b/s.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127819069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156610
J. Corcoran, K. Knudsen, P. Clark, D. Hiller
A 4OOMHz SAMPLE ratr:, 6b Gray code A/D converter. designed and fabricated in a SGHz bipolar process, maintaining good linearity at high input and clock frequencics without thr use of a sample and hold circuit: will bc dcscribed. Mcasuremr:nts show that thls converter pvrforms w c l l at 4001.11Iz clock frequcncy with a 100MHz full scale sinc wav-I: input. This pcrformancc, represents a substantial irnprovemcnt over prcviously rcportt:d 6b monolithic AID convvrtcrs’ .
{"title":"A 400MHz 6b DAC","authors":"J. Corcoran, K. Knudsen, P. Clark, D. Hiller","doi":"10.1109/ISSCC.1984.1156610","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156610","url":null,"abstract":"A 4OOMHz SAMPLE ratr:, 6b Gray code A/D converter. designed and fabricated in a SGHz bipolar process, maintaining good linearity at high input and clock frequencics without thr use of a sample and hold circuit: will bc dcscribed. Mcasuremr:nts show that thls converter pvrforms w c l l at 4001.11Iz clock frequcncy with a 100MHz full scale sinc wav-I: input. This pcrformancc, represents a substantial irnprovemcnt over prcviously rcportt:d 6b monolithic AID convvrtcrs’ .","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126810807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156683
H. Kawamoto, Y. Yamaguchi, S. Shimizu, K. Ohishi, N. Tanimura, T. Yasui
This paper will report on an externally nonclocked 32K×9b PSRAM that employs an N channel dynamic transistor cell, 6.8μm× 13.6μm, with 5.58mm × 9.86mm die size.
{"title":"A 288Kb CMOS pseudo SRAM","authors":"H. Kawamoto, Y. Yamaguchi, S. Shimizu, K. Ohishi, N. Tanimura, T. Yasui","doi":"10.1109/ISSCC.1984.1156683","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156683","url":null,"abstract":"This paper will report on an externally nonclocked 32K×9b PSRAM that employs an N channel dynamic transistor cell, 6.8μm<tex>× 13.6μ</tex>m, with 5.58mm × 9.86mm die size.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115082983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156652
J. Beck, D. Dobberpuhl, M. Doherty, E. Dornekamp, B. Grondalski, D. Grondalski, K. Henry, M. Miller, B. Supnik, S. Thierauf, R. Witek
The development of a 140,000 transistor 32b single chip microprocessor, implementing a superminicomputer's 304 instructions will be described. The chip is 8.5 × 8.0mm and dissipates 3W.
{"title":"A 32b microprocessor with on chip virtual memory management","authors":"J. Beck, D. Dobberpuhl, M. Doherty, E. Dornekamp, B. Grondalski, D. Grondalski, K. Henry, M. Miller, B. Supnik, S. Thierauf, R. Witek","doi":"10.1109/ISSCC.1984.1156652","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156652","url":null,"abstract":"The development of a 140,000 transistor 32b single chip microprocessor, implementing a superminicomputer's 304 instructions will be described. The chip is 8.5 × 8.0mm and dissipates 3W.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129509808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156661
R. Zeman, Chun Ho, T. Chang
A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.
{"title":"A 55ns CMOS EEPROM","authors":"R. Zeman, Chun Ho, T. Chang","doi":"10.1109/ISSCC.1984.1156661","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156661","url":null,"abstract":"A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129838838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156648
W. Johnson
A 5-chip set implementing 304 instructions of a 32b super-minicomputer, will be reported. The designs include 1,220,500 transistors and operate with a 200ns microcycle.
{"title":"A VLSI superminicomputer CPU","authors":"W. Johnson","doi":"10.1109/ISSCC.1984.1156648","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156648","url":null,"abstract":"A 5-chip set implementing 304 instructions of a 32b super-minicomputer, will be reported. The designs include 1,220,500 transistors and operate with a 200ns microcycle.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129604596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156612
A. Lancaster, P. Salsbury
Large bit density EEPROMs are becoming available from multiple vendors. The structures of these devices are based on many diverse technologies, and provide many different features. Potential users are faced with many difficult choices. Panelists will discuss this profileration of approaches, the relative merits of each and address the standardization problem.
{"title":"Status, future and standardization of EEPROMs","authors":"A. Lancaster, P. Salsbury","doi":"10.1109/ISSCC.1984.1156612","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156612","url":null,"abstract":"Large bit density EEPROMs are becoming available from multiple vendors. The structures of these devices are based on many diverse technologies, and provide many different features. Potential users are faced with many difficult choices. Panelists will discuss this profileration of approaches, the relative merits of each and address the standardization problem.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123374887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156642
P. Holloway
Inherent 16b monotonicity overtime and temperature has been achieved in a voltage-segment DAC structure implemented in an N-well CMOS bipolar process by potentiometrically buffering a cascaded second stage across adjacent taps of an untrimmed resistor string. Settling time to 1/2 LSB is 3μs.
{"title":"A trimless 16b digital potentiometer","authors":"P. Holloway","doi":"10.1109/ISSCC.1984.1156642","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156642","url":null,"abstract":"Inherent 16b monotonicity overtime and temperature has been achieved in a voltage-segment DAC structure implemented in an N-well CMOS bipolar process by potentiometrically buffering a cascaded second stage across adjacent taps of an untrimmed resistor string. Settling time to 1/2 LSB is 3μs.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129334507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156657
P. Zdebel, W. Engl
The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.
{"title":"Merged current mode logic","authors":"P. Zdebel, W. Engl","doi":"10.1109/ISSCC.1984.1156657","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156657","url":null,"abstract":"The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130502087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156708
K. Hanson, W. Severin, D. Richardson, E. Klinkovsky, J. Hochschild, J. Bingham
A quadrature phase-shift key MODEM IC will be discussed. The die (55.7K sq mil) contains all of the modulation, demodulation, filtering and data buffering functions for Bell 212 and CCITT V.2 compatibility.
{"title":"A 1200b/s QPSK duplex MODEM","authors":"K. Hanson, W. Severin, D. Richardson, E. Klinkovsky, J. Hochschild, J. Bingham","doi":"10.1109/ISSCC.1984.1156708","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156708","url":null,"abstract":"A quadrature phase-shift key MODEM IC will be discussed. The die (55.7K sq mil) contains all of the modulation, demodulation, filtering and data buffering functions for Bell 212 and CCITT V.2 compatibility.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123690747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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