Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156618
J. Kuo, Oh-Hyun Kwon, D. Galbraith, F. Shone, J. Shott, J. Walker, R. Dutton, J. Meindl
The development of a 2μm poly-gate CMOS array which combines digital gate array together with stacked-layout analog capability will be covered. Up to 10 sections of a biquadratic switched-capacitor filter can be implemented in the analog section.
{"title":"A 2µm poly-gate CMOS analog/digital array","authors":"J. Kuo, Oh-Hyun Kwon, D. Galbraith, F. Shone, J. Shott, J. Walker, R. Dutton, J. Meindl","doi":"10.1109/ISSCC.1984.1156618","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156618","url":null,"abstract":"The development of a 2μm poly-gate CMOS array which combines digital gate array together with stacked-layout analog capability will be covered. Up to 10 sections of a biquadratic switched-capacitor filter can be implemented in the analog section.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127876274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156621
N. Kadekodi, A. Claproth, Tuan Vo, A. Anyiwo, L. Sheu, A. Ibrahim
This report will cover a 5732-element 1.2" linear BCCD imager with bilinear staggered sensor array, qualrilinear readout shift registers and integrated analog delay stage to enable sequential data output.
{"title":"A 5732-element 1.2\" linear CCD imager","authors":"N. Kadekodi, A. Claproth, Tuan Vo, A. Anyiwo, L. Sheu, A. Ibrahim","doi":"10.1109/ISSCC.1984.1156621","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156621","url":null,"abstract":"This report will cover a 5732-element 1.2\" linear BCCD imager with bilinear staggered sensor array, qualrilinear readout shift registers and integrated analog delay stage to enable sequential data output.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156663
K. Okumura, S. Ohya, M. Yamamoto, T. Watanabe, Y. Shimamura, M. Kikuchi
A 1Mb fully static EPROM utilizing a 1.2μm design rule technology will be discussed. The chip features typical access time of 200ns, a programming voltage of approximately 13V, and can be used either as 64K × 16 or 128K × 8 organization.
{"title":"A 1Mb EPROM","authors":"K. Okumura, S. Ohya, M. Yamamoto, T. Watanabe, Y. Shimamura, M. Kikuchi","doi":"10.1109/ISSCC.1984.1156663","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156663","url":null,"abstract":"A 1Mb fully static EPROM utilizing a 1.2μm design rule technology will be discussed. The chip features typical access time of 200ns, a programming voltage of approximately 13V, and can be used either as 64K × 16 or 128K × 8 organization.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120930015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156706
M. Kolluri
The application of a multi-step parallel A/D conversion technique, consisting of a single three-position-switchable current-output DAC, a nonlinearity corrected resistor string and a buffered comparator array, to a 10b 1.5μs ADC, will be described.
{"title":"A multi step parallel 10b 1.5µs ADC","authors":"M. Kolluri","doi":"10.1109/ISSCC.1984.1156706","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156706","url":null,"abstract":"The application of a multi-step parallel A/D conversion technique, consisting of a single three-position-switchable current-output DAC, a nonlinearity corrected resistor string and a buffered comparator array, to a 10b 1.5μs ADC, will be described.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116991559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156611
M. Inoue, A. Matsuzawa, H. Sadamatsu, A. Kanda, T. Takemoto
THIS PAPER will report on a monolithic 8 b flash A / D converter which digitizes more than 40MIk signal at 120MS/s and requires no external sample-and-hold circuit. The ADC I S 1 contains 256 comparators, encoder logics, data latches for pip(: line Operation, clock drivers and output buffers. Although the flash ADC offers the possibility of fast conversion and no requirement of samplc-and-hold circuit. it is also necessarv to cmploy many comparators which consume power. Therefore, a high-speed and low-power comparator must be implemented to achieve an ultrahigh speed ADC which has a conversion rate in excess o f 10OVl1-Iz. Figure 1 shows the comparator circuit of the .4DC ISI . The comparator consists of three stages; the first stage is a differential amplifier, the second is a master-latch which samples the analog input signal; and the third is a slave-latch. The differential amplifier is included to prevent talk back of the clock pulse from thc latch circuit to the analog input port. Besides, the amplifier is provided to increase the amplitude of the input signal to the master-latch stage, hence these results improve the latch speed. At the input port, leakage current of 0.4p.4 is detected by the talk back. How-ever, this valuc is one twenty-fifth of the talk back of the conventional comparator’. The master-and-slave latches arc implemented to improve the clock rate. A n AND gate arranged at the output of the master-latch stage examines the outputs of own comparator and two adjacent comparators. The differential amplifier provides a gain of 6. Both latches of the master and slave acquire the signal in only Ins when the overdrive voltage is LmV. Only 1.5ns is needed to recover from the latched state. The current consumption per one comparator is 1.2mA with the voltage bource (VEE) of -5.2V. Encoder circuitry requires large power consumption to maintain ultrahigh speed, since this is composed of a transistor matrix and hence requires large fan-in and fan-out. To solve this problem, a switching current source is employed in the cucoder circuitry to reduce the power consumption while maintaining hgh speed operation. Figure 2 shows a simplified schematic of the encoder circuitry. Since the output signal from only one comparator is at the high level, only the diode, which is connected to the emitter-follower of that comparator, is activated to ON state. Diodes connected to the other comparators remain at OFF state. Therefore, the charge accumulated at bases o f the encoder matrix is swept away via the ON diode with constant current. One constant current sourcc of 40OpA is implemented per sixteen comparators, and an output emitter-follower of each comparator is opcrated with sink-current of 30pA. Accordingly, the current consumption of the output emitter-followcr of the comparators has bemable to at tain a 86% reduction, compared with the encodcr circuitry, which docs not have such a switching current sourcc. In an ultrahigh speed flash ADC; it is ext
本文将报道一种单片8b闪存a / D转换器，它以120MS/s的速度数字化超过40mk的信号，不需要外部采样保持电路。ADC s1包含256个比较器，编码器逻辑，pip(:线操作)数据锁存器，时钟驱动器和输出缓冲区。虽然闪存ADC提供了快速转换的可能性，并且不需要采样保持电路。还需要使用许多消耗功率的比较器。因此，必须实现一个高速和低功耗比较器，以实现超高速ADC，其转换速率超过10OVl1-Iz。图1显示了0.4 dc ISI的比较器电路。比较器包括三个阶段;第一级是差分放大器，第二级是对模拟输入信号进行采样的主锁存器;第三个是奴隶锁。包括差分放大器，以防止时钟脉冲从锁存电路到模拟输入端口的回讲。此外，还提供了放大器来增加主锁存级输入信号的幅度，从而提高了锁存速度。输入端漏电流为0.4p。4 .被侦测到的是回话。然而，这个值是传统比较器的二十五分之一。主从锁存器的实现是为了提高时钟速率。设置在主锁存器输出端的与门检查自己的比较器和两个相邻的比较器的输出。差分放大器的增益为6。当超速电压为LmV时，主锁存器和从锁存器仅在Ins内获取信号。从锁存状态恢复只需要1.5ns。每个比较器的电流消耗为1.2mA，电压源(VEE)为-5.2V。编码器电路需要大的功耗来保持超高速，因为这是由晶体管矩阵组成的，因此需要大的扇入和扇出。为了解决这一问题，在编码电路中采用开关电流源，在保持高速运行的同时降低功耗。图2显示了编码器电路的简化原理图。由于只有一个比较器的输出信号处于高电平，因此只有连接到该比较器的发射从动器的二极管被激活到ON状态。连接到其他比较器的二极管保持OFF状态。因此，积累在编码器矩阵基底0处的电荷通过ON二极管以恒流扫去。每16个比较器实现一个40OpA的恒流源，每个比较器的输出发射极-从动器以30pA的吸收电流工作。因此，与没有这样的开关电流源的编码器电路相比，比较器的输出发射器-跟随器的电流消耗已经能够降低86%。在超高速闪存ADC中;由于需要亚纳秒级的异或门，将格雷码转换为纯二进制码是极其困难的。因此，有必要实现必须将模拟信号直接转换为纯二进制代码而不丢失代码的编码器逻辑。缺失的代码往往出现在与比较器布局的折叠点相对应的msb的过渡处。为了解决这个问题，在两个相邻的比较器组之间插入了一个抑制电路，如图3所示。每个比较器组由32个比较器组成，其输出信号被转换成低5b二进制codc。然后提供一个或门(例如，OR2A)来检查5LSB位信号的锁存器输出。OR门的输出抑制下一个比较器组的5133位，如果51、SB位信号中的任何一个处于高电平。所使用的工艺是自校准2pm双极技术。制造的关键是基极和发射极的离子注入，以及非活性基极的BSG扩散以获得良好的基极-发射极电压匹配。发射极接触的大小正好与发射极面积相同。外延层厚度为2pm，基底宽度一般为0.2pm。在发射极电流为200pA时，即与比较器的吸收电流相等时，f~值为2.5GHz。4 × 4pm发射极尺寸晶体管对的基极-发射极偏差分布为0.2mV作为标准差;3 0。图4显示了在12OMI-Iz转换速率下采样后重构的4OMHz正弦波。图5为转换频率为12OMHz，输入频率为30.1MHz时的拍频测试结果;因此节拍频率为0.1MIlz。当输入信号为3031Hz时，信噪比为40dB。表1显示了主要特性的列表。图6是包含24,000个元件的ADC IS1的照片。芯片尺寸为4.3mm x 7.5mm。
{"title":"An 8b monolithic ADC","authors":"M. Inoue, A. Matsuzawa, H. Sadamatsu, A. Kanda, T. Takemoto","doi":"10.1109/ISSCC.1984.1156611","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156611","url":null,"abstract":"THIS PAPER will report on a monolithic 8 b flash A / D converter which digitizes more than 40MIk signal at 120MS/s and requires no external sample-and-hold circuit. The ADC I S 1 contains 256 comparators, encoder logics, data latches for pip(: line Operation, clock drivers and output buffers. Although the flash ADC offers the possibility of fast conversion and no requirement of samplc-and-hold circuit. it is also necessarv to cmploy many comparators which consume power. Therefore, a high-speed and low-power comparator must be implemented to achieve an ultrahigh speed ADC which has a conversion rate in excess o f 10OVl1-Iz. Figure 1 shows the comparator circuit of the .4DC ISI . The comparator consists of three stages; the first stage is a differential amplifier, the second is a master-latch which samples the analog input signal; and the third is a slave-latch. The differential amplifier is included to prevent talk back of the clock pulse from thc latch circuit to the analog input port. Besides, the amplifier is provided to increase the amplitude of the input signal to the master-latch stage, hence these results improve the latch speed. At the input port, leakage current of 0.4p.4 is detected by the talk back. How-ever, this valuc is one twenty-fifth of the talk back of the conventional comparator’. The master-and-slave latches arc implemented to improve the clock rate. A n AND gate arranged at the output of the master-latch stage examines the outputs of own comparator and two adjacent comparators. The differential amplifier provides a gain of 6. Both latches of the master and slave acquire the signal in only Ins when the overdrive voltage is LmV. Only 1.5ns is needed to recover from the latched state. The current consumption per one comparator is 1.2mA with the voltage bource (VEE) of -5.2V. Encoder circuitry requires large power consumption to maintain ultrahigh speed, since this is composed of a transistor matrix and hence requires large fan-in and fan-out. To solve this problem, a switching current source is employed in the cucoder circuitry to reduce the power consumption while maintaining hgh speed operation. Figure 2 shows a simplified schematic of the encoder circuitry. Since the output signal from only one comparator is at the high level, only the diode, which is connected to the emitter-follower of that comparator, is activated to ON state. Diodes connected to the other comparators remain at OFF state. Therefore, the charge accumulated at bases o f the encoder matrix is swept away via the ON diode with constant current. One constant current sourcc of 40OpA is implemented per sixteen comparators, and an output emitter-follower of each comparator is opcrated with sink-current of 30pA. Accordingly, the current consumption of the output emitter-followcr of the comparators has bemable to at tain a 86% reduction, compared with the encodcr circuitry, which docs not have such a switching current sourcc. In an ultrahigh speed flash ADC; it is ext","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117243283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156692
P. Greiling
High speed digital GaAs ICs have demonstrated a speed advantage over comparable Si ICs. However, one must ask if a very short gate delay is sufficient for high speed digital applications. To be considered too are the potential user areas (general purpose computers, number crunching computers, parallel processing, high-speed signal processing and/or communication interfaces) and if higher speed, lower complexity GaAs digital ICs provide an overall system advantage over the slower, but more complex Si technologies . . .Panelists will address this problem as it applies to their diverse backgrounds and needs, and attempt to define areas where GaAs digital ICs will provide a speed advantage.
{"title":"System requirements for GaAs digital ICs","authors":"P. Greiling","doi":"10.1109/ISSCC.1984.1156692","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156692","url":null,"abstract":"High speed digital GaAs ICs have demonstrated a speed advantage over comparable Si ICs. However, one must ask if a very short gate delay is sufficient for high speed digital applications. To be considered too are the potential user areas (general purpose computers, number crunching computers, parallel processing, high-speed signal processing and/or communication interfaces) and if higher speed, lower complexity GaAs digital ICs provide an overall system advantage over the slower, but more complex Si technologies . . .Panelists will address this problem as it applies to their diverse backgrounds and needs, and attempt to define areas where GaAs digital ICs will provide a speed advantage.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121383902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156624
T. Chan, O. Barrett, C. Chen, Y. Abendini, D. Wen
A 488-element NTSC-compatible CCD imager with a 2/3" format device utilizing a differentially-diffused drain for variable exposure control and element antiblooming will be coverecL
{"title":"A 488×430 interline transfer CCD imager with integrated exposure and blooming control","authors":"T. Chan, O. Barrett, C. Chen, Y. Abendini, D. Wen","doi":"10.1109/ISSCC.1984.1156624","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156624","url":null,"abstract":"A 488-element NTSC-compatible CCD imager with a 2/3\" format device utilizing a differentially-diffused drain for variable exposure control and element antiblooming will be coverecL","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156619
R. Pease
A monolithic IC whose output is linearly proporational to Fahrenheit temparature will be discussed. The circuit develops +10.0mV/°F and is accurate±1/2°F from -50° to +300°F. Accuracy is achieved by wafer level trimming at room temparature.
{"title":"A fahrenheit temperature sensor","authors":"R. Pease","doi":"10.1109/ISSCC.1984.1156619","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156619","url":null,"abstract":"A monolithic IC whose output is linearly proporational to Fahrenheit temparature will be discussed. The circuit develops +10.0mV/°F and is accurate<tex>±1/2°</tex>F from -50° to +300°F. Accuracy is achieved by wafer level trimming at room temparature.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124168980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156605
S. Tanaka, S. Atsumi, M. Momodomi, K. Shinada, K. Yoshikawa, Y. Nagakubo, K. Kanzaki
{"title":"A programmable 256K CMOS EPROM with on-chip test circuits","authors":"S. Tanaka, S. Atsumi, M. Momodomi, K. Shinada, K. Yoshikawa, Y. Nagakubo, K. Kanzaki","doi":"10.1109/ISSCC.1984.1156605","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156605","url":null,"abstract":"","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126299135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1984.1156582
B. Scott, M. Wurtele, B. Creggar
A monolithic voltage-controlled oscillator covering the 11.5- 20.0GHz band continuously, with an average power output of + 12.8dBm, will be described. A (1.1 × 1.3)mm2chip contains a 300μm wide FET, RF bypass capacitors, gate and source inductors and two planar high capacitance ratio varactors.
{"title":"A GaAs monolithic voltage controlled oscillator","authors":"B. Scott, M. Wurtele, B. Creggar","doi":"10.1109/ISSCC.1984.1156582","DOIUrl":"https://doi.org/10.1109/ISSCC.1984.1156582","url":null,"abstract":"A monolithic voltage-controlled oscillator covering the 11.5- 20.0GHz band continuously, with an average power output of + 12.8dBm, will be described. A (1.1 × 1.3)mm2chip contains a 300μm wide FET, RF bypass capacitors, gate and source inductors and two planar high capacitance ratio varactors.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132749251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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