Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662517
Takashi Takemoto, Masato Hayashi, C. Yoshimura, M. Yamaoka
The last decade has seen impressive progress in the development of a new computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimization problems [3]. In addition to quantum annealers based on superconducting circuits [1], annealing processors based on CMOS technology have received increased interest and are being developed on the basis of simulated annealing (SA) [2]. However, these CMOS annealing processors (CMOS-APs) have room for improvement, such as: i) expanding the bit widths of coefficients, and ii) increasing the number of spins handled by the processor. To address these challenges, a CMOS-AP based on the processing-in-memory approach (where CMOS circuits and an SRAM are tightly coupled [4]) has been developed. Its key features are threefold: a spin operator (processing local memory) which provides coefficients with expandable bit width and fast parallel spin updates according to the Gibbs distribution; a low-latency inter-chip interface (I/F) connecting two Ising chips, resulting in an increased number of spins; and a highly integrated spin circuit which directly connects the spin operator with the SRAM cell. Installed in a $2times30$ k spin system, the CMOS-AP demonstrates the capability for multi-chip operation with energy efficiency $1.75times10^{5}$ higher than running SA on a CPU.
{"title":"2.6 A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems","authors":"Takashi Takemoto, Masato Hayashi, C. Yoshimura, M. Yamaoka","doi":"10.1109/ISSCC.2019.8662517","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662517","url":null,"abstract":"The last decade has seen impressive progress in the development of a new computer architecture, commonly known as annealing processor [1, 2]. An annealing processor provides a fast means for finding the ground state of an Ising model; thus, it can efficiently solve NP-hard combinatorial optimization problems [3]. In addition to quantum annealers based on superconducting circuits [1], annealing processors based on CMOS technology have received increased interest and are being developed on the basis of simulated annealing (SA) [2]. However, these CMOS annealing processors (CMOS-APs) have room for improvement, such as: i) expanding the bit widths of coefficients, and ii) increasing the number of spins handled by the processor. To address these challenges, a CMOS-AP based on the processing-in-memory approach (where CMOS circuits and an SRAM are tightly coupled [4]) has been developed. Its key features are threefold: a spin operator (processing local memory) which provides coefficients with expandable bit width and fast parallel spin updates according to the Gibbs distribution; a low-latency inter-chip interface (I/F) connecting two Ising chips, resulting in an increased number of spins; and a highly integrated spin circuit which directly connects the spin operator with the SRAM cell. Installed in a $2times30$ k spin system, the CMOS-AP demonstrates the capability for multi-chip operation with energy efficiency $1.75times10^{5}$ higher than running SA on a CPU.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125013155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662397
Ziyun Li, Yu Chen, Luyao Gong, Lu Liu, D. Sylvester, D. Blaauw, Hun-Seok Kim
Simultaneous localization and mapping (SLAM) estimates an agent’s trajectory for all six degrees of freedom (6 DoF) and constructs a 3D map of an unknown surrounding. It is a fundamental kernel that enables head-mounted augmented/virtual reality devices and autonomous navigation of micro aerial vehicles. A noticeable recent trend in visual SLAM is to apply computation- and memory-intensive convolutional neural networks (CNNs) that outperform traditional hand-designed feature-based methods [1]. For each video frame, CNN-extracted features are matched with stored keypoints to estimate the agent’s 6-DoF pose by solving a perspective-n-points (PnP) non-linear optimization problem (Fig. 7.3.1, left). The agent’s long-term trajectory over multiple frames is refined by a bundle adjustment process (BA, Fig. 7.3.1 right), which involves a large-scale ($sim$120 variables) non-linear optimization. Visual SLAM requires massive computation ($gt250$ GOP/s) in the CNN-based feature extraction and matching, as well as data-dependent dynamic memory access and control flow with high-precision operations, creating significant low-power design challenges. Software implementations are impractical, resulting in 0.2s runtime with a $sim$3 GHz CPU + GPU system with $gt100$ MB memory footprint and $gt100$ W power consumption. Prior ASICs have implemented either an incomplete SLAM system [2, 3] that lacks estimation of ego-motion or employed a simplified (non-CNN) feature extraction and tracking [2, 4, 5] that limits SLAM quality and range. A recent ASIC [5] augments visual SLAM with an off-chip high-precision inertial measurement unit (IMU), simplifying the computational complexity, but incurring additional power and cost overhead.
{"title":"An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration","authors":"Ziyun Li, Yu Chen, Luyao Gong, Lu Liu, D. Sylvester, D. Blaauw, Hun-Seok Kim","doi":"10.1109/ISSCC.2019.8662397","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662397","url":null,"abstract":"Simultaneous localization and mapping (SLAM) estimates an agent’s trajectory for all six degrees of freedom (6 DoF) and constructs a 3D map of an unknown surrounding. It is a fundamental kernel that enables head-mounted augmented/virtual reality devices and autonomous navigation of micro aerial vehicles. A noticeable recent trend in visual SLAM is to apply computation- and memory-intensive convolutional neural networks (CNNs) that outperform traditional hand-designed feature-based methods [1]. For each video frame, CNN-extracted features are matched with stored keypoints to estimate the agent’s 6-DoF pose by solving a perspective-n-points (PnP) non-linear optimization problem (Fig. 7.3.1, left). The agent’s long-term trajectory over multiple frames is refined by a bundle adjustment process (BA, Fig. 7.3.1 right), which involves a large-scale ($sim$120 variables) non-linear optimization. Visual SLAM requires massive computation ($gt250$ GOP/s) in the CNN-based feature extraction and matching, as well as data-dependent dynamic memory access and control flow with high-precision operations, creating significant low-power design challenges. Software implementations are impractical, resulting in 0.2s runtime with a $sim$3 GHz CPU + GPU system with $gt100$ MB memory footprint and $gt100$ W power consumption. Prior ASICs have implemented either an incomplete SLAM system [2, 3] that lacks estimation of ego-motion or employed a simplified (non-CNN) feature extraction and tracking [2, 4, 5] that limits SLAM quality and range. A recent ASIC [5] augments visual SLAM with an off-chip high-precision inertial measurement unit (IMU), simplifying the computational complexity, but incurring additional power and cost overhead.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114209723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662399
{"title":"ISSCC 2019 Technical Program Committee","authors":"","doi":"10.1109/isscc.2019.8662399","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662399","url":null,"abstract":"","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132690412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662391
Sudhanshu Khanna, M. Zwerg, Brian Elies, Juergen Luebbe, Nagaraj Krishnasawamy, Hadi Najar, Suman Bellary, Wei-Yan Shih, S. Summerfelt, Steven Bartling
Ultra-low Power Microcontrollers (MCUs) [1]–[4] have played a central role in embedded IoT systems providing programmability, analog and digital processing and control, A/D interfaces, and power management. As IoT applications expand, efficient sensing is increasingly becoming part of MCUs. In this paper we present a 130nm 16MHz Ferro-electric RAM (FRAM) based MCU with a sub-1uA embedded piezo-electric strain sensor and AFE for ULP motion detection (Fig. 17.4.1). To our knowledge, this is the first reported MCU with an embedded motion detection strain sensor. Existing applications that would benefit from such a MCU are applications like toys and remote controls that can turn off while not in use. Motion detection in a key fob improves security by preventing a “man in the middle” attack while the key fob lies stationary at home. Tamper detection and strain gauges are other potential applications. When used in “wake-on-motion” applications, the sensor IP is powered-on at all times waiting for a motion event. Hence minimizing its power consumption is crucial. Also, considering ULP MCUs have many cost-sensitive applications, the sensor must be small in area, and not require any additional masks or special processing steps. A single-chip solution allows reuse of power management, programmability and control circuits already existing in the MCU for use in the strain sensor IP, reducing the system level cost vs a 2-chip solution.
{"title":"17.4 16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection","authors":"Sudhanshu Khanna, M. Zwerg, Brian Elies, Juergen Luebbe, Nagaraj Krishnasawamy, Hadi Najar, Suman Bellary, Wei-Yan Shih, S. Summerfelt, Steven Bartling","doi":"10.1109/ISSCC.2019.8662391","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662391","url":null,"abstract":"Ultra-low Power Microcontrollers (MCUs) [1]–[4] have played a central role in embedded IoT systems providing programmability, analog and digital processing and control, A/D interfaces, and power management. As IoT applications expand, efficient sensing is increasingly becoming part of MCUs. In this paper we present a 130nm 16MHz Ferro-electric RAM (FRAM) based MCU with a sub-1uA embedded piezo-electric strain sensor and AFE for ULP motion detection (Fig. 17.4.1). To our knowledge, this is the first reported MCU with an embedded motion detection strain sensor. Existing applications that would benefit from such a MCU are applications like toys and remote controls that can turn off while not in use. Motion detection in a key fob improves security by preventing a “man in the middle” attack while the key fob lies stationary at home. Tamper detection and strain gauges are other potential applications. When used in “wake-on-motion” applications, the sensor IP is powered-on at all times waiting for a motion event. Hence minimizing its power consumption is crucial. Also, considering ULP MCUs have many cost-sensitive applications, the sensor must be small in area, and not require any additional masks or special processing steps. A single-chip solution allows reuse of power management, programmability and control circuits already existing in the MCU for use in the strain sensor IP, reducing the system level cost vs a 2-chip solution.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122890992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662322
Marc-Andre LaCroix, H.C.K. Wong, Yun Hua Liu, H. Ho, Semyon Lebedev, P. Krotnev, Dorin Alexandru Nicolescu, D. Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, F. A. Musa, D. Tonietto
With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2, 4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS SerDes in a system. AMS provides an easier and cheaper approach to implement multi-tap DFEs [3] compared to DSP where it is typically very expensive to implement more than a 1-tap DFE. This paper will show an ADC-DSP SerDes transceiver with a 2-tap DFE is capable of operating error-free over a 38dB link yet having an overall power budget similar to AMS. The same basic SerDes architecture is implemented (Fig. 6.2.1) with minor differences in 16nm and 7nm FinFET, however, power scaling is incorporated into the 7nm version only.
{"title":"6.2 A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss","authors":"Marc-Andre LaCroix, H.C.K. Wong, Yun Hua Liu, H. Ho, Semyon Lebedev, P. Krotnev, Dorin Alexandru Nicolescu, D. Petrov, Carlos Carvalho, Stephen Alie, Euhan Chong, F. A. Musa, D. Tonietto","doi":"10.1109/ISSCC.2019.8662322","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662322","url":null,"abstract":"With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS scaling for high-speed mixed-signal designs, SerDes designers and system architects are faced with severe performance versus power budget constraints. Power management and energy efficiency have become the main drivers for system design. However, industry standards such as EEE have failed to keep up with efficiency demands. In this context the choice between a so-called analog mixed signal (AMS) SerDes architecture vs. an ADC-DSP-based one has been debated at length. AMS provides significantly lower maximum power [2, 4] while ADC-DSP provides higher link margin [1] thus avoiding expensive and power hungry repeater ICs that largely negate the power advantage of AMS SerDes in a system. AMS provides an easier and cheaper approach to implement multi-tap DFEs [3] compared to DSP where it is typically very expensive to implement more than a 1-tap DFE. This paper will show an ADC-DSP SerDes transceiver with a 2-tap DFE is capable of operating error-free over a 38dB link yet having an overall power budget similar to AMS. The same basic SerDes architecture is implemented (Fig. 6.2.1) with minor differences in 16nm and 7nm FinFET, however, power scaling is incorporated into the 7nm version only.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124012304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662295
M. M. Ghanbari, David K. Piech, Konlin Shen, Sina Faraji Alamouti, Cem Yalcin, Benjamin C. Johnson, J. Carmena, M. Maharbiz, R. Muller
Miniaturization of implantable neural recording systems to micron-scale volumes will enable minimally invasive implantation and alleviate cortical scarring, gliosis, and resulting signal degradation. Ultrasound (US) power transmission has been demonstrated to have high efficiency and low tissue attenuation for mm-scale implants at depth in tissue [1, 2, 3], but has not been demonstrated with precision recording circuitry. We present an US implantable wireless neural recording system scaled to 0.8mm3, verified to safely operate at 5cm depth with state of the art neural recording performance an average circuit power dissipation of 13μW, and 28.8μW including power conversion efficiency. Sub-mm scale is achieved through single-link power and communication on a single piezocrystal (Lead Zirconate Titanate, PZT) utilizing linear analog backscattering, small die area, and eliminating all other off-chip components.
{"title":"17.5 A 0.8mm3 Ultrasonic Implantable Wireless Neural Recording System With Linear AM Backscattering","authors":"M. M. Ghanbari, David K. Piech, Konlin Shen, Sina Faraji Alamouti, Cem Yalcin, Benjamin C. Johnson, J. Carmena, M. Maharbiz, R. Muller","doi":"10.1109/ISSCC.2019.8662295","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662295","url":null,"abstract":"Miniaturization of implantable neural recording systems to micron-scale volumes will enable minimally invasive implantation and alleviate cortical scarring, gliosis, and resulting signal degradation. Ultrasound (US) power transmission has been demonstrated to have high efficiency and low tissue attenuation for mm-scale implants at depth in tissue [1, 2, 3], but has not been demonstrated with precision recording circuitry. We present an US implantable wireless neural recording system scaled to 0.8mm3, verified to safely operate at 5cm depth with state of the art neural recording performance an average circuit power dissipation of 13μW, and 28.8μW including power conversion efficiency. Sub-mm scale is achieved through single-link power and communication on a single piezocrystal (Lead Zirconate Titanate, PZT) utilizing linear analog backscattering, small die area, and eliminating all other off-chip components.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/ISSCC.2019.8662412
Maarten Baert, W. Dehaene
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2. These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.
{"title":"20.1 A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step","authors":"Maarten Baert, W. Dehaene","doi":"10.1109/ISSCC.2019.8662412","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662412","url":null,"abstract":"Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2. These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127708164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.1109/isscc.2019.8662287
an aging population to reliable communications for first responders, circuits are at the heart of products that address pervasive challenges in our world. Circuit innovation can make our lives better, but to truly tap into the power of circuits, we need to make circuit-based technology accessible and easy to implement in designs. Doing so will empower inventors and entrepreneurs to explore new use cases and leverage technology across domain areas, extending and amplifying the impact of circuit-level innovation. The talk will include some career insights related to this topic. the talk will cover the use of multifunctional neural probes and non-invasive brain neuromodulation in neuroscience, where we are not just passively monitoring the brain, but stimulating the brain for interactive investigation. The workshop highlights circuits and their impact on healthcare-related industries. The goal of the panel is to provide perspectives from system architects, security experts and circuit designers on where we should be heading with the large amount of data that is being generated from more-advanced tests and increased monitoring of our current health status. Security and privacy problems with medical devices and IOT devices in general are in the news on an almost daily basis. One example from 2017 stated: “FDA issues recall of 465,000 pacemakers to patch security holes.” Once medical data is obtained reliably and securely, it is stored on remote servers and in remote databases where there are risks of leaks and data breaches of private medical records. However, it is difficult to put the genie back into the bottle! We have asked our distinguished panel to discuss how circuit designers can contribute to bolster our trust in medical devices and in electronic healthcare systems that manage private medical records. We also encourage the audience to propose attacks and countermeasures.
{"title":"EE2: How to Save Lives with Circuits","authors":"","doi":"10.1109/isscc.2019.8662287","DOIUrl":"https://doi.org/10.1109/isscc.2019.8662287","url":null,"abstract":"an aging population to reliable communications for first responders, circuits are at the heart of products that address pervasive challenges in our world. Circuit innovation can make our lives better, but to truly tap into the power of circuits, we need to make circuit-based technology accessible and easy to implement in designs. Doing so will empower inventors and entrepreneurs to explore new use cases and leverage technology across domain areas, extending and amplifying the impact of circuit-level innovation. The talk will include some career insights related to this topic. the talk will cover the use of multifunctional neural probes and non-invasive brain neuromodulation in neuroscience, where we are not just passively monitoring the brain, but stimulating the brain for interactive investigation. The workshop highlights circuits and their impact on healthcare-related industries. The goal of the panel is to provide perspectives from system architects, security experts and circuit designers on where we should be heading with the large amount of data that is being generated from more-advanced tests and increased monitoring of our current health status. Security and privacy problems with medical devices and IOT devices in general are in the news on an almost daily basis. One example from 2017 stated: “FDA issues recall of 465,000 pacemakers to patch security holes.” Once medical data is obtained reliably and securely, it is stored on remote servers and in remote databases where there are risks of leaks and data breaches of private medical records. However, it is difficult to put the genie back into the bottle! We have asked our distinguished panel to discuss how circuit designers can contribute to bolster our trust in medical devices and in electronic healthcare systems that manage private medical records. We also encourage the audience to propose attacks and countermeasures.","PeriodicalId":265551,"journal":{"name":"2019 IEEE International Solid- State Circuits Conference - (ISSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129066688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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