Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320971
Kin-Joe Sham, Mahmoud Reza Ahmadi, S. Talbot, R. Harjani
We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX pre-emphasis, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMC's 0.18mum CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2times reduction in line separation, FEXT cancellation can successfully reduce jitter by 51.2 %UI and widen the eye by 14.5%. The 2.5 times 1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply
我们提出并验证了一种高速I/O收发器设计的高效架构，实现了远端串扰(ext)消除。在本设计中，传统上用于减少ISI的TX预强调与发射机的ext抵消相结合，以消除串扰引起的抖动和干扰。基于信道测量的仿真模型验证了该架构的有效性。采用台积电0.18 μ m CMOS技术开发了12.8Gbps源同步串行链路发射机的原型实现。提出的设计由三条12.8Gbps的数据线组成，使用6.4GHz的半速率锁相环时钟。该芯片包括一个PRBS发生器，以简化多车道测试。仿真结果表明，在线间距减小2倍的情况下，文本对消可以成功地减少51.2%的抖动UI，使眼睛变宽14.5%。2.5 × 1.5 mm2的核心在1.8V电源下，以12.8Gbps的速度每通道消耗630mW
{"title":"FEXT Crosstalk Cancellation for High-Speed Serial Link Design","authors":"Kin-Joe Sham, Mahmoud Reza Ahmadi, S. Talbot, R. Harjani","doi":"10.1109/CICC.2006.320971","DOIUrl":"https://doi.org/10.1109/CICC.2006.320971","url":null,"abstract":"We have proposed and verified an efficient architecture for a high-speed I/O transceiver design that implements far-end crosstalk (FEXT) cancellation. In this design, TX pre-emphasis, used traditionally to reduce ISI, is combined with FEXT cancellation at the transmitter to remove crosstalk-induced jitter and interference. The architecture has been verified via simulation models based on channel measurement. A prototype implementation of a 12.8Gbps source-synchronous serial link transmitter has been developed in TSMC's 0.18mum CMOS technology. The proposed design consists of three 12.8Gbps data lines that uses a half-rate PLL clock of 6.4GHz. The chip includes a PRBS generator to simplify multi-lane testing. Simulation results show that, even with a 2times reduction in line separation, FEXT cancellation can successfully reduce jitter by 51.2 %UI and widen the eye by 14.5%. The 2.5 times 1.5 mm2 core consumes 630mW per lane at 12.8Gbps with a 1.8V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320852
Gang Liu, T. Liu, A. Niknejad
A 2.4GHz power amplifier is implemented with standard thin-oxide transistors in a 1.2V, 0.13 mum CMOS process. The output matching network is fully integrated on chip. The PA transmits up to 24dBm linear power with 25% drain efficiency at -1dB compression point. When driven into saturation, it transmits 27dBm peak power with 32% drain efficiency. A technique for enhancing average efficiency is proposed and demonstrated. This technique does not degrade instantaneous efficiency at peak power and maintains constant power gain with power back-off
2.4GHz功率放大器采用标准薄氧化物晶体管，采用1.2V, 0.13 μ m CMOS工艺。输出匹配网络完全集成在芯片上。在-1dB压缩点，PA传输高达24dBm的线性功率，漏极效率为25%。当驱动到饱和状态时，它传输27dBm峰值功率，漏极效率为32%。提出并论证了一种提高平均效率的方法。该技术不会降低峰值功率时的瞬时效率，并在功率回退时保持恒定的功率增益
{"title":"A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement","authors":"Gang Liu, T. Liu, A. Niknejad","doi":"10.1109/CICC.2006.320852","DOIUrl":"https://doi.org/10.1109/CICC.2006.320852","url":null,"abstract":"A 2.4GHz power amplifier is implemented with standard thin-oxide transistors in a 1.2V, 0.13 mum CMOS process. The output matching network is fully integrated on chip. The PA transmits up to 24dBm linear power with 25% drain efficiency at -1dB compression point. When driven into saturation, it transmits 27dBm peak power with 32% drain efficiency. A technique for enhancing average efficiency is proposed and demonstrated. This technique does not degrade instantaneous efficiency at peak power and maintains constant power gain with power back-off","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131988356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320957
S. Alalusi, R. Brodersen
This work comprises an array of 4 phase shifters and antennas operating at 60GHz for a beamforming system. Pass gates form the switching core for a phase selector circuit which is replicated to build up a vector modulator phase shifter. The final beam accuracy is better than 2deg for a 16-way system. The die area is 2.7mm times 2.8mm, the buffers take 240mA from a 1.2V supply, the pass gates take no power
{"title":"A 60GHz Phased Array in CMOS","authors":"S. Alalusi, R. Brodersen","doi":"10.1109/CICC.2006.320957","DOIUrl":"https://doi.org/10.1109/CICC.2006.320957","url":null,"abstract":"This work comprises an array of 4 phase shifters and antennas operating at 60GHz for a beamforming system. Pass gates form the switching core for a phase selector circuit which is replicated to build up a vector modulator phase shifter. The final beam accuracy is better than 2deg for a 16-way system. The die area is 2.7mm times 2.8mm, the buffers take 240mA from a 1.2V supply, the pass gates take no power","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132256296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320922
Charles Thomas, Matthew Cooke, Oliver Ridler, Koen van den Beld, Dominic Yip, Uwe Sontowski, A. Kind, Gongyu Zhou, Yi-Chen Li, L. Ung, Rami Banna, B. Widdup, T. Prokop, M. Bickerstaff, G. Woodward, Ravi Srikantiah, Kumud Gupta, Raghupal Reddy, Satyanarayana Arvapalli, Ravindra Bidnur, A. Prasad, Robert Lang, C. Nicol
An HSDPA coprocessor for 3G mobile terminals performs all layer 1 baseband chip rate, symbol rate, physical channel and transport channel processing required to receive 3GPP Release 6 HSDPA at data rates up to 7.2 Mb/s. The design is scalable to all HSDPA data rates up to 14 Mb/s. An advanced receiver using NLMS adaptive equalisers and receive diversity provides the coprocessor with up to 6.4 dB better performance than a traditional single antenna RAKE receiver
{"title":"A Scalable 7.2 Mb/s 3GPP HSDPA Co-processor with Advanced NLMS Receiver and Receive Diversity for Mobile Terminals","authors":"Charles Thomas, Matthew Cooke, Oliver Ridler, Koen van den Beld, Dominic Yip, Uwe Sontowski, A. Kind, Gongyu Zhou, Yi-Chen Li, L. Ung, Rami Banna, B. Widdup, T. Prokop, M. Bickerstaff, G. Woodward, Ravi Srikantiah, Kumud Gupta, Raghupal Reddy, Satyanarayana Arvapalli, Ravindra Bidnur, A. Prasad, Robert Lang, C. Nicol","doi":"10.1109/CICC.2006.320922","DOIUrl":"https://doi.org/10.1109/CICC.2006.320922","url":null,"abstract":"An HSDPA coprocessor for 3G mobile terminals performs all layer 1 baseband chip rate, symbol rate, physical channel and transport channel processing required to receive 3GPP Release 6 HSDPA at data rates up to 7.2 Mb/s. The design is scalable to all HSDPA data rates up to 14 Mb/s. An advanced receiver using NLMS adaptive equalisers and receive diversity provides the coprocessor with up to 6.4 dB better performance than a traditional single antenna RAKE receiver","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116512853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320832
Masum Hossain, A. C. Carusone
This paper describes a broadband CMOS amplifier for differential receiver front-ends. A capacitive cross-coupling network provides passive gmboosting in the input cascode stage. This results in a greater than 30% increase in bandwidth. Combined with several other established bandwidth-enhancement techniques, the prototype achieves a measured 3-dB bandwidth of 19 GHz with no peaking in a 0.18-μm CMOS process. The dc gain is 11 dB differential, and the power consumption is 113 mW. Eye diagrams up to 24 Gb/s are shown.
{"title":"A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-μm CMOS","authors":"Masum Hossain, A. C. Carusone","doi":"10.1109/CICC.2006.320832","DOIUrl":"https://doi.org/10.1109/CICC.2006.320832","url":null,"abstract":"This paper describes a broadband CMOS amplifier for differential receiver front-ends. A capacitive cross-coupling network provides passive gmboosting in the input cascode stage. This results in a greater than 30% increase in bandwidth. Combined with several other established bandwidth-enhancement techniques, the prototype achieves a measured 3-dB bandwidth of 19 GHz with no peaking in a 0.18-μm CMOS process. The dc gain is 11 dB differential, and the power consumption is 113 mW. Eye diagrams up to 24 Gb/s are shown.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"647 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131910205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320896
R. Mahajan, D. Mallik, Robert Sankman, K. Radhakrishnan, C. Chiu, J. He
The role of semiconductor packaging has evolved from space transformation and environmental protection, to becoming an important enabler for silicon and system performance. This paper examines some of the advances in flip-chip packaging as an enabler of power delivery and power removal using a microprocessor as an example. In addition, the role of the package as an enabler of system I/O performance and silicon back-end reliability will be examined
{"title":"Advances and Challenges in Flip-Chip Packaging","authors":"R. Mahajan, D. Mallik, Robert Sankman, K. Radhakrishnan, C. Chiu, J. He","doi":"10.1109/CICC.2006.320896","DOIUrl":"https://doi.org/10.1109/CICC.2006.320896","url":null,"abstract":"The role of semiconductor packaging has evolved from space transformation and environmental protection, to becoming an important enabler for silicon and system performance. This paper examines some of the advances in flip-chip packaging as an enabler of power delivery and power removal using a microprocessor as an example. In addition, the role of the package as an enabler of system I/O performance and silicon back-end reliability will be examined","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128674917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320996
Ruilin Wang, Cheng-Kok Koh, B. Jung, W. Chappell
We propose a novel traveling-wave oscillator (R2TWO) that uses reflection and regeneration of waves on a transmission line to generate multi-GHz square wave signals. We also propose a scalable, low-power, low-skew and low-jitter clock distribution network by tiling the basic R2TWO s in a regular fashion. Measurement results of a TSMC 0.18mum CMOS test chip show that it can generate and distribute near full-swing 6.5GHz global clock signals with power saving of more than 75% (compared with a traditional ring oscillator). The measured jitter is less than 0.84ps, and the skew less than 1.3ps
{"title":"Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration","authors":"Ruilin Wang, Cheng-Kok Koh, B. Jung, W. Chappell","doi":"10.1109/CICC.2006.320996","DOIUrl":"https://doi.org/10.1109/CICC.2006.320996","url":null,"abstract":"We propose a novel traveling-wave oscillator (R2TWO) that uses reflection and regeneration of waves on a transmission line to generate multi-GHz square wave signals. We also propose a scalable, low-power, low-skew and low-jitter clock distribution network by tiling the basic R2TWO s in a regular fashion. Measurement results of a TSMC 0.18mum CMOS test chip show that it can generate and distribute near full-swing 6.5GHz global clock signals with power saving of more than 75% (compared with a traditional ring oscillator). The measured jitter is less than 0.84ps, and the skew less than 1.3ps","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133279513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320973
Q. Du, J. Zhuang, T. Kwasniewski
This paper presents a new programmable delay-locked loop based frequency multiplier with a period error compensation loop (PECL) designed to reduce the output spurious power level. The low bandwidth auxiliary PECL compensates the output period error caused by the in-lock errors from various noise sources. By employing a novel switching control scheme, the circuit is capable of locking to frequencies either above or below the start up frequency without initialization. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 900 MHz to 2.9 GHz. The circuit is implemented in TSMC 0.18mum CMOS technology and measured with the reference signal from an RF signal generator. A 23 dB spur reduction from -23dB to -46.5dB at 1.216GHz is observed from the measurement results. The measured cycle-to-cycle timing jitter at 2.16GHz is 1.6ps (rms) and 12.9 ps (pk-pk), and the measured phase noise is -110 dBc/Hz at 100 kHz offset with a power consumption of 19.8 mW at a 1.8 V supply
{"title":"An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur","authors":"Q. Du, J. Zhuang, T. Kwasniewski","doi":"10.1109/CICC.2006.320973","DOIUrl":"https://doi.org/10.1109/CICC.2006.320973","url":null,"abstract":"This paper presents a new programmable delay-locked loop based frequency multiplier with a period error compensation loop (PECL) designed to reduce the output spurious power level. The low bandwidth auxiliary PECL compensates the output period error caused by the in-lock errors from various noise sources. By employing a novel switching control scheme, the circuit is capable of locking to frequencies either above or below the start up frequency without initialization. Programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 900 MHz to 2.9 GHz. The circuit is implemented in TSMC 0.18mum CMOS technology and measured with the reference signal from an RF signal generator. A 23 dB spur reduction from -23dB to -46.5dB at 1.216GHz is observed from the measurement results. The measured cycle-to-cycle timing jitter at 2.16GHz is 1.6ps (rms) and 12.9 ps (pk-pk), and the measured phase noise is -110 dBc/Hz at 100 kHz offset with a power consumption of 19.8 mW at a 1.8 V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133898467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320819
I. Arsovski, R. Wistort
A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V
{"title":"Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories","authors":"I. Arsovski, R. Wistort","doi":"10.1109/CICC.2006.320819","DOIUrl":"https://doi.org/10.1109/CICC.2006.320819","url":null,"abstract":"A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation. When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%. The self-referenced sensing scheme (SRSS) is used to implement the search operation in content-addressable memory (CAM) testchip. Fabricated in 1V 65nm CMOS, this scheme achieves a 0.6ns search time on a 70bit sense-line while consuming only 0.99 fJ/bit/search. Measured search access time on a five bank 64times240bit ternary CAM including selective precharge is 2.2ns. Measured power consumption at 450MHz is 10mW. Hardware shows robust search operation over a voltage range of 0.6V to 1.7V","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132944773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320903
Shoushun Chen, A. Bermak, Wang Yan, D. Martinez
In this paper, a CMOS image sensor with on-chip compression processor is proposed. An adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing is proposed enabling low power, robust and compact image compression processor. The image sensor chip has been implemented using 0.35 mu CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 BPP, while maintaining reasonable PSNR levels and very low operating power consumption
本文提出了一种带有片上压缩处理器的CMOS图像传感器。提出了一种基于边界自适应过程和在线象限树分解处理的自适应量化方案，使图像压缩处理器具有低功耗、鲁棒性和紧凑性。该图像传感器芯片采用0.35 mu CMOS技术实现，工作电压为3.3 V。仿真和实验结果表明，在保持合理的PSNR水平和极低的运行功耗的情况下，压缩数字对应于0.6-0.8 BPP
{"title":"A CMOS Image Sensor with combined adaptive-quantization and QTD-based on-chip compression processor","authors":"Shoushun Chen, A. Bermak, Wang Yan, D. Martinez","doi":"10.1109/CICC.2006.320903","DOIUrl":"https://doi.org/10.1109/CICC.2006.320903","url":null,"abstract":"In this paper, a CMOS image sensor with on-chip compression processor is proposed. An adaptive quantization scheme based on boundary adaptation procedure followed by an on-line quadrant tree decomposition processing is proposed enabling low power, robust and compact image compression processor. The image sensor chip has been implemented using 0.35 mu CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 BPP, while maintaining reasonable PSNR levels and very low operating power consumption","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133218573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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