Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320877
B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, P. Kinget
A fully integrated 0.024mm2 differentially tuned 6GHz LC VCO for 6+Gbps high speed serial (HSS) links in a 90nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO's CM. Using a differential control a very wide tuning range from 4.5GHz to 7.1GHz (45%) is achieved. The VCO has a measured phase noise of -117.7dBc/Hz at a 3MHz offset from a 5.63GHz carrier while dissipating 14mW from a 1.6V supply
{"title":"An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback","authors":"B. Soltanian, H. Ainspan, W. Rhee, D. Friedman, P. Kinget","doi":"10.1109/CICC.2006.320877","DOIUrl":"https://doi.org/10.1109/CICC.2006.320877","url":null,"abstract":"A fully integrated 0.024mm2 differentially tuned 6GHz LC VCO for 6+Gbps high speed serial (HSS) links in a 90nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO's CM. Using a differential control a very wide tuning range from 4.5GHz to 7.1GHz (45%) is achieved. The VCO has a measured phase noise of -117.7dBc/Hz at a 3MHz offset from a 5.63GHz carrier while dissipating 14mW from a 1.6V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116970959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320984
M. Bocchi, Mario de Dominicis, C. Mucci, A. Deledda, F. Campi, Andrea Lodi, M. Toma, R. Guerrieri
This paper introduces a novel heterogeneous shared memory multiprocessor architecture based on a reconfigurable processor and a standard RISC processor. The work aims at increasing further the computational density of a reconfigurable device by the integration of the reconfigurable hardware into a heterogeneous multi-core architecture. Though a RISC processor has a lower inner computational density than a reconfigurable processor, this work demonstrates that coupling a reconfigurable core to a RISC core leads to a computational density increase by a factor of up to 1.7times on signal processing applications. Moreover, this approach also achieves up to 37% energy savings on the same applications. The multi-core SoC architecture was implemented in 0.13mum technology, achieving a 166MHz clock frequency with an average 340mW power consumption
{"title":"Design and implementation of a reconfigurable heterogeneous multiprocessor SoC","authors":"M. Bocchi, Mario de Dominicis, C. Mucci, A. Deledda, F. Campi, Andrea Lodi, M. Toma, R. Guerrieri","doi":"10.1109/CICC.2006.320984","DOIUrl":"https://doi.org/10.1109/CICC.2006.320984","url":null,"abstract":"This paper introduces a novel heterogeneous shared memory multiprocessor architecture based on a reconfigurable processor and a standard RISC processor. The work aims at increasing further the computational density of a reconfigurable device by the integration of the reconfigurable hardware into a heterogeneous multi-core architecture. Though a RISC processor has a lower inner computational density than a reconfigurable processor, this work demonstrates that coupling a reconfigurable core to a RISC core leads to a computational density increase by a factor of up to 1.7times on signal processing applications. Moreover, this approach also achieves up to 37% energy savings on the same applications. The multi-core SoC architecture was implemented in 0.13mum technology, achieving a 166MHz clock frequency with an average 340mW power consumption","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115760165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320932
Jinsook Kim, W. Ni, E. Kan
We report efficient crosstalk and signal reflection reduction with nonlinear transmission lines (NLTLs) for high-speed VLSI. Crosstalk measurements of NLTLs implemented with the Lincoln Lab 0.18mum FDSOI (fully-depleted silicon-on-insulator) CMOS process are performed in time domain as well as by S-parameters up to 25GHz. The excellent suppression capabilities on signal reflection, data-dependent timing errors and crosstalk without any circuit overheads in a broadband illustrate the advantage of the NLTL global interconnect
我们报告了高速VLSI中非线性传输线(NLTLs)的有效串扰和信号反射减少。采用林肯实验室0.18 μ m FDSOI(完全耗尽绝缘体上硅)CMOS工艺实现的nltl串扰测量在时域和s参数高达25GHz的情况下进行。对信号反射、数据相关时序误差和串扰的出色抑制能力，在宽带中没有任何电路开销，说明了NLTL全局互连的优势
{"title":"Crosstalk Reduction with Nonlinear Transmission Lines for High-Speed VLSI System","authors":"Jinsook Kim, W. Ni, E. Kan","doi":"10.1109/CICC.2006.320932","DOIUrl":"https://doi.org/10.1109/CICC.2006.320932","url":null,"abstract":"We report efficient crosstalk and signal reflection reduction with nonlinear transmission lines (NLTLs) for high-speed VLSI. Crosstalk measurements of NLTLs implemented with the Lincoln Lab 0.18mum FDSOI (fully-depleted silicon-on-insulator) CMOS process are performed in time domain as well as by S-parameters up to 25GHz. The excellent suppression capabilities on signal reflection, data-dependent timing errors and crosstalk without any circuit overheads in a broadband illustrate the advantage of the NLTL global interconnect","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"24 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114096690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321005
Hong Yu, R. Bashirullah
This paper describes a low power clock and data recovery (CDR) circuit with integrated ASK demodulator for wireless implantable neural recording microsystems. A modulation scheme based on amplitude shift-keying (ASK) and pulse position modulation (PPM) is employed to simplify the complexity of implant circuits and reduce power transmission requirements. A charge-pump based CDR circuit is used to extract non-return to zero data from the demodulated waveforms. A prototype has been fabricated in 2-poly 3-metal 0.6mum bulk CMOS technology in order to validate circuit functionality. The receiver front-end exhibits a sensitivity of 3.2mV p-p at 1MHz. The ASK demodulator and CDR operates over an input data range of 4kbs to 18kbs, measures 300pm by 600pm and dissipates 70pW from a 2.7V supply
{"title":"A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics","authors":"Hong Yu, R. Bashirullah","doi":"10.1109/CICC.2006.321005","DOIUrl":"https://doi.org/10.1109/CICC.2006.321005","url":null,"abstract":"This paper describes a low power clock and data recovery (CDR) circuit with integrated ASK demodulator for wireless implantable neural recording microsystems. A modulation scheme based on amplitude shift-keying (ASK) and pulse position modulation (PPM) is employed to simplify the complexity of implant circuits and reduce power transmission requirements. A charge-pump based CDR circuit is used to extract non-return to zero data from the demodulated waveforms. A prototype has been fabricated in 2-poly 3-metal 0.6mum bulk CMOS technology in order to validate circuit functionality. The receiver front-end exhibits a sensitivity of 3.2mV p-p at 1MHz. The ASK demodulator and CDR operates over an input data range of 4kbs to 18kbs, measures 300pm by 600pm and dissipates 70pW from a 2.7V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114353806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320884
S. Tiwary, Rob A. Rutenbar
Trajectory methods offer an attractive methodology for automated extraction of macromodels from a set of training simulations. A pervasive concern with models based on regression is the lack of certainty about where they fit correctly. The authors show how the unique structure of a scalable trajectory model allows it to monitor the "fidelity" of the fit automatically, and flag where additional model training is warranted. Experimental results demonstrate this self-monitoring ability in practical circuit examples
{"title":"On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels","authors":"S. Tiwary, Rob A. Rutenbar","doi":"10.1109/CICC.2006.320884","DOIUrl":"https://doi.org/10.1109/CICC.2006.320884","url":null,"abstract":"Trajectory methods offer an attractive methodology for automated extraction of macromodels from a set of training simulations. A pervasive concern with models based on regression is the lack of certainty about where they fit correctly. The authors show how the unique structure of a scalable trajectory model allows it to monitor the \"fidelity\" of the fit automatically, and flag where additional model training is warranted. Experimental results demonstrate this self-monitoring ability in practical circuit examples","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320975
R. Barnett, Jin Liu
A 0.8V nano-power relaxation oscillator for EPC standard UHF RFID transponder is presented. A low-voltage inverted mirror feedback VGS/R reference is proposed to provide correlated current and voltage references for the oscillator. As a result, the oscillator frequency is solely determined by the resistor in the reference and the timing capacitor to meet the frequency tolerance specification. Meanwhile, to minimize the power consumption, a minimum-supply-voltage-constraint (MSVC) design criterion is proposed to minimize the required supply voltage. The inverted mirror feedback technique reduces the headroom requirement of the traditional VGS /R to meet the MSVC. Measurement results show that the entire oscillator requires a minimum supply voltage of 0.8V in the prototype chip fabricated in CMOS 0.13mum technologies. The measured oscillation frequency is 1.52MHz with 400nA total current consumption. The chip area is 13400mum2
{"title":"A 0.8V 1.52MHz MSVC Relaxation Oscillator with Inverted Mirror Feedback Reference for UHF RFID","authors":"R. Barnett, Jin Liu","doi":"10.1109/CICC.2006.320975","DOIUrl":"https://doi.org/10.1109/CICC.2006.320975","url":null,"abstract":"A 0.8V nano-power relaxation oscillator for EPC standard UHF RFID transponder is presented. A low-voltage inverted mirror feedback VGS/R reference is proposed to provide correlated current and voltage references for the oscillator. As a result, the oscillator frequency is solely determined by the resistor in the reference and the timing capacitor to meet the frequency tolerance specification. Meanwhile, to minimize the power consumption, a minimum-supply-voltage-constraint (MSVC) design criterion is proposed to minimize the required supply voltage. The inverted mirror feedback technique reduces the headroom requirement of the traditional VGS /R to meet the MSVC. Measurement results show that the entire oscillator requires a minimum supply voltage of 0.8V in the prototype chip fabricated in CMOS 0.13mum technologies. The measured oscillation frequency is 1.52MHz with 400nA total current consumption. The chip area is 13400mum2","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121784312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320845
N. Lu
We describe an innovative and comprehensive interconnect Spice model for IBM 65 nm technology. The model links the variability in the model to the variations in BEOL litho, deposition, etch, and polish process steps, which is an industry first. It provides correct Monte Carlo simulation results, offers correct corner modeling capability, and can also generates a set of optimal interconnect corner models instantly without running Monte Carlo simulations, which is another industry first
{"title":"Statistical and Corner Modeling of Interconnect Resistance and Capacitance","authors":"N. Lu","doi":"10.1109/CICC.2006.320845","DOIUrl":"https://doi.org/10.1109/CICC.2006.320845","url":null,"abstract":"We describe an innovative and comprehensive interconnect Spice model for IBM 65 nm technology. The model links the variability in the model to the variations in BEOL litho, deposition, etch, and polish process steps, which is an industry first. It provides correct Monte Carlo simulation results, offers correct corner modeling capability, and can also generates a set of optimal interconnect corner models instantly without running Monte Carlo simulations, which is another industry first","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"662 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320849
S. Akhtar, M. Ipek, J. Lin, R. Staszewski, P. Litmanen
We present the first published implementation and measurements of a fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO) providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data and a switched inverter divider. The complete chip, with integrated LDOs, consumes 20mA from a 1.4V supply while providing a PN of -157dBc/Hz at a 40MHz offset for a 2GHz output
{"title":"Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS","authors":"S. Akhtar, M. Ipek, J. Lin, R. Staszewski, P. Litmanen","doi":"10.1109/CICC.2006.320849","DOIUrl":"https://doi.org/10.1109/CICC.2006.320849","url":null,"abstract":"We present the first published implementation and measurements of a fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO) providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data and a switched inverter divider. The complete chip, with integrated LDOs, consumes 20mA from a 1.4V supply while providing a PN of -157dBc/Hz at a 40MHz offset for a 2GHz output","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320909
Xiangtao Li, W. Kuo, Yuan Lu, J. Cressler
This paper presents a monolithic continuous-time 2nd-order analog-to-digital sigma-delta modulator implemented in third-generation, 200 GHz SiGe HBT technology. The modulator can operate at a sampling rate of 20 GS/sec with SNRs of 30.5 dB over a signal band from DC to 312.5 MHz, and 51 dB over 1 MHz bandwidth. Operating off a +3.5 V power supply, the modulator dissipates a total of 490 mW. The die occupies an area of 1.58 times 1.7 mm2
{"title":"A 20 GS/sec Analog-to-Digital Sigma-Delta Modulator in SiGe HBT Technology","authors":"Xiangtao Li, W. Kuo, Yuan Lu, J. Cressler","doi":"10.1109/CICC.2006.320909","DOIUrl":"https://doi.org/10.1109/CICC.2006.320909","url":null,"abstract":"This paper presents a monolithic continuous-time 2nd-order analog-to-digital sigma-delta modulator implemented in third-generation, 200 GHz SiGe HBT technology. The modulator can operate at a sampling rate of 20 GS/sec with SNRs of 30.5 dB over a signal band from DC to 312.5 MHz, and 51 dB over 1 MHz bandwidth. Operating off a +3.5 V power supply, the modulator dissipates a total of 490 mW. The die occupies an area of 1.58 times 1.7 mm2","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"734 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131425507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320857
K. Tang, R. M. Goodman
An electronic nose chip which uses three carbon black polymer sensors as its input is fabricated and tested. Results of longitudinal testing, response to analyte mixtures, temperature dependence, and power dissipation are discussed in the paper. Future work towards a fully integrated wearable electronic nose chip is discussed at the end of the paper
{"title":"Towards a Wearable Electronic Nose Chip","authors":"K. Tang, R. M. Goodman","doi":"10.1109/CICC.2006.320857","DOIUrl":"https://doi.org/10.1109/CICC.2006.320857","url":null,"abstract":"An electronic nose chip which uses three carbon black polymer sensors as its input is fabricated and tested. Results of longitudinal testing, response to analyte mixtures, temperature dependence, and power dissipation are discussed in the paper. Future work towards a fully integrated wearable electronic nose chip is discussed at the end of the paper","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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