Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519745
P. Franco, E. McCluskey
A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.
{"title":"DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS","authors":"P. Franco, E. McCluskey","doi":"10.1109/TEST.1991.519745","DOIUrl":"https://doi.org/10.1109/TEST.1991.519745","url":null,"abstract":"A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519738
Jaushin Lee, J. Patel
In this paper, an ATF’G methodology working at an architectural level is proposed. For the data path portion, the hierarchy of the design is exploited and the dependence on the gate level information is relieved. For the conb’oi faults, gate level algorithms are incorporated with high level approaches to excite the fault and differentiate the fault effect to primary outputs. Due to the fault collapsing effect arid the fault differentiation process, several data types have been defined for the manipulation alf all possible fault e€fects. A functional equivalent model is used for sequential modules, which makes this technique extendable beyond the register-transfer level. The backtracking mechanism used in the control unit has been carefully modified to ensure a complete finite space searching. Some experimerrtal results are presented to show the effectiveness of this approach.
{"title":"ARTEST: AN ARCHITECTURAL LEVEL TEST GENERATOR FOR DATA PATH FAULTS AND CONTROL FAULTS","authors":"Jaushin Lee, J. Patel","doi":"10.1109/TEST.1991.519738","DOIUrl":"https://doi.org/10.1109/TEST.1991.519738","url":null,"abstract":"In this paper, an ATF’G methodology working at an architectural level is proposed. For the data path portion, the hierarchy of the design is exploited and the dependence on the gate level information is relieved. For the conb’oi faults, gate level algorithms are incorporated with high level approaches to excite the fault and differentiate the fault effect to primary outputs. Due to the fault collapsing effect arid the fault differentiation process, several data types have been defined for the manipulation alf all possible fault e€fects. A functional equivalent model is used for sequential modules, which makes this technique extendable beyond the register-transfer level. The backtracking mechanism used in the control unit has been carefully modified to ensure a complete finite space searching. Some experimerrtal results are presented to show the effectiveness of this approach.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131182738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519716
J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama
To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.
{"title":"Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme","authors":"J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama","doi":"10.1109/TEST.1991.519716","DOIUrl":"https://doi.org/10.1109/TEST.1991.519716","url":null,"abstract":"To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519503
P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos
&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.
本文展示了边界扫描和伪随机BIST(内置自我测试)方法的特点如何很好地结合在一起，在专用于电信的VLSI电路上实现。所选择的电路是一个由35万个晶体管组成的0.7 p CMOS异步传输模式(ATAI)开关，用于16 x 16 ATM交换矩阵，能够以高达1.244 gbit / s的通流率运行。首先，给出了标称电路。然后回顾了常用的测试方法，讨论了测试中遇到的主要问题。最后给出了具体的结果，验证了所选方法及其在大型电路中的应用。
{"title":"IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH","authors":"P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos","doi":"10.1109/TEST.1991.519503","DOIUrl":"https://doi.org/10.1109/TEST.1991.519503","url":null,"abstract":"&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114135689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519758
Lawrence P. Holmquist, L. Kinney
A methodology is developed using convolutional codes for on-line detection of sequencing errors in sequential circuits induced by any given set of transient faults. Key outputs are added to the machine. In the casc of microprogrammed control units, key bits are appended to each microinstruction. The keys are chosen such that all sequences of key outputs are code sequences in a convolutional code. Using an error-detecting decoder for the code, all transient sequencing errors resulting from faults in the fault set can be detected with latency not exceeding the latency distance of the convolutional code.
{"title":"CONCURRENT ERROR DETECTION FOR RESTRICTED FAULT SETS IN SEQUENTIAL CIRCUITS AND MICROPROGRAMMED CONT","authors":"Lawrence P. Holmquist, L. Kinney","doi":"10.1109/TEST.1991.519758","DOIUrl":"https://doi.org/10.1109/TEST.1991.519758","url":null,"abstract":"A methodology is developed using convolutional codes for on-line detection of sequencing errors in sequential circuits induced by any given set of transient faults. Key outputs are added to the machine. In the casc of microprogrammed control units, key bits are appended to each microinstruction. The keys are chosen such that all sequences of key outputs are code sequences in a convolutional code. Using an error-detecting decoder for the code, all transient sequencing errors resulting from faults in the fault set can be detected with latency not exceeding the latency distance of the convolutional code.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519751
A. Lioy
Recognition of test equivalent faults is usually applied to reduce the number of target faults for test generation and fault simulation. Also fault diagnosis benefits from this knowledge as it allows fast dropping of undistinguishable faults. Equivalent faults are generally identified by mean of a structural analysis of the circuit. Functionally equivalent faults are not considered as their identification is computationally too expensive for real circuits. This paper presents new theorems about functional fault equivalence and dominance. They provide a constructive basis upon which a functional fault collapsing algorithm is built. Application to a set of benchmark circuits establish that identification of functionally equivalent faults is feasible, and that their number may be a not negligible fraction of the faults in a circuit. Results apply both to combinational and synchronous sequential circuits.
{"title":"Looking for Functional Fault Equivalence","authors":"A. Lioy","doi":"10.1109/TEST.1991.519751","DOIUrl":"https://doi.org/10.1109/TEST.1991.519751","url":null,"abstract":"Recognition of test equivalent faults is usually applied to reduce the number of target faults for test generation and fault simulation. Also fault diagnosis benefits from this knowledge as it allows fast dropping of undistinguishable faults. Equivalent faults are generally identified by mean of a structural analysis of the circuit. Functionally equivalent faults are not considered as their identification is computationally too expensive for real circuits. This paper presents new theorems about functional fault equivalence and dominance. They provide a constructive basis upon which a functional fault collapsing algorithm is built. Application to a set of benchmark circuits establish that identification of functionally equivalent faults is feasible, and that their number may be a not negligible fraction of the faults in a circuit. Results apply both to combinational and synchronous sequential circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519705
Sally Wilk
This paper describes a Statistical Process Control (SPC) application to a WSI testec The application reviewed provides an accurate monitor of tester reliability as reported through stability, repeatability, and accuracy metrics using a calibrated external instrument. This SPC process conforms to MIL-M-38510 requirements.
{"title":"EFFECTIVE IMPLEMENTATION OF STATISTICAL PROCESS CONTROL IN AN INTEGRATED CIRCUIT TEST ENVIRONMENT","authors":"Sally Wilk","doi":"10.1109/TEST.1991.519705","DOIUrl":"https://doi.org/10.1109/TEST.1991.519705","url":null,"abstract":"This paper describes a Statistical Process Control (SPC) application to a WSI testec The application reviewed provides an accurate monitor of tester reliability as reported through stability, repeatability, and accuracy metrics using a calibrated external instrument. This SPC process conforms to MIL-M-38510 requirements.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123885178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519720
G. Stenbakken, T., Michael Souders
Techniquesare presented for developinglinear error models for analog and mixed-signal devices. Methods for choosingparameters and assuring the models are complete and wellconditioned, are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices.
{"title":"LINEAR ERROR MODELING OF ANALOG AND MIXED-SIGNAL DEVICES","authors":"G. Stenbakken, T., Michael Souders","doi":"10.1109/TEST.1991.519720","DOIUrl":"https://doi.org/10.1109/TEST.1991.519720","url":null,"abstract":"Techniquesare presented for developinglinear error models for analog and mixed-signal devices. Methods for choosingparameters and assuring the models are complete and wellconditioned, are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519721
A. Chatterjee
In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.
{"title":"CONCURRENT ERROR DETECTION IN LINEAR ANALOG AND SWITCHED-CAPACITOR STATE VARIABLE SYSTEMS USING CONT","authors":"A. Chatterjee","doi":"10.1109/TEST.1991.519721","DOIUrl":"https://doi.org/10.1109/TEST.1991.519721","url":null,"abstract":"In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519740
B. Murray, J. Hayes
Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.
{"title":"Test Propagation Through Modules and Circuits","authors":"B. Murray, J. Hayes","doi":"10.1109/TEST.1991.519740","DOIUrl":"https://doi.org/10.1109/TEST.1991.519740","url":null,"abstract":"Test generation performance can be improved significantly over conventional techniques by combining precomputed module tests to form a test for a complete circuit. We introduce a theory of propagation for modules and circuits which can be used for hierarchical test generation and design for testability. The propagation characteristics of a module - whether it can be sensitized to propagate some or all possible fault effects on an input bus - are represented by structures called ambiguity sets. Algebraic operations are performed on ambiguity sets to determine the propagation characteristics of multi-module circuits. We show how this propagation theory is used in test generation and also to aid in designing circuits suitable for high-level test generation.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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