Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519716
J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama
To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.
{"title":"Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme","authors":"J. Miyamoto, N. Ohtsuka, K. Imamiya, N. Tomita, Y. Iyama","doi":"10.1109/TEST.1991.519716","DOIUrl":"https://doi.org/10.1109/TEST.1991.519716","url":null,"abstract":"To reject defective cells and to guarantee device reliability in a short time, internal test circuits have been implemented in non-volatile memories. On the other hand, for high density EPROMs, implementing column redundancy scheme is of vital importance in order to obtain a reasonable yield, as inter-connection design rules are limiting the cell size. However, the conventional column redundancy scheme was not very efficient, because the test circuits did not work well for one of the most dominant failures on miniaturized cells. This paper proposes a new test algorithm, multi-step stress test to solve the problem. The concept has been applied to an actual 16Mbit EPROM, and the yield has been improved to almost double that at the time of the initial developing stage.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519509
J. Giraldi, M. Bushnell
We present new extensions to the EST' algoritlm, which accelerates combinational circuit Redundancy Identification and Automatic Test Pattern Generation (ATPG) algorithms, in particular SOCRATES. EST detects equivalent search states, which are saved. for all faults during ATPG. The search space is reduced by using learned Search State equiualences to detect previously-encountered search states (possibly from prior faults) and to make internal node assignments. We present two extensions to EST. The first ensures that each portion of the ATPG search space is explored only once. The second applies headline objectives in parallel, rather than serially. For the 1965 ISCAS combinational benchmarks, EST accelerates S 0 CRATES by 6.53 times, when all faults are targeted, and by 5.51 times, when used with random pattern generation, f,iult simulation and fault dropping. This acceleration was achieved with minimal memory overhead.
{"title":"SEARCH STATE EQUIVALENCE FOR REDUNDANCY IDENTIFICATION AND TEST GENERATION","authors":"J. Giraldi, M. Bushnell","doi":"10.1109/TEST.1991.519509","DOIUrl":"https://doi.org/10.1109/TEST.1991.519509","url":null,"abstract":"We present new extensions to the EST' algoritlm, which accelerates combinational circuit Redundancy Identification and Automatic Test Pattern Generation (ATPG) algorithms, in particular SOCRATES. EST detects equivalent search states, which are saved. for all faults during ATPG. The search space is reduced by using learned Search State equiualences to detect previously-encountered search states (possibly from prior faults) and to make internal node assignments. We present two extensions to EST. The first ensures that each portion of the ATPG search space is explored only once. The second applies headline objectives in parallel, rather than serially. For the 1965 ISCAS combinational benchmarks, EST accelerates S 0 CRATES by 6.53 times, when all faults are targeted, and by 5.51 times, when used with random pattern generation, f,iult simulation and fault dropping. This acceleration was achieved with minimal memory overhead.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127559143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519745
P. Franco, E. McCluskey
A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.
{"title":"DELAY TESTING OF DIGITAL CIRCUITS BY OUTPUT WAVEFORM ANALYSIS","authors":"P. Franco, E. McCluskey","doi":"10.1109/TEST.1991.519745","DOIUrl":"https://doi.org/10.1109/TEST.1991.519745","url":null,"abstract":"A new method for delay fault testing of digital circuits is presented. Unlike catastrophic failures that simply have incorrect steady-state logic values at the circuit outputs, delay faults change the shape of the output waveforms by moving the signal transitions in time. Therefore, since the output waveforms contain information about the circuit delays, instead of only latching the outputs at the sampling time, the output waveforms between samples are analyzed as well. Two classes of output waveform analysis are discussed. In the first technique, the output waveform is observed for any changes after the sampling time, since in a fault-free circuit, the outputs are expected to have stabilized at the desired logic values. In the second technique, information is extracted from the faulty and fault-free waveforms before the sampling time, and compared for any differences. Circuits for the waveform analyzers are presented to show that the method is feasible, and experimental results are given.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519758
Lawrence P. Holmquist, L. Kinney
A methodology is developed using convolutional codes for on-line detection of sequencing errors in sequential circuits induced by any given set of transient faults. Key outputs are added to the machine. In the casc of microprogrammed control units, key bits are appended to each microinstruction. The keys are chosen such that all sequences of key outputs are code sequences in a convolutional code. Using an error-detecting decoder for the code, all transient sequencing errors resulting from faults in the fault set can be detected with latency not exceeding the latency distance of the convolutional code.
{"title":"CONCURRENT ERROR DETECTION FOR RESTRICTED FAULT SETS IN SEQUENTIAL CIRCUITS AND MICROPROGRAMMED CONT","authors":"Lawrence P. Holmquist, L. Kinney","doi":"10.1109/TEST.1991.519758","DOIUrl":"https://doi.org/10.1109/TEST.1991.519758","url":null,"abstract":"A methodology is developed using convolutional codes for on-line detection of sequencing errors in sequential circuits induced by any given set of transient faults. Key outputs are added to the machine. In the casc of microprogrammed control units, key bits are appended to each microinstruction. The keys are chosen such that all sequences of key outputs are code sequences in a convolutional code. Using an error-detecting decoder for the code, all transient sequencing errors resulting from faults in the fault set can be detected with latency not exceeding the latency distance of the convolutional code.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123252411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519522
C. Henderson, J. Soden, C. Hawkins
The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.
{"title":"THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS","authors":"C. Henderson, J. Soden, C. Hawkins","doi":"10.1109/TEST.1991.519522","DOIUrl":"https://doi.org/10.1109/TEST.1991.519522","url":null,"abstract":"The electrical and test properties of several logic gate open circuit defect structures were measured. Results indicate that tunneling current across fine geometry discontinuities enables low frequency operation of ICs. No significant capacitive coupling was observed for adjacent metal interconnect or for large metal opens on the gate interconnects. These results indicate the need for different methods of open circuit defect detection during test. I. Introduct ion Structured test methods require thorough knowledge of the defects that cause failure. This study presents data on the electrical characteristics of a common CMOS IC defect, an input open circuit to a logic gate. Individual transistor gate terminal opens are not considered. Data show that logic gate input open circuit defects for narrow interconnect discontinuities allow circuit functionality at frequencies from DC into the MHz region. Evidence supports electron tunneling as the basic mechanism for circuit functionality in the presence of this type of defect. This suggests that the open-circuited logic gate defect should be treated as a delay fault in order to guarantee detection. Open circuit defects with wide dimensions exhibited no signal coupling. Data also show the conditions under which quiescent power supply current (IDD,) tests can detect open circuit logic gate inputs. In the late 1980s two groups fabricated circuits or tested existing circuits with specific types of open circuits [l, 21. Others studied transistor-level open circuit phenomena and proposed design changes to reduce the occurrence of opens [3, 41. It was demonstrated that some open circuits are not detected by conventional stuck-at test methodologies.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128531072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519695
P. Maxwell, R. Aitken, V. Johansen, I. Chiang
This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.
{"title":"THE EFFECT OF DIFFERENT TEST SETS ON QUALITY LEVEL PREDICTION: WHEN IS 80% BETTER THAN 90%?","authors":"P. Maxwell, R. Aitken, V. Johansen, I. Chiang","doi":"10.1109/TEST.1991.519695","DOIUrl":"https://doi.org/10.1109/TEST.1991.519695","url":null,"abstract":"This paper discusses the use of stuck-at fault coverage as a means of determining quality levels. Data from a part tested with both functional and scan tests is analyzed and compared to three existing theories. It is shown that reasonable predictions of quality level are possible for the functional tests, but that scan tests produce significantly worse quality levels than predicted, Apparent clustering of defects resulted in very good quality levels for fault coverages less than 99%.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124329193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519751
A. Lioy
Recognition of test equivalent faults is usually applied to reduce the number of target faults for test generation and fault simulation. Also fault diagnosis benefits from this knowledge as it allows fast dropping of undistinguishable faults. Equivalent faults are generally identified by mean of a structural analysis of the circuit. Functionally equivalent faults are not considered as their identification is computationally too expensive for real circuits. This paper presents new theorems about functional fault equivalence and dominance. They provide a constructive basis upon which a functional fault collapsing algorithm is built. Application to a set of benchmark circuits establish that identification of functionally equivalent faults is feasible, and that their number may be a not negligible fraction of the faults in a circuit. Results apply both to combinational and synchronous sequential circuits.
{"title":"Looking for Functional Fault Equivalence","authors":"A. Lioy","doi":"10.1109/TEST.1991.519751","DOIUrl":"https://doi.org/10.1109/TEST.1991.519751","url":null,"abstract":"Recognition of test equivalent faults is usually applied to reduce the number of target faults for test generation and fault simulation. Also fault diagnosis benefits from this knowledge as it allows fast dropping of undistinguishable faults. Equivalent faults are generally identified by mean of a structural analysis of the circuit. Functionally equivalent faults are not considered as their identification is computationally too expensive for real circuits. This paper presents new theorems about functional fault equivalence and dominance. They provide a constructive basis upon which a functional fault collapsing algorithm is built. Application to a set of benchmark circuits establish that identification of functionally equivalent faults is feasible, and that their number may be a not negligible fraction of the faults in a circuit. Results apply both to combinational and synchronous sequential circuits.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"36 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519510
I. Pomeranz, L. Reddy, S. Reddy
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >
{"title":"COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS","authors":"I. Pomeranz, L. Reddy, S. Reddy","doi":"10.1109/TEST.1991.519510","DOIUrl":"https://doi.org/10.1109/TEST.1991.519510","url":null,"abstract":"Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121601049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519503
P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos
&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.
本文展示了边界扫描和伪随机BIST(内置自我测试)方法的特点如何很好地结合在一起，在专用于电信的VLSI电路上实现。所选择的电路是一个由35万个晶体管组成的0.7 p CMOS异步传输模式(ATAI)开关，用于16 x 16 ATM交换矩阵，能够以高达1.244 gbit / s的通流率运行。首先，给出了标称电路。然后回顾了常用的测试方法，讨论了测试中遇到的主要问题。最后给出了具体的结果，验证了所选方法及其在大型电路中的应用。
{"title":"IMPLEMENTING BOUNDARY-SCAN AND PSEUDO-RANDOM BIST IN AN ASYNCHRONOUS TRANSFER MODE SWITCH","authors":"P. Thorel, J. Rainard, A. Botta, A. Chemarin, J. Majos","doi":"10.1109/TEST.1991.519503","DOIUrl":"https://doi.org/10.1109/TEST.1991.519503","url":null,"abstract":"&pact : This paper shows how the features of both Boundary-Scan and Pseudo-Random BIST (Built-In Self Test) approaches go well together, implemented on a VLSI circuit devoted to telecommunications. The chosen circuit is a 0.7 p CMOS Asynchronous Transfer Mode (ATAI) switch of 350,000 transistors, for use in a 16 x 16 ATM Switching Matrix able to run at a throughpuu rate of up to 1.244 Gbitls. First, the nominal circuit is presented. Then the test approaches used are evoked, before discussing the main test problems encountered. The paper concludes with concrete results, validating tk chosen approaches and their applications in such a large circuit.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"18 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114135689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-10-26DOI: 10.1109/TEST.1991.519713
R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio
Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.
{"title":"CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS","authors":"R. Rodríguez-Montañés, J. Segura, V. Champac, J. Figueras, J. A. Rubio","doi":"10.1109/TEST.1991.519713","DOIUrl":"https://doi.org/10.1109/TEST.1991.519713","url":null,"abstract":"Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.","PeriodicalId":272630,"journal":{"name":"1991, Proceedings. International Test Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114582005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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