In this work, we describe an effective and simple method for surface patterning of 3D objects with antireflective moth-eye structures via UV based nanoimprint lithography using soft stamps. So-called anti-reflective moth-eye structures are subwavelength nanostructures that can reduce the reflection of surfaces over the entire visible spectrum of light. Such broadband antireflective coatings are especially interesting for optical elements like lenses.
{"title":"Antireflective moth-eye structures on curved surfaces fabricated by nanoimprint lithography","authors":"M. Haslinger, A. Moharana, M. Mühlberger","doi":"10.1117/12.2535683","DOIUrl":"https://doi.org/10.1117/12.2535683","url":null,"abstract":"In this work, we describe an effective and simple method for surface patterning of 3D objects with antireflective moth-eye structures via UV based nanoimprint lithography using soft stamps. So-called anti-reflective moth-eye structures are subwavelength nanostructures that can reduce the reflection of surfaces over the entire visible spectrum of light. Such broadband antireflective coatings are especially interesting for optical elements like lenses.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127162771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Romanets, K. Ricken, M. Kupers, F. Wählisch, C. Piliego, P. Broman, D. de Graaf
The purpose of pellicles is to protect reticles from particle contamination, thus reducing the number of defects and increasing yield. In this paper we show how recent progress in pellicle technology has succeeded in solving the main challenges in imaging with EUV pellicles. We demonstrate this using the recent results of imaging tests in scanner, EUV reflectivity measurements, and lifetime testing. EUV light reflectivity of pellicles is one of the effects that have negatively impacted imaging with pellicles in the past. Light reflected from pellicles leads to the overexposure of neighboring fields in the corners and edges. Tests with pellicles produced using a new process show EUV reflectivity within specification of 0.04%, and measured impact on critical dimension in the corners below 0.15nm for multiple pellicles. Lifetime performance was tested by exposing up to 3000 wafers with a pellicle while periodically assessing the stability of imaging metrics. The lithometrics studies include: critical dimension (CD) and critical dimension uniformity (CDU), and contrast (via line width roughness). DoseMapper, which is an EUV scanner application developed to improve CDU, was applied during the lifetime test. Here we show that it can successfully reduce the pellicle-induced CDU and CDU over lifetime (previously shown to be dominated by pellicle EUV transmission drift). Our results using DoseMapper show that whilst intrafield CDU 3sigma increases over lifetime, it stays comfortably within the 1.1nm NXE3400 ATP specification using DoseMapper.
{"title":"Progress in imaging performance with EUV pellicles","authors":"O. Romanets, K. Ricken, M. Kupers, F. Wählisch, C. Piliego, P. Broman, D. de Graaf","doi":"10.1117/12.2535675","DOIUrl":"https://doi.org/10.1117/12.2535675","url":null,"abstract":"The purpose of pellicles is to protect reticles from particle contamination, thus reducing the number of defects and increasing yield. In this paper we show how recent progress in pellicle technology has succeeded in solving the main challenges in imaging with EUV pellicles. We demonstrate this using the recent results of imaging tests in scanner, EUV reflectivity measurements, and lifetime testing. EUV light reflectivity of pellicles is one of the effects that have negatively impacted imaging with pellicles in the past. Light reflected from pellicles leads to the overexposure of neighboring fields in the corners and edges. Tests with pellicles produced using a new process show EUV reflectivity within specification of 0.04%, and measured impact on critical dimension in the corners below 0.15nm for multiple pellicles. Lifetime performance was tested by exposing up to 3000 wafers with a pellicle while periodically assessing the stability of imaging metrics. The lithometrics studies include: critical dimension (CD) and critical dimension uniformity (CDU), and contrast (via line width roughness). DoseMapper, which is an EUV scanner application developed to improve CDU, was applied during the lifetime test. Here we show that it can successfully reduce the pellicle-induced CDU and CDU over lifetime (previously shown to be dominated by pellicle EUV transmission drift). Our results using DoseMapper show that whilst intrafield CDU 3sigma increases over lifetime, it stays comfortably within the 1.1nm NXE3400 ATP specification using DoseMapper.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129350931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hiromatsu, Ryo Ohkubo, Hitoshi Maeda, Toru Fukui, H. Shishido, K. Ono, M. Hashimoto
This paper shows the latest challenges facing mask blank evolution to support leading-edge lithography processes. ArF immersion lithography has been employing multi-pass exposures to exceed the physical diffraction limit. These photomasks demand very accurate overlay, higher NILS and best CD uniformity for wider process window. The subject was considered from two perspectives from a mask blank producer, which are the mask-making perspective and the wafer lithography perspective. To improve the overlay, we introduced the dedicated CDL (Charge Dissipation Layer) for improving mask registration error. From the lithography resolution perspective, we have developed a high-transmittance phase-shifter film for higher NILS. CDU stability point of view, we described “Superior pattern fidelity CAR”, “High ArF durability SiN phase-shifter” and “Transparent etching stopper”. The industry decided to move to EUV lithography. But there are still many challenges for optical lithography.
{"title":"Continuous challenges for next era of lithography","authors":"T. Hiromatsu, Ryo Ohkubo, Hitoshi Maeda, Toru Fukui, H. Shishido, K. Ono, M. Hashimoto","doi":"10.1117/12.2534910","DOIUrl":"https://doi.org/10.1117/12.2534910","url":null,"abstract":"This paper shows the latest challenges facing mask blank evolution to support leading-edge lithography processes. ArF immersion lithography has been employing multi-pass exposures to exceed the physical diffraction limit. These photomasks demand very accurate overlay, higher NILS and best CD uniformity for wider process window. The subject was considered from two perspectives from a mask blank producer, which are the mask-making perspective and the wafer lithography perspective. To improve the overlay, we introduced the dedicated CDL (Charge Dissipation Layer) for improving mask registration error. From the lithography resolution perspective, we have developed a high-transmittance phase-shifter film for higher NILS. CDU stability point of view, we described “Superior pattern fidelity CAR”, “High ArF durability SiN phase-shifter” and “Transparent etching stopper”. The industry decided to move to EUV lithography. But there are still many challenges for optical lithography.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124895768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The systematic analysis of ever-increasing data collection presents companies with ever-greater challenges. Many manufacturing organizations simply lack the know-how to handle Big Data projects and the corresponding data analysis right. Therefore one simply follows the current trends and buzz words and adopts approaches which are currently en vogue. This approach often leads to less successful projects and several regularly reoccurring patterns of misconceptions can be identified. This paper highlights some of these unsuccessful patterns and introduces some of the work done in the PRO-OPT SMART-DATA research project. The innovation in this data analysis approach is the combination of traditional statistical methods with new Big Data and AI analysis techniques applied to high tech manufacturing. Being able to align process data with the complete metrology data provides amazing new insights into the manufacturing. Furthermore, we will introduce a new visualization technique specifically suited for domains with high amounts of categorical data like semiconductor, photovoltaics, electronics and such. This paper will show how the combination of the statistical data analysis system Cornerstone in conjunction with Apache Spark1 and Apache Cassandra2 provides a good basis for engineering analytics of massive data amounts. By properly nesting the solid mathematical methods in Cornerstone with big data-appropriate infrastructure such as Apache Spark and, in our case, Apache Cassandra, many new analytics issues can be addressed. Analyzes that used to be inefficient due to the sheer volume of data in classically modeled schema’s can now be performed through appropriate big-table modeling and provide the ability to provide completely new insights into production data. Those directly impacted the manufacturing procedures and improved the products quality and reliability. Experiences gained in the project impacted the upcoming VDI/VDE guideline 37143 to be published later in the year 2019.
{"title":"Applying big data technologies to high tech manufacturing","authors":"D. Ortloff, Nils Knoblauch","doi":"10.1117/12.2535589","DOIUrl":"https://doi.org/10.1117/12.2535589","url":null,"abstract":"The systematic analysis of ever-increasing data collection presents companies with ever-greater challenges. Many manufacturing organizations simply lack the know-how to handle Big Data projects and the corresponding data analysis right. Therefore one simply follows the current trends and buzz words and adopts approaches which are currently en vogue. This approach often leads to less successful projects and several regularly reoccurring patterns of misconceptions can be identified. This paper highlights some of these unsuccessful patterns and introduces some of the work done in the PRO-OPT SMART-DATA research project. The innovation in this data analysis approach is the combination of traditional statistical methods with new Big Data and AI analysis techniques applied to high tech manufacturing. Being able to align process data with the complete metrology data provides amazing new insights into the manufacturing. Furthermore, we will introduce a new visualization technique specifically suited for domains with high amounts of categorical data like semiconductor, photovoltaics, electronics and such. This paper will show how the combination of the statistical data analysis system Cornerstone in conjunction with Apache Spark1 and Apache Cassandra2 provides a good basis for engineering analytics of massive data amounts. By properly nesting the solid mathematical methods in Cornerstone with big data-appropriate infrastructure such as Apache Spark and, in our case, Apache Cassandra, many new analytics issues can be addressed. Analyzes that used to be inefficient due to the sheer volume of data in classically modeled schema’s can now be performed through appropriate big-table modeling and provide the ability to provide completely new insights into production data. Those directly impacted the manufacturing procedures and improved the products quality and reliability. Experiences gained in the project impacted the upcoming VDI/VDE guideline 37143 to be published later in the year 2019.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124085142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Zahlten, P. Gräupner, J. van Schoot, P. Kürz, J. Stoeldraijer, W. Kaiser
EUV technology with its state-of-the-art tool generation equipped with a Numerical Aperture (NA) of 0.33 and providing 13 nm resolution is on the brink of entering high volume manufacturing. Extending the roadmap down to a resolution of 8 nm requires a high-NA successor tool. ASML and ZEISS are jointly developing an EUV scanner system with an NA of 0.55 to enable the continuation of Moore’s law throughout the next decade. In this paper we motivate the top-level requirements of this high-NA tool, deduce implications on system design and present how they are solved in the tool. In particular, we address implications of the high-NA leading to large mirror sizes, introduction of a central obscuration and an anamorphic lens design resulting in the transition from full to half field. A consequence of the high-NA is a reduced depth of focus which is dealt with by an improved focus control of the system. The aberration level of the high-NA tool will be significantly reduced w.r.t. the NA 0.33 tool generation. This is achieved by extreme aspheres accompanied by an advanced mirror manufacturing process with corrections down to atomic scale. To enable mirror manufacturing to this precision the limits of mirror metrology are pushed out by transferring the whole measurement process into vacuum. Finally, we will give an update on the current status of the high-NA tool development and the build-up of the necessary infrastructure.
{"title":"High-NA EUV lithography: pushing the limits","authors":"C. Zahlten, P. Gräupner, J. van Schoot, P. Kürz, J. Stoeldraijer, W. Kaiser","doi":"10.1117/12.2536469","DOIUrl":"https://doi.org/10.1117/12.2536469","url":null,"abstract":"EUV technology with its state-of-the-art tool generation equipped with a Numerical Aperture (NA) of 0.33 and providing 13 nm resolution is on the brink of entering high volume manufacturing. Extending the roadmap down to a resolution of 8 nm requires a high-NA successor tool. ASML and ZEISS are jointly developing an EUV scanner system with an NA of 0.55 to enable the continuation of Moore’s law throughout the next decade. In this paper we motivate the top-level requirements of this high-NA tool, deduce implications on system design and present how they are solved in the tool. In particular, we address implications of the high-NA leading to large mirror sizes, introduction of a central obscuration and an anamorphic lens design resulting in the transition from full to half field. A consequence of the high-NA is a reduced depth of focus which is dealt with by an improved focus control of the system. The aberration level of the high-NA tool will be significantly reduced w.r.t. the NA 0.33 tool generation. This is achieved by extreme aspheres accompanied by an advanced mirror manufacturing process with corrections down to atomic scale. To enable mirror manufacturing to this precision the limits of mirror metrology are pushed out by transferring the whole measurement process into vacuum. Finally, we will give an update on the current status of the high-NA tool development and the build-up of the necessary infrastructure.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"55 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131578959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Bilski, J. Zimmermann, Matthias Roesch, J. Liddle, E. van Setten, G. Bottiglieri, J. van Schoot
The continuation of Moore’s law demands the continuous development of EUV lithography. After the NXE:3400B scanner, currently being inserted in high-volume manufacturing (HVM), the next logical step is to increase the numerical aperture (NA) of the EUV projection optics, from 0.33 to 0.55, resulting in a high-NA EUV scanner. Looking back at the history of lithography tools developed in the last decades, we can see that such an increase of NA is, in relative terms, unprecedented (0.55 = 0.33 + 67%). This significant step forward in the NA is a challenge on many fronts and requires many adaptations. In this paper you will find an overview of the key concepts that make high-NA lithography different on imaging end, how the imaging assures the continued life of Moore’s law for the years to come and what are potential mask-related developments that would contribute to high-NA’s success.
{"title":"High-NA EUV imaging: challenges and outlook","authors":"B. Bilski, J. Zimmermann, Matthias Roesch, J. Liddle, E. van Setten, G. Bottiglieri, J. van Schoot","doi":"10.1117/12.2536329","DOIUrl":"https://doi.org/10.1117/12.2536329","url":null,"abstract":"The continuation of Moore’s law demands the continuous development of EUV lithography. After the NXE:3400B scanner, currently being inserted in high-volume manufacturing (HVM), the next logical step is to increase the numerical aperture (NA) of the EUV projection optics, from 0.33 to 0.55, resulting in a high-NA EUV scanner. Looking back at the history of lithography tools developed in the last decades, we can see that such an increase of NA is, in relative terms, unprecedented (0.55 = 0.33 + 67%). This significant step forward in the NA is a challenge on many fronts and requires many adaptations. In this paper you will find an overview of the key concepts that make high-NA lithography different on imaging end, how the imaging assures the continued life of Moore’s law for the years to come and what are potential mask-related developments that would contribute to high-NA’s success.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133549106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wafer Intra-Field Process (Printing) Defects created due to various process segments. Narrow Lithography process window (Litho PW), effected by Dose & Focus (calibrated by FEM – Focus Exposure Matrix), is one of the major contributors for the wafer intra-filed process defects caused by hot spots. The Litho PW can be expanded by controlling the Dose parameters over the wafer intra-field. Dose parameters effect the Critical Dimension Uniformity (CDU). Controlling the wafer intra-field CDU will expand the Litho PW and will reduce the process (printing) defects. The extension of 193nm based lithography usage combined with design shrinkage rules for process control (in particular the wafer level CDU control), are extremely important and challenging task in IC manufacturing. This work will show the ZEISS CDC application (CD Control) and its significant positive effect on the intra-field CDU, Litho PW, and process defects probability, as well as introduction for wafer FAB integration flow. It will also challenge some existing process parameters specifications and will explain why IC manufacturing failures come real although all individual process parameters in spec. Specification limits for each individual parameter do not necessarily guarantee a successful process, as it’s almost impossible to anticipate and verify all possible interdependencies among different parameters. The goal is therefore, to show how to improve IC process by shrinking its individual parameters distributions, even if the variability of those parameters is in specification. This work will offer solution named as “Excursion Prevention” - Improve wafer intra-field CDU by using the ZEISS CDC tool, to reduce the wafer intra-field printing defects caused by narrow Litho PW.
{"title":"Reduce probability of wafer intra-field process (printing) defects for logic and DRAM applications","authors":"Yael Sufrin, Avi Cohen, Ofir Sharoni, R. Seltmann","doi":"10.1117/12.2535686","DOIUrl":"https://doi.org/10.1117/12.2535686","url":null,"abstract":"Wafer Intra-Field Process (Printing) Defects created due to various process segments. Narrow Lithography process window (Litho PW), effected by Dose & Focus (calibrated by FEM – Focus Exposure Matrix), is one of the major contributors for the wafer intra-filed process defects caused by hot spots. The Litho PW can be expanded by controlling the Dose parameters over the wafer intra-field. Dose parameters effect the Critical Dimension Uniformity (CDU). Controlling the wafer intra-field CDU will expand the Litho PW and will reduce the process (printing) defects. The extension of 193nm based lithography usage combined with design shrinkage rules for process control (in particular the wafer level CDU control), are extremely important and challenging task in IC manufacturing. This work will show the ZEISS CDC application (CD Control) and its significant positive effect on the intra-field CDU, Litho PW, and process defects probability, as well as introduction for wafer FAB integration flow. It will also challenge some existing process parameters specifications and will explain why IC manufacturing failures come real although all individual process parameters in spec. Specification limits for each individual parameter do not necessarily guarantee a successful process, as it’s almost impossible to anticipate and verify all possible interdependencies among different parameters. The goal is therefore, to show how to improve IC process by shrinking its individual parameters distributions, even if the variability of those parameters is in specification. This work will offer solution named as “Excursion Prevention” - Improve wafer intra-field CDU by using the ZEISS CDC tool, to reduce the wafer intra-field printing defects caused by narrow Litho PW.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131567364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lithographers are currently unable to generate quality patterning at tight pitches with values of k1 that are as low as have been achieved routinely using ArF immersion patterning, a situation that is largely due to the continuing pursuit of resists with low exposure doses. As a consequence, multiple patterning may be required to scale to a second node with EUV lithography, which reduces its cost-effectiveness, even if each individual exposure is done with a low exposure dose. Because of process control limitations, such multiple patterning may necessarily be triple or quadruple patterning, rather than double patterning. Processes with reduced line-edge roughness (LER) could be applied to front-end layers, increasing the value of EUV lithography. High-NA EUV lithography is in development, with a number of technical issues requiring solution, but with no apparent show-stoppers.
{"title":"The potential of EUV lithography","authors":"H. Levinson","doi":"10.1117/12.2528446","DOIUrl":"https://doi.org/10.1117/12.2528446","url":null,"abstract":"Lithographers are currently unable to generate quality patterning at tight pitches with values of k1 that are as low as have been achieved routinely using ArF immersion patterning, a situation that is largely due to the continuing pursuit of resists with low exposure doses. As a consequence, multiple patterning may be required to scale to a second node with EUV lithography, which reduces its cost-effectiveness, even if each individual exposure is done with a low exposure dose. Because of process control limitations, such multiple patterning may necessarily be triple or quadruple patterning, rather than double patterning. Processes with reduced line-edge roughness (LER) could be applied to front-end layers, increasing the value of EUV lithography. High-NA EUV lithography is in development, with a number of technical issues requiring solution, but with no apparent show-stoppers.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123360789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
EUV lithography is being used at relatively high-k1 Rayleigh factors. Advancing EUV to smaller resolution requires several technological advancements. The EUV reticle is a strong contributor that limits current EUV imaging performance. Improvements with advanced mask types are required to reduce mask 3D effects and to improve image contrast. This will enable low-k1 resolution with reduced stochastic defect rates. In this paper we discuss what the requirements of high-k absorber masks and attenuated phase shift masks are to achieve optimal imaging performance. Recommendations on the mask stack composition and the application of mask types to different use cases are based on the physical understanding of the mask diffraction spectrum.
{"title":"Alternative mask materials for low-k1 EUV imaging","authors":"F. Timmermans, C. van Lare, J. Finders","doi":"10.1117/12.2535682","DOIUrl":"https://doi.org/10.1117/12.2535682","url":null,"abstract":"EUV lithography is being used at relatively high-k1 Rayleigh factors. Advancing EUV to smaller resolution requires several technological advancements. The EUV reticle is a strong contributor that limits current EUV imaging performance. Improvements with advanced mask types are required to reduce mask 3D effects and to improve image contrast. This will enable low-k1 resolution with reduced stochastic defect rates. In this paper we discuss what the requirements of high-k absorber masks and attenuated phase shift masks are to achieve optimal imaging performance. Recommendations on the mask stack composition and the application of mask types to different use cases are based on the physical understanding of the mask diffraction spectrum.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115781690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leon van Dijk, A. Charley, M. Stokhof, Ronald Otten, S. Van Elshocht, Bert Jongbloed, P. Leray, Richard J. F. van Haren
Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.
{"title":"Detection and mitigation of furnace anneal induced distortions at the wafer edge","authors":"Leon van Dijk, A. Charley, M. Stokhof, Ronald Otten, S. Van Elshocht, Bert Jongbloed, P. Leray, Richard J. F. van Haren","doi":"10.1117/12.2535636","DOIUrl":"https://doi.org/10.1117/12.2535636","url":null,"abstract":"Every advance in technology node challenges the semiconductor industry to achieve even tighter on-product overlay (OPO) requirements. With the latest immersion scanners performing well below the sub-2-nm overlay level, the OPO budget is more and more determined by non-lithography contributors. Achieving the tight overlay specifications in a high-volume manufacturing environment is therefore far from trivial, especially in the wafer edge region where processing is even less well controlled. For example, Reactive Ion Etch (RIE), the deposition of stressed thin films and the presence of significant intra-field (or intra-die) stress distributions are all known to cause localized distortions in the wafer edge region. Annealing steps during integrated circuit manufacturing are another source of wafer deformation. Furnace anneal is one particular type of annealing step. During furnace anneal processing, many wafers are heated-up simultaneously and wafers stay at elevated temperatures for a fixed time on the order of minutes to hours. Although in general, furnace anneal does not cause significant wafer deformations, local distortions are sometimes observed in the wafer edge region by using standard boats at higher anneal temperatures. In this work, we have setup a controlled experiment to characterize the local distortions that can be induced by furnace anneal processes. To this end, wafers are processed with various furnace anneal settings, i.e. temperature and ramp rate, and two different boat types are used. The induced distortions are accurately and densely measured on an NXT:1970Ci scanner using its SMASH alignment system. We will see that, depending on the process conditions and boat type, local distortions occur at the wafer edge. The locations of these distortions coincide with the wafer support positions of the boat and therefore they are also referred to as boat marks. Several solution directions for mitigating furnace anneal induced distortions will be discussed. A very effective solution is the employment of an optimized boat design that, depending on the process conditions, can prevent the localized distortions at elevated temperatures. It would therefore be beneficial to have a detection system in place that can detect and consequently trigger actions to mitigate furnace anneal induced distortions during the development phase of anneal processing steps. We will demonstrate that the scanner can be used as such a detection system as its inline metrology is able to detect signatures related to the boat marks.","PeriodicalId":287066,"journal":{"name":"European Mask and Lithography Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132785356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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