Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690993
Laura Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto
A 346μm2 reference-free, asynchronous VCO-based sensor interface circuit is demonstrated in 28nm LP CMOS. This design does not require high accuracy current sources, voltage sources, or low jitter timing references. It achieves wide resolution and voltage scalability, and consumes only ~1/100th the area of prior approaches. Resolution can be scaled from 2.8 to 11.7 bits and VDD from 500mV to 1.0V.
{"title":"A 346μm2 reference-free sensor interface for highly constrained microsystems in 28nm CMOS","authors":"Laura Freyman, D. Fick, D. Blaauw, D. Sylvester, M. Alioto","doi":"10.1109/ASSCC.2013.6690993","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690993","url":null,"abstract":"A 346μm2 reference-free, asynchronous VCO-based sensor interface circuit is demonstrated in 28nm LP CMOS. This design does not require high accuracy current sources, voltage sources, or low jitter timing references. It achieves wide resolution and voltage scalability, and consumes only ~1/100th the area of prior approaches. Resolution can be scaled from 2.8 to 11.7 bits and VDD from 500mV to 1.0V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122727851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691016
Ying-Yao Lin, Wen-Kai Li, Pi-An Wu, Chih-Lung Chen, Yibin Hsieh, Eric Lu, Edris Rostami, Bryan Huang, Bart Wu, J. Ko, K. Fong, Y. Huang, Chun-Yi Wu, Chia-Hsin Wu, A. Jerng
A single-chip 2×2 MIMO 802.11 b/g/n compliant WLAN AP/Router system-on-a chip(AP/Router SOC) that integrates all RF, analog, digital PHY, MAC, CPU and 5-port Ethernet functions as well as all necessary peripheral blocks has been integrated in 55nm CMOS. To reduce rBOM and PCB design complexity, two high power CMOS PAs, LNAs, and T/R switches are integrated for the MIMO transceiver. The radio transmits 22.4 dBm CCK mask compliant power and delivers 19dBm with EVM= -30dB at HT20 and 18dBm with EVM= -30dB at HT40. CCK RX sensitivity at the shared antenna port is -99dBm at 1Mbps rate, while CCK RX sensitivity is -100dBm at the auxiliary LNA path.
{"title":"A 2×2 MIMO 802.11 b/g/n WLAN SOC in 55nm CMOS for AP/Router application","authors":"Ying-Yao Lin, Wen-Kai Li, Pi-An Wu, Chih-Lung Chen, Yibin Hsieh, Eric Lu, Edris Rostami, Bryan Huang, Bart Wu, J. Ko, K. Fong, Y. Huang, Chun-Yi Wu, Chia-Hsin Wu, A. Jerng","doi":"10.1109/ASSCC.2013.6691016","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691016","url":null,"abstract":"A single-chip 2×2 MIMO 802.11 b/g/n compliant WLAN AP/Router system-on-a chip(AP/Router SOC) that integrates all RF, analog, digital PHY, MAC, CPU and 5-port Ethernet functions as well as all necessary peripheral blocks has been integrated in 55nm CMOS. To reduce rBOM and PCB design complexity, two high power CMOS PAs, LNAs, and T/R switches are integrated for the MIMO transceiver. The radio transmits 22.4 dBm CCK mask compliant power and delivers 19dBm with EVM= -30dB at HT20 and 18dBm with EVM= -30dB at HT40. CCK RX sensitivity at the shared antenna port is -99dBm at 1Mbps rate, while CCK RX sensitivity is -100dBm at the auxiliary LNA path.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122954939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690990
M. Ghanad, Michael M. Green, C. Dehollain
Multiple techniques are presented to implement an ultra-low-power remotely powered implantable system. The temperature is monitored locally by a thermistor-type sensor. The resistive response of the sensor is amplified and resolved in the time-domain. The data is transmitted using a duty cycled free running oscillator operating at 868 MHz. In addition, the sensor interface and data transmitter are time interleaved to improve power link sensitivity. A prototype chip is fabricated in 0.18 μm CMOS. The implant is powered with a 13.56 MHz inductive link and operates with a minimum power of 53 μW. The system is capable of recording temperature with accuracy of ±0.09 °C when 8 times oversampling is done at the base station.
{"title":"A remotely powered implantable IC for recording mouse local temperature with ±0.09 °C accuracy","authors":"M. Ghanad, Michael M. Green, C. Dehollain","doi":"10.1109/ASSCC.2013.6690990","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690990","url":null,"abstract":"Multiple techniques are presented to implement an ultra-low-power remotely powered implantable system. The temperature is monitored locally by a thermistor-type sensor. The resistive response of the sensor is amplified and resolved in the time-domain. The data is transmitted using a duty cycled free running oscillator operating at 868 MHz. In addition, the sensor interface and data transmitter are time interleaved to improve power link sensitivity. A prototype chip is fabricated in 0.18 μm CMOS. The implant is powered with a 13.56 MHz inductive link and operates with a minimum power of 53 μW. The system is capable of recording temperature with accuracy of ±0.09 °C when 8 times oversampling is done at the base station.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122167546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691074
S. Kawai, Tong Wang, T. Mitomo, S. Saigusa
This paper presents a temperature variation tolerant 60 GHz Low Noise Amplifier (LNA) for mm-wave communication systems. The proposed temperature compensated bias circuit is utilized for the common source LNA. The temperature variation of S21 is 1.71dB in the temperature range from -20°C to 100°C, which is 47% lower than the value reported in previous work. The Figure of Merit (FoM) of the proposed LNA at 25°C is comparable to the top value of state-of-the-art work and FoM at 100°C is also comparable to those reported in the literature operated at room temperature.
{"title":"A temperature variation tolerant 60 GHz Low Noise Amplifier with current compensated bias circuit","authors":"S. Kawai, Tong Wang, T. Mitomo, S. Saigusa","doi":"10.1109/ASSCC.2013.6691074","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691074","url":null,"abstract":"This paper presents a temperature variation tolerant 60 GHz Low Noise Amplifier (LNA) for mm-wave communication systems. The proposed temperature compensated bias circuit is utilized for the common source LNA. The temperature variation of S21 is 1.71dB in the temperature range from -20°C to 100°C, which is 47% lower than the value reported in previous work. The Figure of Merit (FoM) of the proposed LNA at 25°C is comparable to the top value of state-of-the-art work and FoM at 100°C is also comparable to those reported in the literature operated at room temperature.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123616434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690975
P. Francese, T. Toifl, P. Buchmann, M. Brandli, M. Kossel, C. Menolfi, T. Morf, L. Kull, T. Andersen, A. Cevrero
The circuit presented is a power-efficient implementation of a 16 Gb/s I/O link NRZ receiver in 22 nm CMOS SOI. A CTLE feeds an 8-tap DFE for ISI equalization. The first tap uses digital speculation and the following seven taps are realized with switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud rate CDR. The receiver architecture is half rate and requires only a single phase rotator. In total, six comparators in each even/odd signal path slice recover both data and timing information. The timing information extraction requires four additional comparators per slice in parallel to the two required by the first-tap DFE speculation. The CDR digital section operates at quarter rate and features a low-latency implementation for the timing control loop. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization are recovered error-free (BER <; 10-12) across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 30 kppm (16 GHz ±480 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered error-free (BER<; 10-12) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.
{"title":"A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth","authors":"P. Francese, T. Toifl, P. Buchmann, M. Brandli, M. Kossel, C. Menolfi, T. Morf, L. Kull, T. Andersen, A. Cevrero","doi":"10.1109/ASSCC.2013.6690975","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690975","url":null,"abstract":"The circuit presented is a power-efficient implementation of a 16 Gb/s I/O link NRZ receiver in 22 nm CMOS SOI. A CTLE feeds an 8-tap DFE for ISI equalization. The first tap uses digital speculation and the following seven taps are realized with switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud rate CDR. The receiver architecture is half rate and requires only a single phase rotator. In total, six comparators in each even/odd signal path slice recover both data and timing information. The timing information extraction requires four additional comparators per slice in parallel to the two required by the first-tap DFE speculation. The CDR digital section operates at quarter rate and features a low-latency implementation for the timing control loop. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization are recovered error-free (BER <; 10-12) across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 30 kppm (16 GHz ±480 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered error-free (BER<; 10-12) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125767866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691005
Chih-Lung Chen, Yu-Cheng Lan, Hsie-Chia Chang, Chen-Yi Lee
In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.
{"title":"A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications","authors":"Chih-Lung Chen, Yu-Cheng Lan, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ASSCC.2013.6691005","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691005","url":null,"abstract":"In this work, a decoder chip for time-invariant tail-biting LDPC convolutional code (TB-LDPC-CC) is proposed. By modifying the layered decoding scheduling, the proposed decoding algorithm can achieve twice faster decoding convergence than the conventional flooding scheduling. Furthermore, 30.77% storage requirement is also reduced due to adaptive channel value addressing employed in memory-based decoder design. The multiple frame sizes handling ability can lower the power and adapt to multiple applications. By integrating these techniques, a TB-LDPC-CC decoder chip supporting three frame sizes is implemented in UMC 90nm CMOS technology. The decoder containing 4 processors occupies 2.18mm2 area and provides maximum throughput 3.66Gb/s under 0.8V supply and 305MHz with a 18.8pJ/bit/proc energy efficiency.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129611975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1109/ASSCC.2013.6691061
Taewook Kang, Yoontaek Lee, Myeong-Jae Park, Jaeha Kim
This paper presents a new type of gate driver IC that can significantly reduce the gate switching loss by leveraging high-speed and low-power operation of custom integrated circuits. The gate driver itself works as a mini bidirectional buck converter, which charges and discharges the gate terminal of a power device (e.g. IGBT) by feeding a chain of short pulses whose widths gradually increase or decrease into an LC filter. A set of circuit techniques to minimize the energy consumption in generating these pulses at the required frequency of up to 50-MHz and duty-cycle resolution of 5% is presented. A prototype IC fabricated in a 0.25-μm HV CMOS demonstrates 27.8-mW power consumption or equivalently 62% energy recycling while switching a 120-nC IGBT at 40-kHz and 15-V.
{"title":"A 15-V, 40-kHz class-D gate driver IC with 62% energy recycling rate","authors":"Taewook Kang, Yoontaek Lee, Myeong-Jae Park, Jaeha Kim","doi":"10.1109/ASSCC.2013.6691061","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691061","url":null,"abstract":"This paper presents a new type of gate driver IC that can significantly reduce the gate switching loss by leveraging high-speed and low-power operation of custom integrated circuits. The gate driver itself works as a mini bidirectional buck converter, which charges and discharges the gate terminal of a power device (e.g. IGBT) by feeding a chain of short pulses whose widths gradually increase or decrease into an LC filter. A set of circuit techniques to minimize the energy consumption in generating these pulses at the required frequency of up to 50-MHz and duty-cycle resolution of 5% is presented. A prototype IC fabricated in a 0.25-μm HV CMOS demonstrates 27.8-mW power consumption or equivalently 62% energy recycling while switching a 120-nC IGBT at 40-kHz and 15-V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123824125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1109/ASSCC.2013.6690998
A. Islam, T. Ishihara, H. Onodera
To measure target MOSFET variation, specific monitor schemes are required. With device scaling, developing each monitor scheme is costly. This paper proposes a universal delay monitor cell which enables measurements of various types of variations with single monitor scheme. The monitor cell is reconfigurable and standard cell compatible; thus it can be used in the conventional place and route flow. An area-efficient monitor scheme to monitor global, local, and dynamic variations is developed. Measurement results from a 65-nm test chip shows the validity of the proposed monitor cell. The proposed cell enables area-efficient and low cost implementation of monitor schemes which can be integrated with application such as testing and adaptive voltage scaling.
{"title":"Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes","authors":"A. Islam, T. Ishihara, H. Onodera","doi":"10.1109/ASSCC.2013.6690998","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690998","url":null,"abstract":"To measure target MOSFET variation, specific monitor schemes are required. With device scaling, developing each monitor scheme is costly. This paper proposes a universal delay monitor cell which enables measurements of various types of variations with single monitor scheme. The monitor cell is reconfigurable and standard cell compatible; thus it can be used in the conventional place and route flow. An area-efficient monitor scheme to monitor global, local, and dynamic variations is developed. Measurement results from a 65-nm test chip shows the validity of the proposed monitor cell. The proposed cell enables area-efficient and low cost implementation of monitor schemes which can be integrated with application such as testing and adaptive voltage scaling.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130990266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1109/ASSCC.2013.6691051
B. Ong, E. Khoo, Wei Yang, MinJie Wu, Jiqing Cui, S. R. Karri, Junmin Cao, Ming Kong, C. Leow, C. Heng, O. Shana'a
A 45MHz to 1002MHz direct conversion Universal TV Tuner (UTV) supports world-wide TV broadcast standards, such as ATV (NTSC, PAL, SECAM), DTV (ISDB-T, DVB-T, DVB-T2, ATSC, DTMB, DVB-C/C2), EN55020 etc. The tuner exhibits less than 5.5dB noise figure (NF), >70dB image rejection, +30dBm IIP3, +67dBm IIP2 and harmonic rejection of more than 70dB over the operating frequency range. An integrated ΣΔ PLL with a novel compact integrated loop filter locks a broadband dual-tank VCO to a 29MHz reference. The tuner occupies less than 10mm2 of silicon area in 0.18μm CMOS and consumes around 659mW from 3.3V/2.2V dual supply.
{"title":"A Universal silicon TV Tuner with a compact synthesizer in 0.18μm CMOS","authors":"B. Ong, E. Khoo, Wei Yang, MinJie Wu, Jiqing Cui, S. R. Karri, Junmin Cao, Ming Kong, C. Leow, C. Heng, O. Shana'a","doi":"10.1109/ASSCC.2013.6691051","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691051","url":null,"abstract":"A 45MHz to 1002MHz direct conversion Universal TV Tuner (UTV) supports world-wide TV broadcast standards, such as ATV (NTSC, PAL, SECAM), DTV (ISDB-T, DVB-T, DVB-T2, ATSC, DTMB, DVB-C/C2), EN55020 etc. The tuner exhibits less than 5.5dB noise figure (NF), >70dB image rejection, +30dBm IIP3, +67dBm IIP2 and harmonic rejection of more than 70dB over the operating frequency range. An integrated ΣΔ PLL with a novel compact integrated loop filter locks a broadband dual-tank VCO to a 29MHz reference. The tuner occupies less than 10mm2 of silicon area in 0.18μm CMOS and consumes around 659mW from 3.3V/2.2V dual supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122825725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-01DOI: 10.1109/ASSCC.2013.6691023
Shih-Hao Huang, Wei-Zen Chen
This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm. This receiver core drains 30 mW from 1-V supply.
{"title":"A 20-Gb/s optical receiver with integrated photo detector in 40-nm CMOS","authors":"Shih-Hao Huang, Wei-Zen Chen","doi":"10.1109/ASSCC.2013.6691023","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691023","url":null,"abstract":"This paper presents a 20-Gb/s monolithically integrated CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. Incorporating a 2-D meshed spatially-modulated light detector, the optical receiver achieves a record-high speed and is capable of delivering 80-dBΩ conversion gain when driving 50-Ω output loads. Nested-feedback topologies are adopted for transimpedance and post limiting amplifier design to achieve broad-band and high-gain operations without shunt-peaking inductors. Implemented in a generic 40-nm CMOS technology, the chip size is 0.6 × 0.54 mm. This receiver core drains 30 mW from 1-V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132319626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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