Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691050
Nan Qi, Zheng Song, Zehong Zhang, Yang Xu, B. Chi, Zhihua Wang
A fully-integrated multi-mode SAW-less GNSS receiver in 65nm CMOS is presented, which supports both ordinary and high precision GNSS signals with their bandwidth covering from 4MHz to 20MHz. The receiver employs a voltage sampling RF front-end and a 2nd-order continuous-time (CT) sigma-delta ADC to provide large dynamic range, as well as simplifying the analog baseband circuits. Besides, an on-chip I/Q calibration is integrated to improve the image rejection ratio (IRR), which can be realized manually or automatically with a FPGA. Op-amp arrays are used in the analog baseband, whose power consumption is scalable for different operation modes. The receiver achieves 3dB noise figure, -31dBm in-band 1dB compression point, -15dBm out-of-band (OOB) 1dB desensitization point, 43dB IRR and a maxim 62dB SNDR ADC outputs, while consuming 40mW DC power in the narrow-band and 52.5mW in the wide-band mode respectively.
{"title":"A multi-mode blocker-tolerant GNSS receiver with CT sigma-delta ADC in 65nm CMOS","authors":"Nan Qi, Zheng Song, Zehong Zhang, Yang Xu, B. Chi, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691050","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691050","url":null,"abstract":"A fully-integrated multi-mode SAW-less GNSS receiver in 65nm CMOS is presented, which supports both ordinary and high precision GNSS signals with their bandwidth covering from 4MHz to 20MHz. The receiver employs a voltage sampling RF front-end and a 2nd-order continuous-time (CT) sigma-delta ADC to provide large dynamic range, as well as simplifying the analog baseband circuits. Besides, an on-chip I/Q calibration is integrated to improve the image rejection ratio (IRR), which can be realized manually or automatically with a FPGA. Op-amp arrays are used in the analog baseband, whose power consumption is scalable for different operation modes. The receiver achieves 3dB noise figure, -31dBm in-band 1dB compression point, -15dBm out-of-band (OOB) 1dB desensitization point, 43dB IRR and a maxim 62dB SNDR ADC outputs, while consuming 40mW DC power in the narrow-band and 52.5mW in the wide-band mode respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691046
H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.
{"title":"A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop","authors":"H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi","doi":"10.1109/ASSCC.2013.6691046","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691046","url":null,"abstract":"We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-microsecond entry/exit delay penalty in power-on/power-off, which is one order of magnitude faster than a conventional MPU's deep power down mode. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems because of its easy controllability for the power gating mode.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128726643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.
{"title":"A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS","authors":"Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu, Chun-Po Huang","doi":"10.1109/ASSCC.2013.6691039","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691039","url":null,"abstract":"This paper reports a successive-approximation analog-to-digital converter (ADC) which combines the bypass window and direct switching technique to tolerate the incomplete settling error and reduce the control logic delay. A small unit capacitor cell reduces the power consumption and settling time. The 10-bit prototype is fabricated in a 40nm CMOS process. At 200 MS/s and 0.9-V supply, this ADC consumes 0.82 mW and achieves an SNDR of 57.16 dB, resulting in an FOM of 13.9 fJ/Conversion-step.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128739714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690971
V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang
The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.
{"title":"A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications","authors":"V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang","doi":"10.1109/ASSCC.2013.6690971","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690971","url":null,"abstract":"The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116914789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691032
Yuya Hasegawa, K. Tomita, Subaru Ishihara, Ryutaro Honma, H. Ishikuro
A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option.
{"title":"Single-inductor-dual-output wireless power receiver with synchronous pseudo-random-sequence PWM switched rectifiers","authors":"Yuya Hasegawa, K. Tomita, Subaru Ishihara, Ryutaro Honma, H. Ishikuro","doi":"10.1109/ASSCC.2013.6691032","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691032","url":null,"abstract":"A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132726427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691054
M. S. Jalali, Clifford Ting, Behrooz Abiri, A. Sheikholeslami, M. Kibune, H. Tamura
This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16" FR4 channel.
{"title":"A 3x blind ADC-based CDR","authors":"M. S. Jalali, Clifford Ting, Behrooz Abiri, A. Sheikholeslami, M. Kibune, H. Tamura","doi":"10.1109/ASSCC.2013.6691054","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691054","url":null,"abstract":"This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16\" FR4 channel.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134297635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690972
Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams
Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.
{"title":"Zero leakage microcontroller with 384ns wakeup time using FRAM mini-array architecture","authors":"Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams","doi":"10.1109/ASSCC.2013.6690972","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690972","url":null,"abstract":"Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691022
Jong-Hoon Kim, Soo-Min Lee, J. Sim, Byungsub Kim, Hong-June Park
By increasing the termination resistance to 4ZO at both TX and RX of a differential serial link with a CML driver, the transceiver power is reduced by 37%. The TX power is reduced by 54%. The TX includes a CML driver, a pre-driver and a serializer. While the reflection and the ISI are increased due to the increase of the termination resistance, they are compensated for by a 2-tap DFE circuit at RX. The DFE tap position for reflection and the DFE coefficients for ISI and reflection are found automatically during the initial training mode. The transceiver chip fabricated in a 0.13μm process shows a BER<;1E-12 with 25, 30 and 35cm FR4 channels at 5Gbps.
{"title":"A power reduction of 37% in a differential serial link transceiver by increasing the termination resistance","authors":"Jong-Hoon Kim, Soo-Min Lee, J. Sim, Byungsub Kim, Hong-June Park","doi":"10.1109/ASSCC.2013.6691022","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691022","url":null,"abstract":"By increasing the termination resistance to 4ZO at both TX and RX of a differential serial link with a CML driver, the transceiver power is reduced by 37%. The TX power is reduced by 54%. The TX includes a CML driver, a pre-driver and a serializer. While the reflection and the ISI are increased due to the increase of the termination resistance, they are compensated for by a 2-tap DFE circuit at RX. The DFE tap position for reflection and the DFE coefficients for ISI and reflection are found automatically during the initial training mode. The transceiver chip fabricated in a 0.13μm process shows a BER<;1E-12 with 25, 30 and 35cm FR4 channels at 5Gbps.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 μW with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.
{"title":"Batteryless 275mV startup single-cell photovoltaic energy harvesting system for alleviating shading effect","authors":"Chao-Jen Huang, Yi-Ping Su, Ke-Horng Chen, Li-Ren Huang, Fang-Chih Chu, Yuan-Hua Chu, Chinder Wey","doi":"10.1109/ASSCC.2013.6691033","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691033","url":null,"abstract":"Without any batteries, a low input voltage converter is presented for a single-cell (SC) photovoltaic (PV) energy harvesting to alleviate the energy degradation due to shading effect. The proposed low voltage startup (LVS) circuit with low input voltage of 275 mV and less than 840 ms startup time achieves high voltage conversion ratio to supply a high accuracy bandgap reference. Experimental results show the maximum power throughput is up to 6 mW and the quiescent power is less than 650 μW with integrated two buck-boost converters and two boost converters. The peak efficiency of the boost converter can be up to 75.8% for ultra-low voltage hearing aid systems.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"49 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128627599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691028
S. Sheu, Chia-Chen Kuo, Meng-Fan Chang, P. Tseng, L. Chih-Sheng, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, K. Su, T. Ku, M. Tsai, M. Kao
This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.
{"title":"A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application","authors":"S. Sheu, Chia-Chen Kuo, Meng-Fan Chang, P. Tseng, L. Chih-Sheng, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, K. Su, T. Ku, M. Tsai, M. Kao","doi":"10.1109/ASSCC.2013.6691028","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691028","url":null,"abstract":"This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128847812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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