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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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Dynamic bootstrap voltage technique for high efficiency buck converter in universal serial bus power device supplying system 通用串行总线供电系统中高效降压变换器的动态自举电压技术
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691008
Wei-Chung Chen, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee
For high power universal serial bus (USB) devices, the dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over a wide load range, including light and heavy loads. Besides, the silicon area of power management of the system-on-a-chip (Soc) can be effectively reduced to 50% of conventional design with P-type high-side power MOSFET. The test chip fabricated in 0.25μm CMOS process shows 92% peak efficiency from 1mA to 1A. The maximum driving current is higher than 3A with 88 % efficiency. Compared to that without the DBV technique, the efficiency is improved about 28%.
针对大功率通用串行总线(USB)器件,提出了动态自举电压(DBV)技术,以在包括轻负载和重负载在内的宽负载范围内保持高效率。此外,采用p型高侧功率MOSFET,可以有效地将系统级单片(Soc)电源管理的硅面积减少到传统设计的50%。采用0.25μm CMOS工艺制作的测试芯片在1mA到1A范围内的峰值效率为92%。最大驱动电流大于3A,效率88%。与没有DBV技术相比,效率提高了约28%。
{"title":"Dynamic bootstrap voltage technique for high efficiency buck converter in universal serial bus power device supplying system","authors":"Wei-Chung Chen, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee","doi":"10.1109/ASSCC.2013.6691008","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691008","url":null,"abstract":"For high power universal serial bus (USB) devices, the dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over a wide load range, including light and heavy loads. Besides, the silicon area of power management of the system-on-a-chip (Soc) can be effectively reduced to 50% of conventional design with P-type high-side power MOSFET. The test chip fabricated in 0.25μm CMOS process shows 92% peak efficiency from 1mA to 1A. The maximum driving current is higher than 3A with 88 % efficiency. Compared to that without the DBV technique, the efficiency is improved about 28%.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129466980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs HEPP:一种用于容差超低电压设计的实时误差预测与预防新技术
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690999
Jun Zhou, Xin Liu, Yat-Hei Lam, Chao Wang, Kah-Hyong Chang, Jingjing Lan, M. Je
A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.
为了减轻PVT变化对超低电压数字设计的影响,提出了一种新的实时误差预测和预防技术——HEPP。与先前的Razor和Canary触发器技术相比,该技术消除了保持时间限制,能够处理由不频繁激活的关键路径和快速动态变化引起的错误。它开销低,适用于一般的数字设计。将HEPP技术应用于FFT处理器的实验结果表明,与传统的最坏情况设计相比,该技术的性能提高了122%,能耗降低了88%。
{"title":"HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs","authors":"Jun Zhou, Xin Liu, Yat-Hei Lam, Chao Wang, Kah-Hyong Chang, Jingjing Lan, M. Je","doi":"10.1109/ASSCC.2013.6690999","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690999","url":null,"abstract":"A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the proposed technique eliminates the hold-time constraint and is able to deal with errors caused by infrequently activated critical paths and fast dynamic variations. It has low overhead and is applicable to general digital designs. The experimental results of applying the proposed HEPP technique to a FFT processor show 122% performance improvement or 88% energy reduction compared to the conventional worst-case design.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117224211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A 5V, 33-kHz, OJ-μW pulse generation circuit for ultra-low-power boost charging energy harvesters 用于超低功耗升压充电能量收集器的 5V、33 kHz、OJ-μW 脉冲发生电路
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691079
Wootaek Lim, Joonseok Yang, Myeong-Jae Park, Min-Woo Won, Jaeha Kim
This paper presents a ultra-low-power oscillator and pulse-width modulator circuits for a boost-converter-based energy harvester that is capable of collecting net energy even when the input power is less than 2μW. While the previously published leakage-based relaxation oscillators demonstrated 0.42μW at 3.2-MHz, their voltage swings were limited to 0.45V to prevent crowbar currents in the crossing detector stages. New crossing detector circuits that limit the crowbar current to a sub-threshold leakage level enables both the ultra-low-power oscillator and pulse-width modulator even when they are operating at a 5V supply. Fabricated in a 0.25μm CMOS, the prototype oscillator dissipates only 10nW~50μW while generating a 10-Hz to 20-MHz clock at 5V swing. The energy harvester switching at 33-kHz keeps the efficiency above 59% even when the input power level from photovoltaic cells drops to 2μW.
本文介绍了一种超低功耗振荡器和脉宽调制器电路,用于基于升压转换器的能量收集器,即使输入功率小于 2μW 也能收集净能量。虽然之前发布的基于漏电的弛豫振荡器在 3.2-MHz 时的功率为 0.42μW,但其电压摆幅被限制在 0.45V,以防止交叉检测器级中出现撬棍电流。新的交叉检测器电路将撬棍电流限制在阈值以下漏电水平,使超低功率振荡器和脉宽调制器即使在 5V 电源下工作也能正常工作。原型振荡器采用 0.25μm CMOS 制作,在 5V 摆幅下产生 10-Hz 至 20-MHz 时钟时,耗散功率仅为 10nW 至 50μW。即使光伏电池的输入功率降至 2μW,33-kHz 的能量收集器开关也能保持 59% 以上的效率。
{"title":"A 5V, 33-kHz, OJ-μW pulse generation circuit for ultra-low-power boost charging energy harvesters","authors":"Wootaek Lim, Joonseok Yang, Myeong-Jae Park, Min-Woo Won, Jaeha Kim","doi":"10.1109/ASSCC.2013.6691079","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691079","url":null,"abstract":"This paper presents a ultra-low-power oscillator and pulse-width modulator circuits for a boost-converter-based energy harvester that is capable of collecting net energy even when the input power is less than 2μW. While the previously published leakage-based relaxation oscillators demonstrated 0.42μW at 3.2-MHz, their voltage swings were limited to 0.45V to prevent crowbar currents in the crossing detector stages. New crossing detector circuits that limit the crowbar current to a sub-threshold leakage level enables both the ultra-low-power oscillator and pulse-width modulator even when they are operating at a 5V supply. Fabricated in a 0.25μm CMOS, the prototype oscillator dissipates only 10nW~50μW while generating a 10-Hz to 20-MHz clock at 5V swing. The energy harvester switching at 33-kHz keeps the efficiency above 59% even when the input power level from photovoltaic cells drops to 2μW.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125711569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.1–5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS 基于65nm CMOS的0.1-5GHz SDR发射器,采用双模功率放大器和数字辅助I/Q不平衡校准
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691018
Yun Yin, B. Chi, Qian Yu, Bingqiao Liu, Zhihua Wang
A 0.1-5GHz Software-Defined Radio (SDR) transmitter in 65nm CMOS is presented. The transmitter integrates a dual-mode power amplifier (PA) for 0.1-1.5GHz low-cost narrowband applications (such as Industry Specific Applications, 2G, ZigBee), while a three-sub-band pre-power amplifier (PPA) is used for 0.45-5GHz high performance wideband applications (3G, 4G and etc.). A digital-assisted I/Q imbalance calibration circuit is proposed ahead the TX chain to pre-compensate I/Q mismatch in IF and LO modules. Analog baseband utilizes power scalable technique to optimize power consumption among different modes. The transmitter achieves -63.9dBc image rejection ratio (IRR) and -56.9dBc LO leakage rejection. In narrowband modes, the dual-mode PA provides >19dBm output P1dB with >20% PAE in its linear mode, and 23.2dBm maximum saturation power with 60% peak PAE in the switching mode. In wideband modes, the PPA provides maximum 9dBm output P1dB. F urthermore, system verifications demonstrate 0.5% EVM for 905MHz GSM at 19.5dBm output power. And the transmitter achieves -42.6dBc ACLR and 1.4% EVM for 2.3GHz LTE20 at 6.2dBm output.
提出了一种基于65nm CMOS的0.1-5GHz软件定义无线电(SDR)发射机。发射器集成了双模功率放大器(PA),用于0.1-1.5GHz低成本窄带应用(如Industry Specific applications, 2G, ZigBee),而三子带预功率放大器(PPA)用于0.45-5GHz高性能宽带应用(3G, 4G等)。提出了一种数字辅助I/Q不平衡校正电路,用于在信号传输链前预补偿中频和LO模块中的I/Q不匹配。模拟基带利用功率可扩展技术优化不同模式间的功耗。发射机实现了-63.9dBc的图像抑制比(IRR)和-56.9dBc的LO泄漏抑制。在窄带模式下,双模放大器在线性模式下提供>19dBm输出P1dB, PAE >20%;在开关模式下提供23.2dBm最大饱和功率,峰值PAE为60%。在宽带模式下,PPA提供最大9dBm输出P1dB。此外,系统验证表明,在19.5dBm输出功率下,905MHz GSM的EVM为0.5%。在6.2dBm输出下,2.3GHz LTE20的ACLR为-42.6dBc, EVM为1.4%。
{"title":"A 0.1–5GHz SDR transmitter with dual-mode power amplifier and digital-assisted I/Q imbalance calibration in 65nm CMOS","authors":"Yun Yin, B. Chi, Qian Yu, Bingqiao Liu, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691018","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691018","url":null,"abstract":"A 0.1-5GHz Software-Defined Radio (SDR) transmitter in 65nm CMOS is presented. The transmitter integrates a dual-mode power amplifier (PA) for 0.1-1.5GHz low-cost narrowband applications (such as Industry Specific Applications, 2G, ZigBee), while a three-sub-band pre-power amplifier (PPA) is used for 0.45-5GHz high performance wideband applications (3G, 4G and etc.). A digital-assisted I/Q imbalance calibration circuit is proposed ahead the TX chain to pre-compensate I/Q mismatch in IF and LO modules. Analog baseband utilizes power scalable technique to optimize power consumption among different modes. The transmitter achieves -63.9dBc image rejection ratio (IRR) and -56.9dBc LO leakage rejection. In narrowband modes, the dual-mode PA provides >19dBm output P1dB with >20% PAE in its linear mode, and 23.2dBm maximum saturation power with 60% peak PAE in the switching mode. In wideband modes, the PPA provides maximum 9dBm output P1dB. F urthermore, system verifications demonstrate 0.5% EVM for 905MHz GSM at 19.5dBm output power. And the transmitter achieves -42.6dBc ACLR and 1.4% EVM for 2.3GHz LTE20 at 6.2dBm output.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125956324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.56mW 50MHz 3rd-order filter with current-mode active-RC biquad and 33dBm IIP3 in 65nm CMOS 1.56mW 50MHz三阶滤波器,电流型有源rc双置,33dBm IIP3, 65nm CMOS
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691060
Rakesh Kumar Palani, M. Sturm, R. Harjani
A novel inverter-based-integrator filter design is proposed that relaxes the UGB requirement of the OTAs by decoupling the integration capacitance from the feedback loop. The proposed scheme allows the entire filtering operation to take place in the current domain reducing power supply limitations. Further, in the design the load acts as the compensation capacitance to the OTAs allowing the majority of the current to flow into the load, increasing the overall power efficiency. As a proof of concept, a 3rd order lowpass filter is designed and implemented in an IBM 65nm CMOS process. The measured prototype designed for a 50MHz bandwidth achieves an IIP3 of +33dBm and 1.8X better FOM over state-of-art while drawing 1.3mA from a 1.2V supply, is capable of driving a lpF load, and occupies 6X smaller area.
提出了一种新的基于逆变器的积分器滤波器设计,通过将积分电容与反馈回路解耦来降低OTAs对UGB的要求。该方案允许整个滤波操作在电流域中进行,减少了电源的限制。此外,在设计中,负载充当ota的补偿电容,允许大部分电流流入负载,从而提高整体功率效率。作为概念验证,在IBM 65nm CMOS工艺中设计并实现了一个三阶低通滤波器。设计用于50MHz带宽的测量原型实现了+33dBm的IIP3和比最先进的1.8倍的FOM,同时从1.2V电源汲取1.3mA,能够驱动lpF负载,占地面积减少6倍。
{"title":"A 1.56mW 50MHz 3rd-order filter with current-mode active-RC biquad and 33dBm IIP3 in 65nm CMOS","authors":"Rakesh Kumar Palani, M. Sturm, R. Harjani","doi":"10.1109/ASSCC.2013.6691060","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691060","url":null,"abstract":"A novel inverter-based-integrator filter design is proposed that relaxes the UGB requirement of the OTAs by decoupling the integration capacitance from the feedback loop. The proposed scheme allows the entire filtering operation to take place in the current domain reducing power supply limitations. Further, in the design the load acts as the compensation capacitance to the OTAs allowing the majority of the current to flow into the load, increasing the overall power efficiency. As a proof of concept, a 3rd order lowpass filter is designed and implemented in an IBM 65nm CMOS process. The measured prototype designed for a 50MHz bandwidth achieves an IIP3 of +33dBm and 1.8X better FOM over state-of-art while drawing 1.3mA from a 1.2V supply, is capable of driving a lpF load, and occupies 6X smaller area.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128035972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder 750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC最小和模拟解码器
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691012
A. R. Abolfazli, Y. Shayan, G. Cowan
Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes implemented to date using analog techniques. At a Bit Error Rate of 10-5, the measured performance is within 0.2dB of modeled performance using floating-point arithmetic. The chip was tested at a throughput of 750Mb/s. This improves the throughput of analog decoders by a factor of 57. The power dissipation of the core is 13 mW resulting in 17pJ/b energy efficiency. The core area is 1.38mm2. The fabricated MS-based TS-LDPC analog decoder has BER performance nearly identical to theory without compromising energy efficiency.
介绍了一种基于(120,75)最小和的涡轮结构LDPC模拟解码器的电路和集成电路实现。这是迄今为止使用模拟技术实现的最高吞吐量和最长代码之一。在误码率为10-5的情况下,测量的性能与使用浮点运算建模的性能相差不超过0.2dB。该芯片的测试吞吐量为750Mb/s。这将模拟解码器的吞吐量提高了57倍。磁芯的功耗为13mw,能量效率为17pJ/b。核心面积为1.38平方毫米。制造的基于ms的TS-LDPC模拟解码器具有几乎与理论相同的误码率性能,而不影响能源效率。
{"title":"750Mb/s 17pJ/b 90nm CMOS (120,75) TS-LDPC Min-Sum based analog decoder","authors":"A. R. Abolfazli, Y. Shayan, G. Cowan","doi":"10.1109/ASSCC.2013.6691012","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691012","url":null,"abstract":"Circuit and IC implementation of a (120, 75) Min-Sum based Turbo-Structured LDPC analog decoder in CMOS 90nm technology is presented. This is the highest throughput and one of the longest codes implemented to date using analog techniques. At a Bit Error Rate of 10-5, the measured performance is within 0.2dB of modeled performance using floating-point arithmetic. The chip was tested at a throughput of 750Mb/s. This improves the throughput of analog decoders by a factor of 57. The power dissipation of the core is 13 mW resulting in 17pJ/b energy efficiency. The core area is 1.38mm2. The fabricated MS-based TS-LDPC analog decoder has BER performance nearly identical to theory without compromising energy efficiency.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134201234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Hybrid circuit and algorithmic timing error correction for low-power robust DSP accelerators 低功耗鲁棒DSP加速器的混合电路和时序纠错算法
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690974
P. Whatmough, Shidhartha Das, David M. Bull
Datapath accelerators are a key performance enabler for many digital signal processing systems. Razor provides a means to improve the performance and power efficiency of DSP accelerators by minimizing static guardbands. Unlike with Razor CPU implementations, recovery can be achieved without the complexity and intrusiveness of checkpoint and replay schemes. We demonstrate two recovery approaches, (1) a circuit-level technique that makes use of a small time borrowing window to efficiently correct marginal timing errors, and (2) an approximate error correction scheme to minimize error magnitude of large timing errors using an interpolation-based approach. Both techniques are demonstrated in a 65nm CMOS testchip. Measurement results show a 37% improvement in energy efficiency at 1GS/s using Razor, compared to a margined baseline on the same silicon. The proposed error detection and correction system is shown to maintain a 10% margin to account for fast-moving supply voltage noise.
数据路径加速器是许多数字信号处理系统的关键性能使能器。Razor提供了一种通过最小化静态保护带来提高DSP加速器性能和功率效率的方法。与Razor CPU实现不同,恢复可以在没有检查点和重放方案的复杂性和侵入性的情况下实现。我们展示了两种恢复方法,(1)一种电路级技术,利用小的时间借用窗口来有效地纠正边际时序误差,以及(2)一种近似误差校正方案,使用基于插值的方法来最小化大时序误差的误差幅度。这两种技术都在65nm CMOS测试芯片上进行了验证。测量结果显示,与在相同的硅上的边际基线相比,使用Razor在1GS/s时的能源效率提高了37%。所提出的误差检测和校正系统显示保持10%的余量,以考虑快速移动的电源电压噪声。
{"title":"Hybrid circuit and algorithmic timing error correction for low-power robust DSP accelerators","authors":"P. Whatmough, Shidhartha Das, David M. Bull","doi":"10.1109/ASSCC.2013.6690974","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690974","url":null,"abstract":"Datapath accelerators are a key performance enabler for many digital signal processing systems. Razor provides a means to improve the performance and power efficiency of DSP accelerators by minimizing static guardbands. Unlike with Razor CPU implementations, recovery can be achieved without the complexity and intrusiveness of checkpoint and replay schemes. We demonstrate two recovery approaches, (1) a circuit-level technique that makes use of a small time borrowing window to efficiently correct marginal timing errors, and (2) an approximate error correction scheme to minimize error magnitude of large timing errors using an interpolation-based approach. Both techniques are demonstrated in a 65nm CMOS testchip. Measurement results show a 37% improvement in energy efficiency at 1GS/s using Razor, compared to a margined baseline on the same silicon. The proposed error detection and correction system is shown to maintain a 10% margin to account for fast-moving supply voltage noise.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit 采用BL功率计算器和数字可控保持电路的双电源SRAM有效功耗降低27%,待机功耗降低85%
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6690973
K. Kushida, F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe, Y. Unekawa
This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.
本文介绍了SRAM电路技术,以降低有源和待机模式的功率,特别是在室温(RT)下,实际功耗占主导地位。位线功率计算器用于自适应设置主模式下的电池供电电压(VCS)。数字可控保持电路调节VCS在待机模式下,控制功率小。这些电路在28纳米CMOS技术的双电源SRAM中实现。与传统方案相比,25℃时主、待机模式的功耗分别降低27%和85%。
{"title":"A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit","authors":"K. Kushida, F. Tachibana, O. Hirabayashi, Y. Takeyama, M. Shizuno, A. Kawasumi, A. Suzuki, Y. Niki, S. Sasaki, T. Yabe, Y. Unekawa","doi":"10.1109/ASSCC.2013.6690973","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690973","url":null,"abstract":"This paper presents SRAM circuit techniques to reduce both active and standby mode power especially at room temperature (RT) where actual power consumption is dominant. A bit line power calculator is used to adaptively set the cell supply voltage (VCS) in the active mode. A digitally controllable retention circuit regulates VCS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28 nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25°C is reduced by 27% and 85%, respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125113455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS 集成60GHz 5Gb/s QPSK发射机,片上T/R开关和65nm CMOS全差分锁相环频率合成器
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691070
Lixue Kuang, B. Chi, Lei Chen, Meng Wei, Xiaobao Yu, Zhihua Wang
An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.
提出了一种带片上T/R开关和全差分锁相环频率合成器的60GHz 5Gb/s QPSK发射机。直接QPSK调制在第一次上转换期间实现,随后是最后的上转换混频器和功率放大器(PA)以及片上T/R开关。利用分布式放大器技术扩展扩频系统的带宽。与其他带宽扩展技术一起,最小化信号链路的带内增益变化以提高误差矢量幅度(EVM)。为了抑制共模噪声和改善相位噪声性能,实现了40GHz全差分锁相环频率合成器,以提供LO信号和各种时钟。测量到的输出功率在60GHz时为6.4dBm,在>6GHz带宽下增益变化为1.2dB。采用片上27-1 PRBS发生器测量发射机性能,在5Gb/s QPSK调制下,测量到的EVM为-21.9dB。发射机和锁相LO配网分别消耗73mW和62mW。
{"title":"An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS","authors":"Lixue Kuang, B. Chi, Lei Chen, Meng Wei, Xiaobao Yu, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691070","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691070","url":null,"abstract":"An integrated 60GHz 5Gb/s QPSK transmitter with on-chip T/R switch and fully-differential PLL frequency synthesizer in 65nm CMOS is presented. Direct QPSK modulation is implemented during the first up-conversion, followed by the final up-conversion mixer and power amplifier (PA) as well as on-chip T/R switch. Distributed amplifier technique is utilized to extend the bandwidth of PA. Along with other bandwidth extension techniques, in-band gain variation in signal link is minimized to improve the error vector magnitude (EVM). To reject common-mode noise and improve phase noise performance, a 40GHz fully-differential PLL frequency synthesizer is implemented to provide LO signals and various clocks. The measured output power is 6.4dBm at 60GHz, with 1.2dB gain variation over >6GHz bandwidth. On-chip 27-1 PRBS generators are used to measure the transmitter performance, and the measured EVM is -21.9dB with 5Gb/s QPSK modulation. The transmitter and the PLL & LO distribution network consume 73mW and 62mW, respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116153301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 6.3 mW high-SNR frame-rate scalable touch screen panel readout IC with column-parallel Σ-Δ ADC structure for mobile devices 一种6.3 mW高信噪比帧率可扩展触摸屏面板读出集成电路,具有列并行Σ-Δ ADC结构,用于移动设备
Pub Date : 2013-12-23 DOI: 10.1109/ASSCC.2013.6691056
Jun-Eun Park, Dong-Hyuk Lim, D. Jeong
This paper presents a capacitive touch screen panel (TSP) readout IC that provides highly enhanced signal-to-noise ratio (SNR) and scalable frame rate. To increase touch sensitivity and noise immunity, the proposed readout IC employs a differential sensing method. A column-parallel incremental sigma-delta (Σ-Δ) ADC structure is adopted to obtain high frame rate and its scalability. The readout IC is fabricated in 0.18-μm CMOS process and its active area is 2.2 mm2. The measured results show that the readout IC achieves 60-dB SNR and 200-Hz frame rate with 12 × 8 mutual capacitive TSP. The frame rate and SNR can be adjusted from 50 Hz to 1.6 kHz and from 50 dB to 67 dB, respectively. The power consumption is 6.3 mW with 3.3-V supply.
本文提出了一种电容式触摸屏面板(TSP)读出IC,它提供了高增强的信噪比(SNR)和可扩展的帧速率。为了提高触摸灵敏度和抗噪声能力,所提出的读出集成电路采用差分传感方法。采用列并行增量式sigma-delta (Σ-Δ) ADC结构,可获得高帧率和可扩展性。该读出IC采用0.18 μm CMOS工艺制作,其有源面积为2.2 mm2。测量结果表明,该读出IC在12 × 8互容TSP下实现了60 db的信噪比和200 hz的帧率。帧率和信噪比可分别在50hz ~ 1.6 kHz和50db ~ 67db范围内调节。功耗为6.3 mW, 3.3 v供电。
{"title":"A 6.3 mW high-SNR frame-rate scalable touch screen panel readout IC with column-parallel Σ-Δ ADC structure for mobile devices","authors":"Jun-Eun Park, Dong-Hyuk Lim, D. Jeong","doi":"10.1109/ASSCC.2013.6691056","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691056","url":null,"abstract":"This paper presents a capacitive touch screen panel (TSP) readout IC that provides highly enhanced signal-to-noise ratio (SNR) and scalable frame rate. To increase touch sensitivity and noise immunity, the proposed readout IC employs a differential sensing method. A column-parallel incremental sigma-delta (Σ-Δ) ADC structure is adopted to obtain high frame rate and its scalability. The readout IC is fabricated in 0.18-μm CMOS process and its active area is 2.2 mm2. The measured results show that the readout IC achieves 60-dB SNR and 200-Hz frame rate with 12 × 8 mutual capacitive TSP. The frame rate and SNR can be adjusted from 50 Hz to 1.6 kHz and from 50 dB to 67 dB, respectively. The power consumption is 6.3 mW with 3.3-V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124871261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
期刊
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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