Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691021
Takanori Nakao, Y. Hidaka, Sota Sakabayashi, T. Hashida, Y. Tomita, Y. Koyanagi, H. Tamura
We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded connection of a high-frequency equalizer (HFEQ) and a low-frequency equalizer (LFEQ). The HFEQ is adjusted by using the conventional filter-pattern method. For the LFEQ adjustment, we used a modified filter-pattern method where the pattern matching is performed based on the mark ratio (i.e., the probability of `1'), to enhance the gain of the parameter-adjusting feedback loop. The adaptation is performed in the background, i.e., while data is being received.
{"title":"An equalizer-adaptation logic for a 25-Gb/s wireline receiver in 28-nm CMOS","authors":"Takanori Nakao, Y. Hidaka, Sota Sakabayashi, T. Hashida, Y. Tomita, Y. Koyanagi, H. Tamura","doi":"10.1109/ASSCC.2013.6691021","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691021","url":null,"abstract":"We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded connection of a high-frequency equalizer (HFEQ) and a low-frequency equalizer (LFEQ). The HFEQ is adjusted by using the conventional filter-pattern method. For the LFEQ adjustment, we used a modified filter-pattern method where the pattern matching is performed based on the mark ratio (i.e., the probability of `1'), to enhance the gain of the parameter-adjusting feedback loop. The adaptation is performed in the background, i.e., while data is being received.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129034521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690997
Bo Wang, Jun Zhou, Kah-Hyong Chang, M. Je, T. T. Kim
This paper presents a 16-transistor charge-pumped DFF featuring a low energy-delay product for near-/sub-threshold applications. The device count of the proposed DFF is minimized by eliminating clock buffer and employing pass gates instead of transmission gates. To reduce the Clock-to-Q delay and improve variation resilience, two charge pumps and an anti-inverse-narrow-width-effect strategy are utilized, improving the performance by 23%. The proposed DFF is fully functional down to 0.18V and shows the energy-delay product of 13.1 pJ·ns at 100% data activity, achieving 51.8% improvement compared to the conventional TGFF. When VDD=0.5V, the energy-delay product is averagely enhanced by 50.8%. Two 256-bit FIFOs are implemented in 180nm CMOS technology using the proposed DFF and TGFF. The FIFO utilizing the charge-pumped DFF exhibits 31.2% total power reduction at subthreshold regime.
{"title":"A 0.18V charge-pumped DFF with 50.8% energy-delay reduction for near-/sub-threshold circuits","authors":"Bo Wang, Jun Zhou, Kah-Hyong Chang, M. Je, T. T. Kim","doi":"10.1109/ASSCC.2013.6690997","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690997","url":null,"abstract":"This paper presents a 16-transistor charge-pumped DFF featuring a low energy-delay product for near-/sub-threshold applications. The device count of the proposed DFF is minimized by eliminating clock buffer and employing pass gates instead of transmission gates. To reduce the Clock-to-Q delay and improve variation resilience, two charge pumps and an anti-inverse-narrow-width-effect strategy are utilized, improving the performance by 23%. The proposed DFF is fully functional down to 0.18V and shows the energy-delay product of 13.1 pJ·ns at 100% data activity, achieving 51.8% improvement compared to the conventional TGFF. When VDD=0.5V, the energy-delay product is averagely enhanced by 50.8%. Two 256-bit FIFOs are implemented in 180nm CMOS technology using the proposed DFF and TGFF. The FIFO utilizing the charge-pumped DFF exhibits 31.2% total power reduction at subthreshold regime.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117274954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691035
Wala Saadeh, Temesghen Tekeste, M. Perrott
A modified boost converter topology is proposed to achieve better than 89% efficiency as an LED driver for applications in which low supply voltage and low average current are desired such as in a photoplethysmographic (PPG) heart rate (HR) monitor device. The approach embraces pulsing of the LED current, and allows a highly digital implementation for varying LED brightness based on Pulse Density Modulation (PDM). Measured results indicate that the LED driver, which is implemented in 180nm CMOS along with an external inductor, achieves an output current range of 28uA to 1.3mA with 6 current settings while maintaining >89% efficiency over a supply voltage range of 0.5 to 0.6V.
{"title":"A > 89% efficient LED driver with 0.5V supply voltage for applications requiring low average current","authors":"Wala Saadeh, Temesghen Tekeste, M. Perrott","doi":"10.1109/ASSCC.2013.6691035","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691035","url":null,"abstract":"A modified boost converter topology is proposed to achieve better than 89% efficiency as an LED driver for applications in which low supply voltage and low average current are desired such as in a photoplethysmographic (PPG) heart rate (HR) monitor device. The approach embraces pulsing of the LED current, and allows a highly digital implementation for varying LED brightness based on Pulse Density Modulation (PDM). Measured results indicate that the LED driver, which is implemented in 180nm CMOS along with an external inductor, achieves an output current range of 28uA to 1.3mA with 6 current settings while maintaining >89% efficiency over a supply voltage range of 0.5 to 0.6V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126622827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691076
J. Anders, J. Handwerker, M. Ortmanns, G. Boero
In this paper, we present a fully integrated receiver for NMR microscopy applications realized in a 0.13 μm CMOS technology. The chip co-integrates a planar detection coil together with a complete low-IF downconversion receiver consisting of a low noise amplifier, a quadrature downconversion mixer, a baseband amplifier stage and line drivers. The chip operates from a single 1.5V supply and consumes about 12mA of current. The active chip area is about 350×450 μm2. The detector's measured input referred voltage noise density at the operating frequency of 300 MHz is 260 pV/√Hz resulting in a measured spin sensitivity of 2×1013 spins/√Hz. Preliminary imaging experiments demonstrate the chip's capability of recording micron resolution MR images in imaging times which significantly advance the state-of-the-art.
{"title":"A fully-integrated detector for NMR microscopy in 0.13μm CMOS","authors":"J. Anders, J. Handwerker, M. Ortmanns, G. Boero","doi":"10.1109/ASSCC.2013.6691076","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691076","url":null,"abstract":"In this paper, we present a fully integrated receiver for NMR microscopy applications realized in a 0.13 μm CMOS technology. The chip co-integrates a planar detection coil together with a complete low-IF downconversion receiver consisting of a low noise amplifier, a quadrature downconversion mixer, a baseband amplifier stage and line drivers. The chip operates from a single 1.5V supply and consumes about 12mA of current. The active chip area is about 350×450 μm2. The detector's measured input referred voltage noise density at the operating frequency of 300 MHz is 260 pV/√Hz resulting in a measured spin sensitivity of 2×1013 spins/√Hz. Preliminary imaging experiments demonstrate the chip's capability of recording micron resolution MR images in imaging times which significantly advance the state-of-the-art.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122018819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690979
A. Paul, Dong Jiao, S. Sapatnekar, C. Kim
A switched capacitor step-down converter fabricated in 32nm CMOS achieves a 5X improvement in response time for fast dynamic voltage and frequency scaling (DVFS). We also present a step-up converter based on a bi-directional voltage doubler, which is capable of reducing supply noise up to 45% by opportunistically borrowing current from adjacent idle power domains. Using ultra-high density deep trench capacitors, we are able to achieve an output power density of 2.78W/mm2 at a peak efficiency of 85% from the step-down converter and 0.9W/mm2 at a peak efficiency of 82% from the voltage doubler.
{"title":"Deep trench capacitor based step-up and step-down DC/DC converters in 32nm SOI with opportunistic current borrowing and fast DVFS capabilities","authors":"A. Paul, Dong Jiao, S. Sapatnekar, C. Kim","doi":"10.1109/ASSCC.2013.6690979","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690979","url":null,"abstract":"A switched capacitor step-down converter fabricated in 32nm CMOS achieves a 5X improvement in response time for fast dynamic voltage and frequency scaling (DVFS). We also present a step-up converter based on a bi-directional voltage doubler, which is capable of reducing supply noise up to 45% by opportunistically borrowing current from adjacent idle power domains. Using ultra-high density deep trench capacitors, we are able to achieve an output power density of 2.78W/mm2 at a peak efficiency of 85% from the step-down converter and 0.9W/mm2 at a peak efficiency of 82% from the voltage doubler.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"75 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128066151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691025
T. T. Kim, Ngoc Le Ba
An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking bitline sensing margin enhancement technique to improve the bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.
{"title":"A low voltage 8-T SRAM with PVT-tracking bitline sensing margin enhancement for high operating temperature (up to 300°C)","authors":"T. T. Kim, Ngoc Le Ba","doi":"10.1109/ASSCC.2013.6691025","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691025","url":null,"abstract":"An 8-Kbit low power 8-T SRAM for high temperature (up to 300°C) applications is presented. Near-threshold operation is selected for minimum performance variations over a wide temperate range. We proposed a PVT-tracking bitline sensing margin enhancement technique to improve the bitline swing and the sensing window. Test chips fabricated in a commercial 1.0-μm SOI technology with high temperature interconnection option demonstrates successful SRAM operation at 2 V, 300°C. The power consumption and access time of 0.94 mW and 256ns was achieved at 2 V and 300°C.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"37 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123179576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691029
Y. Umeki, Koji Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, T. Sugii
This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.
{"title":"A 0.38-V operating STT-MRAM with process variation tolerant sense amplifier","authors":"Y. Umeki, Koji Yanagida, S. Yoshimoto, S. Izumi, M. Yoshimoto, H. Kawaguchi, K. Tsunoda, T. Sugii","doi":"10.1109/ASSCC.2013.6691029","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691029","url":null,"abstract":"This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin in any process corner. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 6.15 μW at that voltage. The minimum energy per access is 3.89 pJ/bit when the supply voltage is 0.44 V. The proposed STT-MRAM operates at lower energy than SRAM when a utilization of a memory bandwidth is 14% or less.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129524828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691066
Amrith Sukumaran, Kunal Karanjkar, Sandeep Jhanwar, N. Krishnapura, S. Pavan
We describe a low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process. The IC accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the DSP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece, all over a 10kHz bandwidth. The programmable gain amplifier uses current sharing in the input stage to obtain low noise with low power consumption. The single-bit continuous-time ΔΣ ADC and the closed loop class-D amplifier use assisted opamp integrators to reduce power dissipation. An on chip ring oscillator provides the clock to the digital parts of the chip and to the digital signal processor (DSP). The chip has an input referred noise of 2.1μV, a dynamic range of 106 dB, an output THD of 0.006% and a peak output SNR of 79dB. It occupies 2.3 mm2 and consumes 285μA from a 1.2V supply.
{"title":"A 1.2 V 285μA analog front end chip for a digital hearing aid in 0.13 μm CMOS","authors":"Amrith Sukumaran, Kunal Karanjkar, Sandeep Jhanwar, N. Krishnapura, S. Pavan","doi":"10.1109/ASSCC.2013.6691066","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691066","url":null,"abstract":"We describe a low power analog front-end for a digital hearing aid, designed and fabricated in a 0.13μm CMOS process. The IC accepts inputs from a microphone or telecoil, amplifies and digitizes it for processing by a DSP, accepts digital data from the DSP, converts it to analog form using a pulse width modulated class D amplifier, and drives the earpiece, all over a 10kHz bandwidth. The programmable gain amplifier uses current sharing in the input stage to obtain low noise with low power consumption. The single-bit continuous-time ΔΣ ADC and the closed loop class-D amplifier use assisted opamp integrators to reduce power dissipation. An on chip ring oscillator provides the clock to the digital parts of the chip and to the digital signal processor (DSP). The chip has an input referred noise of 2.1μV, a dynamic range of 106 dB, an output THD of 0.006% and a peak output SNR of 79dB. It occupies 2.3 mm2 and consumes 285μA from a 1.2V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129553675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691068
Jelle Van Rethy, G. Gielen
This paper presents the optimization and implementation of an area- and energy-efficient capacitance-controlled oscillator-based sensor interface, which outputs a period-modulated signal. This time-based output signal can easily be digitized with a reset counter, which benefits from firstorder quantization noise shaping and oversampling. The circuit is prototyped in 130-nm CMOS technology and takes only 0.05 mm2. The performance is validated with both an external variable capacitor and a bare-die MEMS capacitive pressure sensor. The chip consumes 371 μW from a 1.2-V supply voltage and achieves 10.5-b resolution with 10-kHz input bandwidth for an input capacitance ranging from 3.7 to 13.7 pF. For both the external capacitor and the MEMS sensor, measurements show an improved energy efficiency compared to prior period modulation-based sensor interfaces.
{"title":"An energy-efficient capacitance-controlled oscillator-based sensor interface for MEMS sensors","authors":"Jelle Van Rethy, G. Gielen","doi":"10.1109/ASSCC.2013.6691068","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691068","url":null,"abstract":"This paper presents the optimization and implementation of an area- and energy-efficient capacitance-controlled oscillator-based sensor interface, which outputs a period-modulated signal. This time-based output signal can easily be digitized with a reset counter, which benefits from firstorder quantization noise shaping and oversampling. The circuit is prototyped in 130-nm CMOS technology and takes only 0.05 mm2. The performance is validated with both an external variable capacitor and a bare-die MEMS capacitive pressure sensor. The chip consumes 371 μW from a 1.2-V supply voltage and achieves 10.5-b resolution with 10-kHz input bandwidth for an input capacitance ranging from 3.7 to 13.7 pF. For both the external capacitor and the MEMS sensor, measurements show an improved energy efficiency compared to prior period modulation-based sensor interfaces.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134166468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691063
Amrith Sukumaran, S. Pavan
An optimally designed FIR feedback DAC is used in a third order, single bit continuous-time delta sigma modulator to reduce power dissipation and jitter sensitivity. The loop filter is carefully stabilized for the delay added by the FIR DAC. A current reuse two stage feedforward compensated opamp minimizes current consumption in the first integrator. The efficacy of our techniques is borne out by measurements from a 17 bit audio converter designed in a 0.18 μm CMOS technology. It achieves 103 dB dynamic range, 102 dB A-Weighted SNR and 106 dB SFDR in a 24 kHz bandwidth and dissipates 280 μW from a 1.8 V supply.
优化设计的FIR反馈DAC用于三阶单比特连续δ σ调制器，以降低功耗和抖动灵敏度。环路滤波器对FIR DAC增加的延迟进行了仔细的稳定。电流复用两级前馈补偿运放最大限度地减少了第一个积分器的电流消耗。采用0.18 μm CMOS技术设计的17位音频转换器的测量结果证明了我们技术的有效性。在24 kHz带宽下实现103 dB动态范围、102 dB a加权信噪比和106 dB SFDR, 1.8 V电源功耗280 μW。
{"title":"A 280μW audio continuous-time ΔΣ modulator with 103dB DR and 102dB A-Weighted SNR","authors":"Amrith Sukumaran, S. Pavan","doi":"10.1109/ASSCC.2013.6691063","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691063","url":null,"abstract":"An optimally designed FIR feedback DAC is used in a third order, single bit continuous-time delta sigma modulator to reduce power dissipation and jitter sensitivity. The loop filter is carefully stabilized for the delay added by the FIR DAC. A current reuse two stage feedforward compensated opamp minimizes current consumption in the first integrator. The efficacy of our techniques is borne out by measurements from a 17 bit audio converter designed in a 0.18 μm CMOS technology. It achieves 103 dB dynamic range, 102 dB A-Weighted SNR and 106 dB SFDR in a 24 kHz bandwidth and dissipates 280 μW from a 1.8 V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132933074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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