Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691071
Xiang Yi, C. Boon, Junyi Sun, N. Huang, W. M. Lim
A low phase noise 24/77 GHz dual-band subsampling PLL with a dual-band VCO is presented. Implemented in 65 nm CMOS technology, the proposed PLL occupies an area of 900 μm × 550 μm. The measured phase noise is -120.0 and -108.5 dBc/Hz at 1 MHz offset in 24 and 77 GHz modes respectively. With 1.3 V supply, the power consumption is 26.4 and 31.5 mW for 24 and 77 GHz modes respectively. Compared with other state-of-the-art works, the proposed PLL has the best phase noise performance among all of reported PLLs for automotive radar applications.
{"title":"A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology","authors":"Xiang Yi, C. Boon, Junyi Sun, N. Huang, W. M. Lim","doi":"10.1109/ASSCC.2013.6691071","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691071","url":null,"abstract":"A low phase noise 24/77 GHz dual-band subsampling PLL with a dual-band VCO is presented. Implemented in 65 nm CMOS technology, the proposed PLL occupies an area of 900 μm × 550 μm. The measured phase noise is -120.0 and -108.5 dBc/Hz at 1 MHz offset in 24 and 77 GHz modes respectively. With 1.3 V supply, the power consumption is 26.4 and 31.5 mW for 24 and 77 GHz modes respectively. Compared with other state-of-the-art works, the proposed PLL has the best phase noise performance among all of reported PLLs for automotive radar applications.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690984
Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins
This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.
{"title":"A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS","authors":"Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2013.6690984","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690984","url":null,"abstract":"This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128289215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691009
Xian Tang, K. Pun, W. Ng
This paper presents a new low-voltage temperature sensor which uses resistor as the sensing element and digitizes in time domain. Fabricated in 90nm CMOS, the sensor measures an inaccuracy of -0.6°C/0.8°C over -40°C~125°C range and a peak supply sensitivity of 4°C/V after two-point calibration at 25°C and 45°C. It dissipates 11.8μW at a sampling rate of 5kS/s from a 0.9V supply.
{"title":"A 0.9V 5kS/s resistor-based time-domain temperature sensor in 90nm CMOS with calibrated inaccuracy of −0.6°C/0.8°C from −40°C to 125°C","authors":"Xian Tang, K. Pun, W. Ng","doi":"10.1109/ASSCC.2013.6691009","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691009","url":null,"abstract":"This paper presents a new low-voltage temperature sensor which uses resistor as the sensing element and digitizes in time domain. Fabricated in 90nm CMOS, the sensor measures an inaccuracy of -0.6°C/0.8°C over -40°C~125°C range and a peak supply sensitivity of 4°C/V after two-point calibration at 25°C and 45°C. It dissipates 11.8μW at a sampling rate of 5kS/s from a 0.9V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127037465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690991
Chin Yin, C. Hsieh
This paper proposes a 0.5V smart image sensor with multi-operation modes of edge extraction, centroid tracking, and high-dynamic-range imaging output. The 0.5V operated pulse-width-modulation (PWM) sensor [1] is applied to achieve a high dynamic range (HDR) response and reduce the fixed pattern noise (FPN). The array-level analog signal processing (ASP) is implemented by local inter-pixel feedback and the event-driven (ED) hand-shaking readout. A prototype chip of smart image sensor with 64×64 CIS array was fabricated in 0.18um CMOS technology. The prototype has been verified to demonstrate the features of real-time edge extraction, object tracking, and high-dynamic range imaging successfully. The measurement results show a power dissipation of 34.4uW in edge extraction mode, a frame rate of 14.28kfps and a tracking error of 0.36 pixels in centroid tracking mode, and a high dynamic range (DR) of 105dB in imaging mode.
{"title":"A 0.5V 34.4uW 14.28kfps 105dB smart image sensor with array-level analog signal processing","authors":"Chin Yin, C. Hsieh","doi":"10.1109/ASSCC.2013.6690991","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690991","url":null,"abstract":"This paper proposes a 0.5V smart image sensor with multi-operation modes of edge extraction, centroid tracking, and high-dynamic-range imaging output. The 0.5V operated pulse-width-modulation (PWM) sensor [1] is applied to achieve a high dynamic range (HDR) response and reduce the fixed pattern noise (FPN). The array-level analog signal processing (ASP) is implemented by local inter-pixel feedback and the event-driven (ED) hand-shaking readout. A prototype chip of smart image sensor with 64×64 CIS array was fabricated in 0.18um CMOS technology. The prototype has been verified to demonstrate the features of real-time edge extraction, object tracking, and high-dynamic range imaging successfully. The measurement results show a power dissipation of 34.4uW in edge extraction mode, a frame rate of 14.28kfps and a tracking error of 0.36 pixels in centroid tracking mode, and a high dynamic range (DR) of 105dB in imaging mode.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114608848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691078
Yuan Gao, Darmayuda I. Made, San-Jeow Cheng, M. Je, C. Heng
A high efficiency energy-autonomous interface circuit for piezoelectric energy harvester is presented in this paper. The proposed circuit includes a negative voltage converter (NVC) with dynamic body bias control, a reconfigurable switching converter working in discontinuous conduction mode (DCM) and a clock generator. The body biasing circuit provides dynamic forward body bias control to enhance NVC conversion efficiency in low input voltage range and reduce substrate leakage under high input voltage range. A reconfigurable switching converter in DCM boost/buck-boost modes provides synthesized resistive input impedance for power matching and voltage step-up. Implemented in a standard 65nm CMOS process, the proposed system has a measured cold startup voltage of 0.3V with a maximum conversion efficiency of 70%.
{"title":"An energy-autonomous piezoelectric energy harvester interface circuit with 0.3V startup voltage","authors":"Yuan Gao, Darmayuda I. Made, San-Jeow Cheng, M. Je, C. Heng","doi":"10.1109/ASSCC.2013.6691078","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691078","url":null,"abstract":"A high efficiency energy-autonomous interface circuit for piezoelectric energy harvester is presented in this paper. The proposed circuit includes a negative voltage converter (NVC) with dynamic body bias control, a reconfigurable switching converter working in discontinuous conduction mode (DCM) and a clock generator. The body biasing circuit provides dynamic forward body bias control to enhance NVC conversion efficiency in low input voltage range and reduce substrate leakage under high input voltage range. A reconfigurable switching converter in DCM boost/buck-boost modes provides synthesized resistive input impedance for power matching and voltage step-up. Implemented in a standard 65nm CMOS process, the proposed system has a measured cold startup voltage of 0.3V with a maximum conversion efficiency of 70%.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129176053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691019
Hoai-Nam Nguyen, Jang-Hong Choi, Byung-Hun Min, Mi-Jeong Park, M. Park, Seok-Kyun Han, Sang-Gug Lee, C. Kim
This paper presents the design of a low-power small-size transmitter with discrete-time baseband filter for LTE application operating at 1.8-2 GHz. The transmitter achieves 4.5 dBm output power with more than -46 dBc of LO feedthrough suppression and -38 dBc image rejection ratio. At -0.3 dBm transmitted power of LTE 5 MHz channel, ACLR is measured below -42 dBc for both upper and lower channels with 1.83 and 2.47 % EVM for QPSK and 16-QAM modulation signals, respectively. The prototype chip is fabricated in a 65 nm CMOS technology and dissipates 59 mA current from 1.2 V supply and 13 mA from 2.5 V supply.
{"title":"A low-power small-size transmitter with discrete-time baseband filter for LTE in 65 nm CMOS","authors":"Hoai-Nam Nguyen, Jang-Hong Choi, Byung-Hun Min, Mi-Jeong Park, M. Park, Seok-Kyun Han, Sang-Gug Lee, C. Kim","doi":"10.1109/ASSCC.2013.6691019","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691019","url":null,"abstract":"This paper presents the design of a low-power small-size transmitter with discrete-time baseband filter for LTE application operating at 1.8-2 GHz. The transmitter achieves 4.5 dBm output power with more than -46 dBc of LO feedthrough suppression and -38 dBc image rejection ratio. At -0.3 dBm transmitted power of LTE 5 MHz channel, ACLR is measured below -42 dBc for both upper and lower channels with 1.83 and 2.47 % EVM for QPSK and 16-QAM modulation signals, respectively. The prototype chip is fabricated in a 65 nm CMOS technology and dissipates 59 mA current from 1.2 V supply and 13 mA from 2.5 V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133418681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691013
C. Brendler, Naser Pour Aryan, V. Rieger, S. Klinger, A. Rothermel
A power control circuit by magnetic field diminish-ment in inductively powered biomedical implants is presented. Due to large and fast coupling variations in inductively powered retinal implants caused by the eye movements, excessive power has to be controlled. This proposal attenuates the magnetic field in the secondary coil to reduce received power. Coil shorting is realized by applying short enough pulses to enable a parallel ASK data transmission. The system was fabricated and measured using a 350 nm BiCMOS High Voltage technology. Measurement results show a reduction of the thermal power generated by the implant.
{"title":"Power control by magnetic field diminishment in inductively powered biomedical implants","authors":"C. Brendler, Naser Pour Aryan, V. Rieger, S. Klinger, A. Rothermel","doi":"10.1109/ASSCC.2013.6691013","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691013","url":null,"abstract":"A power control circuit by magnetic field diminish-ment in inductively powered biomedical implants is presented. Due to large and fast coupling variations in inductively powered retinal implants caused by the eye movements, excessive power has to be controlled. This proposal attenuates the magnetic field in the secondary coil to reduce received power. Coil shorting is realized by applying short enough pulses to enable a parallel ASK data transmission. The system was fabricated and measured using a 350 nm BiCMOS High Voltage technology. Measurement results show a reduction of the thermal power generated by the implant.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133424496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a 130mW 16-core mobile GPU is fabricated with TSMC 45nm technology. With three approximation techniques, this proposed architecture can trade-off between power consumption and visual quality to provide power-aware ability. Implementation results show that, with satisfactory visual quality, 53% of the power consumption can be reduced with the proposed Approximated Precision Shader architecture and Screen-space Approximated Lighting technique. Moreover, the Approximated Texturing technique reduces 24.57% L1 cache requests in our evaluation.
{"title":"A 130.3mW 16-core mobile GPU with power-aware approximation techniques","authors":"Yu-Jung Chen, Shan-Yi Chuang, Chung-Yao Hung, Chao-Hsien Hsu, Chia-Ming Chang, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/ASSCC.2013.6691041","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691041","url":null,"abstract":"In this work, a 130mW 16-core mobile GPU is fabricated with TSMC 45nm technology. With three approximation techniques, this proposed architecture can trade-off between power consumption and visual quality to provide power-aware ability. Implementation results show that, with satisfactory visual quality, 53% of the power consumption can be reduced with the proposed Approximated Precision Shader architecture and Screen-space Approximated Lighting technique. Moreover, the Approximated Texturing technique reduces 24.57% L1 cache requests in our evaluation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting true capacitive-to-digital converter (CDC) without Analog-to-Digital Converter (ADC). The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between ±8g and support the 4-level adjustable resolutions of 0.1g/ 0.2g/ 0.4g/ 0.8g for each axis. The proposed readout circuit with 0.0354mm2 area is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show power consumption is 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency and 0.1g acceleration sensitivity for 0.2fF MEMS capacitance change.
{"title":"0.0354mm 82μW 125KS/s 3-axis readout circuit for capacitive MEMS accelerometer","authors":"Kelvin Yi-Tse Lai, Zih-Cheng He, Yu-Tao Yang, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ASSCC.2013.6690994","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690994","url":null,"abstract":"In this paper, we propose a power/area-efficient capacitive readout circuit for the Micro-Electro-Mechanical Systems (MEMS) sensor of 3-axis accelerometer. The proposed architecture is different from other traditional structures by exploiting true capacitive-to-digital converter (CDC) without Analog-to-Digital Converter (ADC). The proposed CDC can differentiate the bidirectional 125KS/s 80-level accelerations between ±8g and support the 4-level adjustable resolutions of 0.1g/ 0.2g/ 0.4g/ 0.8g for each axis. The proposed readout circuit with 0.0354mm2 area is fabricated in UMC 0.18um CMOS-MEMS process. Experimental results show power consumption is 50uW with 1.8V supply voltage for 1-axis (FOM=3.84pJ), 82uW for 3-axis (FOM=2.1pJ) under 125KHz of sampling frequency and 0.1g acceleration sensitivity for 0.2fF MEMS capacitance change.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691043
Chang-Hung Tsai, Hsiuan-Ting Wang, Chia-Lin Liu, Yao Li, Chen-Yi Lee
An architecture of H.265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H.265/HEVC video decoder occupies an area of 1.60×1.98mm2 to achieve 1080p@30fps and 720p@30fps realtime decoding with power consumption of 36.90 and 9.57mW.
{"title":"A 446.6K-gates 0.55–1.2V H.265/HEVC decoder for next generation video applications","authors":"Chang-Hung Tsai, Hsiuan-Ting Wang, Chia-Lin Liu, Yao Li, Chen-Yi Lee","doi":"10.1109/ASSCC.2013.6691043","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691043","url":null,"abstract":"An architecture of H.265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H.265/HEVC video decoder occupies an area of 1.60×1.98mm2 to achieve 1080p@30fps and 720p@30fps realtime decoding with power consumption of 36.90 and 9.57mW.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115371711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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