Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690988
Changyi Yang, Fule Li, Weitao Li, Xuan Wang, Zhihua Wang
A low-power 14-bit 150MS/s pipelined ADC is presented. This prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. Range-scaling in the first stage enables a maximal 2Vp-p input signal swing with a power-efficient single-stage opamp. Opamp and capacitor sharing between the first and second stage reduces the opamp power consumption further. And the sample-and-hold amplifier (SHA)-less technique is also used to lower the power dissipation and noise. With digital calibration, the SNDR of the ADC is 71.3dB with a 2.4MHz input, and remains higher than 68dB for input frequencies up to 150MHz. The ADC consumes 85mW, which includes 57mW for the ADC core, 11mW for the low jitter clock receiver and 17mW for the high-speed reference buffer.
{"title":"An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS","authors":"Changyi Yang, Fule Li, Weitao Li, Xuan Wang, Zhihua Wang","doi":"10.1109/ASSCC.2013.6690988","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690988","url":null,"abstract":"A low-power 14-bit 150MS/s pipelined ADC is presented. This prototype ADC is fabricated in a 130nm CMOS process with a 1.3-V supply voltage. Range-scaling in the first stage enables a maximal 2Vp-p input signal swing with a power-efficient single-stage opamp. Opamp and capacitor sharing between the first and second stage reduces the opamp power consumption further. And the sample-and-hold amplifier (SHA)-less technique is also used to lower the power dissipation and noise. With digital calibration, the SNDR of the ADC is 71.3dB with a 2.4MHz input, and remains higher than 68dB for input frequencies up to 150MHz. The ADC consumes 85mW, which includes 57mW for the ADC core, 11mW for the low jitter clock receiver and 17mW for the high-speed reference buffer.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114614212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690995
Valentijn De Smedt, G. Gielen, W. Dehaene
A fully-integrated, oscillator-based sensor interface for RFIDs and low-power applications is presented in this article. The circuit is processed and tested in a 40 nm CMOS technology. The interface translates the analog sensor signal, coming from a differential sensor, into a Pulse width Modulated (PWM) signal of which the duty cycle is proportional to the sensor value. Due to the high control linearity of the used oscillator, the interface has a low nonlinearity and can be made highly temperature and supply voltage independent. The total power consumption is 18 μW at 1.0 V and the interface works over a 0.8 to 1.5 V supply voltage range and a -20 to 100°C temperature range. The voltage dependency is below 1.42 %/V and the maximum temperature dependency is 79 ppm/°C. The oscillator frequency is slightly above 2 MHz in all circumstances. The measured SNDR of 47.4 dB results in a FOM of 66 fJ/b-conv.
{"title":"A 40nm-CMOS, 18 μW, temperature and supply voltage independent sensor interface for RFID tags","authors":"Valentijn De Smedt, G. Gielen, W. Dehaene","doi":"10.1109/ASSCC.2013.6690995","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690995","url":null,"abstract":"A fully-integrated, oscillator-based sensor interface for RFIDs and low-power applications is presented in this article. The circuit is processed and tested in a 40 nm CMOS technology. The interface translates the analog sensor signal, coming from a differential sensor, into a Pulse width Modulated (PWM) signal of which the duty cycle is proportional to the sensor value. Due to the high control linearity of the used oscillator, the interface has a low nonlinearity and can be made highly temperature and supply voltage independent. The total power consumption is 18 μW at 1.0 V and the interface works over a 0.8 to 1.5 V supply voltage range and a -20 to 100°C temperature range. The voltage dependency is below 1.42 %/V and the maximum temperature dependency is 79 ppm/°C. The oscillator frequency is slightly above 2 MHz in all circumstances. The measured SNDR of 47.4 dB results in a FOM of 66 fJ/b-conv.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691073
Haikun Jia, B. Chi, Lixue Kuang, Zhihua Wang
A self-healing mm-wave amplifier using digital controlled artificial dielectric (DiCAD) transmission lines is proposed. DiCAD transmission lines are employed to correct the frequency shifting of input matching (S11), output matching (S22) and gain (S21) due to process, voltage and temperature (PVT) variation and model inaccuracy. On-chip power detector is integrated into the amplifier to detect the output voltage strength, which could be used to implement the closed-loop frequency self-calibration. The chip is implemented in 65nm CMOS with a die area of 0.48×0.79 mm2 including the PADs. Measurement results show that the gain of the amplifier is improved by 3.4dB and the input matching is improved by 20.3dB at 56GHz after healing.
{"title":"A self-healing mm-wave amplifier using digital controlled artificial dielectric transmission lines","authors":"Haikun Jia, B. Chi, Lixue Kuang, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691073","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691073","url":null,"abstract":"A self-healing mm-wave amplifier using digital controlled artificial dielectric (DiCAD) transmission lines is proposed. DiCAD transmission lines are employed to correct the frequency shifting of input matching (S11), output matching (S22) and gain (S21) due to process, voltage and temperature (PVT) variation and model inaccuracy. On-chip power detector is integrated into the amplifier to detect the output voltage strength, which could be used to implement the closed-loop frequency self-calibration. The chip is implemented in 65nm CMOS with a die area of 0.48×0.79 mm2 including the PADs. Measurement results show that the gain of the amplifier is improved by 3.4dB and the input matching is improved by 20.3dB at 56GHz after healing.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125733569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690978
Xin Zhang, Yasuyuki Okuma, Po-Hung Chen, K. Ishida, Y. Ryu, Kazumori Watanabe, T. Sakurai, M. Takamiya
A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias & zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.
{"title":"A 0.6-V input 94% peak efficiency CCM/DCM digital buck converter in 40-nm CMOS with dual-mode-body-biased zero-crossing detector","authors":"Xin Zhang, Yasuyuki Okuma, Po-Hung Chen, K. Ishida, Y. Ryu, Kazumori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/ASSCC.2013.6690978","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690978","url":null,"abstract":"A 0.6-V input, 0.3-0.55V output buck converter is developed in 40-nm CMOS, for low-voltage low-power wireless sensor network systems. The buck converter is able to automatically select DCM or CCM operation, therefore improving the power efficiency and enlarging the output current range, by virtue of the proposed low-power CCM/DCM controller. A dual-mode-body-biased (DMBB) (forward body bias & zero body bias) low-voltage zero-crossing detector is designed to enable DCM operation with both low supply voltage and normal supply voltage. The proposed buck converter achieves a peak efficiency of 94% with an output current range of 50μA to 10mA. Thanks to the DCM operation, the efficiency at an output current of 100μA is improved by 20% and 9%, with an output voltage of 0.35V and 0.5V, respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A PWM receiver, without using a PLL or DLL, is proposed in this paper. This receiver does not need any synchronization (sync) bit sequence for locking on to the incoming data rate. No requirement of sync bits increases not only link throughput, but also reduces overall link power by allowing quick burst-sleep-burst transitions. A PWM bit symbol is decoded by time-to-voltage conversions of PWM major and minor durations followed by a comparison between them. Three such decoders are used in a time interleaved fashion to extract three consecutive PWM bits to achieve 1.2Gbps bit rate. Jitter tolerance measurement shows a high frequency jitter tolerance of 0.45UI at 1.2Gbps. This PWM receiver is fabricated in 40nm bulk CMOS process. It consumes 5.5mW and occupies an area of 0.0389mm2.
{"title":"A low power 1.2Gbps sync-less integrating PWM receiver","authors":"Anchal Jain, Sajal Kumar Mandal, Tapas Nandy, Vivek Uppal","doi":"10.1109/ASSCC.2013.6691024","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691024","url":null,"abstract":"A PWM receiver, without using a PLL or DLL, is proposed in this paper. This receiver does not need any synchronization (sync) bit sequence for locking on to the incoming data rate. No requirement of sync bits increases not only link throughput, but also reduces overall link power by allowing quick burst-sleep-burst transitions. A PWM bit symbol is decoded by time-to-voltage conversions of PWM major and minor durations followed by a comparison between them. Three such decoders are used in a time interleaved fashion to extract three consecutive PWM bits to achieve 1.2Gbps bit rate. Jitter tolerance measurement shows a high frequency jitter tolerance of 0.45UI at 1.2Gbps. This PWM receiver is fabricated in 40nm bulk CMOS process. It consumes 5.5mW and occupies an area of 0.0389mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125654688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691062
Jianping Guo, K. Leung
A CMOS low-dropout regulator (LDO) with high power-supply rejection ratio (PSRR) achieved by the proposed supply ripple feed-forward path is presented in this paper. The LDO is simple with two additional low-pass filters included. No extra power is consumed when comparing to the traditional design. The proposed LDO is implemented in 0.18-μ m CMOS technology. It occupies active area of 0.042 mm2. With the proposed embedded supply ripple feed-forward path, in the maximum loading of 25 mA, it achieves PSRR of -85 dB at 2.5 MHz and PSRR better than -55 dB when frequency is below 5 MHz with a 4.7-μF output capacitor. The measured quiescent current is 15 μA only. The overshoot and undershoot voltages are less than 40 mV when loading changes between 1 mA and 25 mA within 40 ns. The LDO achieves line and load regulations of 3 mV/V and 50 μV/mA, respectively.
{"title":"A 25mA CMOS LDO with −85dB PSRR at 2.5MHz","authors":"Jianping Guo, K. Leung","doi":"10.1109/ASSCC.2013.6691062","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691062","url":null,"abstract":"A CMOS low-dropout regulator (LDO) with high power-supply rejection ratio (PSRR) achieved by the proposed supply ripple feed-forward path is presented in this paper. The LDO is simple with two additional low-pass filters included. No extra power is consumed when comparing to the traditional design. The proposed LDO is implemented in 0.18-μ m CMOS technology. It occupies active area of 0.042 mm2. With the proposed embedded supply ripple feed-forward path, in the maximum loading of 25 mA, it achieves PSRR of -85 dB at 2.5 MHz and PSRR better than -55 dB when frequency is below 5 MHz with a 4.7-μF output capacitor. The measured quiescent current is 15 μA only. The overshoot and undershoot voltages are less than 40 mV when loading changes between 1 mA and 25 mA within 40 ns. The LDO achieves line and load regulations of 3 mV/V and 50 μV/mA, respectively.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129177847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691007
Chun-Fu Liao, Jhong-Yu Wang, Yuan-Hao Huang
This study presents a joint QR decomposition and lattice reduction processor for 8×8 multiple-input multiple-output (MIMO) systems. The proposed algorithm enhances the BER performance by lattice reduction and reduces the hardware cost by sharing computation units and removing redundant operations. This processor can be reconfigured as three different modes, including joint QR decomposition and lattice reduction, lattice reduction, and QR decomposition. The proposed processor was implemented in TSMC 90nm 1P9M CMOS technology. The maximum throughput is 1.1 M matrix/s for QR decomposition, and 0.5 M matrix/s for the lattice reduction, and 0.33 M matrix/s for the joint QR decomposition and lattice reduction at a power consumption of 31.2 mW. The energy efficiency achieves 0.18nJ/matrix for the 8×8 MIMO preprocessing including both QR decomposition and lattice reduction.
{"title":"A 0.18nJ/Matrix QR decomposition and lattice reduction processor for 8×8 MIMO preprocessing","authors":"Chun-Fu Liao, Jhong-Yu Wang, Yuan-Hao Huang","doi":"10.1109/ASSCC.2013.6691007","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691007","url":null,"abstract":"This study presents a joint QR decomposition and lattice reduction processor for 8×8 multiple-input multiple-output (MIMO) systems. The proposed algorithm enhances the BER performance by lattice reduction and reduces the hardware cost by sharing computation units and removing redundant operations. This processor can be reconfigured as three different modes, including joint QR decomposition and lattice reduction, lattice reduction, and QR decomposition. The proposed processor was implemented in TSMC 90nm 1P9M CMOS technology. The maximum throughput is 1.1 M matrix/s for QR decomposition, and 0.5 M matrix/s for the lattice reduction, and 0.33 M matrix/s for the joint QR decomposition and lattice reduction at a power consumption of 31.2 mW. The energy efficiency achieves 0.18nJ/matrix for the 8×8 MIMO preprocessing including both QR decomposition and lattice reduction.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691038
R. Yousry, Ming-Shuan Chen, Mau-Chung Frank Chang, C. Yang
This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm2.
{"title":"An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving","authors":"R. Yousry, Ming-Shuan Chen, Mau-Chung Frank Chang, C. Yang","doi":"10.1109/ASSCC.2013.6691038","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691038","url":null,"abstract":"This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115992091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690970
R. Nair
Advanced mobile applications are the predominant driver for semiconductor technology innovations both at the leading edge and at the mature nodes. The short life-cycles of mobile products and the need for SoC level differentiation imposes significant challenges on technology architecture and time-to-volume. We foresee a move towards much closer collaboration, in fact a virtual IDM-like model, on both technical and business levels. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, extreme ultraviolet (EUV) lithography, collaboration - early, often and deep - is really the only practical approach given the cost and complexities involved. Early eco-system enablement with accurate models and silicon proven IP ensures first pass design success, which is an important step for faster Time-to-volume (TTV). We refer to this close collaborative model as Foundry 2.0.
{"title":"Collaborative innovation for future mobile applications","authors":"R. Nair","doi":"10.1109/ASSCC.2013.6690970","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690970","url":null,"abstract":"Advanced mobile applications are the predominant driver for semiconductor technology innovations both at the leading edge and at the mature nodes. The short life-cycles of mobile products and the need for SoC level differentiation imposes significant challenges on technology architecture and time-to-volume. We foresee a move towards much closer collaboration, in fact a virtual IDM-like model, on both technical and business levels. With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, extreme ultraviolet (EUV) lithography, collaboration - early, often and deep - is really the only practical approach given the cost and complexities involved. Early eco-system enablement with accurate models and silicon proven IP ensures first pass design success, which is an important step for faster Time-to-volume (TTV). We refer to this close collaborative model as Foundry 2.0.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114358289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691044
B. Devlin, M. Ikeda, Hiroshi Ueki, Kazuhiko Fukushima
We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the performance of the self-synchronous, gate-level pipelined architectures. Both implementations employ identical data-paths and take 804k transistors, with only difference in controller, and two interleaved 1024b cryptographic operations take from 6.1ms to 3.1ms for HTL and 6.0ms for MPL, at nominal power supply of 1.1V.
{"title":"Completely self-synchronous 1024-bit RSA crypt-engine in 40nm CMOS","authors":"B. Devlin, M. Ikeda, Hiroshi Ueki, Kazuhiko Fukushima","doi":"10.1109/ASSCC.2013.6691044","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691044","url":null,"abstract":"We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the performance of the self-synchronous, gate-level pipelined architectures. Both implementations employ identical data-paths and take 804k transistors, with only difference in controller, and two interleaved 1024b cryptographic operations take from 6.1ms to 3.1ms for HTL and 6.0ms for MPL, at nominal power supply of 1.1V.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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