Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690967
M. Je, T. Liow, H. Chang, S. Bhattacharya, D. Kwong
Mobile society is opening the way to “Always-On” future where we are constantly connected to everything we care about, which allows us to do “Anything”, “Anytime”, from “Anywhere”. This future mobile society will come true only when major technology advances are successfully made to overcome challenges in mobile devices, connectivity, and cloud computing infrastructure. While incessant technology push dictated by Moore's Law is certainly relevant, there are still so much more to innovate, to address all these challenges. In this paper, recent advances and opportunities of More-than-Moore technologies are presented as key enablers for the realization of future mobile society.
{"title":"Future mobile society beyond Moore's Law","authors":"M. Je, T. Liow, H. Chang, S. Bhattacharya, D. Kwong","doi":"10.1109/ASSCC.2013.6690967","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690967","url":null,"abstract":"Mobile society is opening the way to “Always-On” future where we are constantly connected to everything we care about, which allows us to do “Anything”, “Anytime”, from “Anywhere”. This future mobile society will come true only when major technology advances are successfully made to overcome challenges in mobile devices, connectivity, and cloud computing infrastructure. While incessant technology push dictated by Moore's Law is certainly relevant, there are still so much more to innovate, to address all these challenges. In this paper, recent advances and opportunities of More-than-Moore technologies are presented as key enablers for the realization of future mobile society.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113978081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691034
Xuan-Dien Do, Huy-Hieu Nguyen, Seok-Kyun Han, Sang-Gug Lee
In this paper, a rectifier with series Synchronized Switch Harvesting Inductor (Series SSHI) is proposed for piezoelectric (PE) energy harvesting system. The serial inductor helps to flip the voltage across the internal capacitor of the PE transducer instead of wasting the capacitor voltage by discharge. Active diodes are used for the switches to further improve the extraction efficiency. From measurements, the proposed rectifier shows a power extraction efficiency of 3.3 times that of the active full bridge (FB) rectifier, and more than 90% of the power conversion efficiency.
{"title":"A rectifier for piezoelectric energy harvesting system with series Synchronized Switch Harvesting Inductor","authors":"Xuan-Dien Do, Huy-Hieu Nguyen, Seok-Kyun Han, Sang-Gug Lee","doi":"10.1109/ASSCC.2013.6691034","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691034","url":null,"abstract":"In this paper, a rectifier with series Synchronized Switch Harvesting Inductor (Series SSHI) is proposed for piezoelectric (PE) energy harvesting system. The serial inductor helps to flip the voltage across the internal capacitor of the PE transducer instead of wasting the capacitor voltage by discharge. Active diodes are used for the switches to further improve the extraction efficiency. From measurements, the proposed rectifier shows a power extraction efficiency of 3.3 times that of the active full bridge (FB) rectifier, and more than 90% of the power conversion efficiency.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124349385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691010
J. Pathrose, L. Zou, K. Chai, M. Je, Y. Xu
This paper presents a smart temperature sensor operating over a wide temperature range from 25°C-225°C. The proposed smart temperature sensor eliminates the explicit bandgap reference and only requires the ratio of two diode voltages to obtain ratiometric temperature measurements. The temperature sensor is implemented with a simple time-domain architecture, resulting in low power consumption and small chip area. Fabricated in a PDSOI CMOS process, the proposed smart temperature sensor achieves an accuracy of 2°C over 25°C-225°C and consumes only 25-μA current under a 4.5-V supply with a chip area of 0.45mm2.
{"title":"A time-domain smart temperature sensor without an explicit bandgap reference in SOI CMOS operating up to 225°C","authors":"J. Pathrose, L. Zou, K. Chai, M. Je, Y. Xu","doi":"10.1109/ASSCC.2013.6691010","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691010","url":null,"abstract":"This paper presents a smart temperature sensor operating over a wide temperature range from 25°C-225°C. The proposed smart temperature sensor eliminates the explicit bandgap reference and only requires the ratio of two diode voltages to obtain ratiometric temperature measurements. The temperature sensor is implemented with a simple time-domain architecture, resulting in low power consumption and small chip area. Fabricated in a PDSOI CMOS process, the proposed smart temperature sensor achieves an accuracy of 2°C over 25°C-225°C and consumes only 25-μA current under a 4.5-V supply with a chip area of 0.45mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691055
Hiroaki Katsurai, M. Nogawa, Y. Ohtomo, J. Terada, H. Koizumi
A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize a continuous-mode CDR (C-CDR) after a B-CDR with converting the burst signal to the quasi-continuous signal by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs a fully digital, 6-bit automatic frequency calibrator for compensating the process variation. It calibrates the oscillation frequency of the VCO in the B-CDR from 10.3 GHz ± 2 GHz to 10.3 GHz ± 60 MHz. The B-CDR, integrated with the C-CDR, achieves output-data-jitter reduction of 17.3 dB at jitter frequency of 300 MHz and lock time of 220 ns, complying with the 10G-EPON standard.
{"title":"10.3-Gb/s burst-mode CDR with idle insertion and digital calibration in 40-nm CMOS for 10G-EPON systems","authors":"Hiroaki Katsurai, M. Nogawa, Y. Ohtomo, J. Terada, H. Koizumi","doi":"10.1109/ASSCC.2013.6691055","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691055","url":null,"abstract":"A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize a continuous-mode CDR (C-CDR) after a B-CDR with converting the burst signal to the quasi-continuous signal by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs a fully digital, 6-bit automatic frequency calibrator for compensating the process variation. It calibrates the oscillation frequency of the VCO in the B-CDR from 10.3 GHz ± 2 GHz to 10.3 GHz ± 60 MHz. The B-CDR, integrated with the C-CDR, achieves output-data-jitter reduction of 17.3 dB at jitter frequency of 300 MHz and lock time of 220 ns, complying with the 10G-EPON standard.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128198882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690968
T. Hirayama
Previous video cameras were big and heavy. However, CCD image sensors (CCD-ISs) replaced video camera tubes, so that video cameras became smaller and lighter, and video cameras as consumer products were introduced. Moreover, CCD-ISs created a market for digital still cameras and they replaced film cameras because of they were easy to use. However, CMOS image sensors (CISs) were incorporated into cellular phones that did not require high image resolution. CCD-ISs were then used for digital still cameras; however, their market share drastically declined with the appearance of back illuminated CMOS image sensors (BI-CISs) that had a better signal to noise ratio than CCD-ISs. LOGIC chip stacked BI-CISs were launched after that, which could improve the characteristics of cameras, increase their functions, and enable them to be miniaturized. This paper describes the evolution of CISs and their applications utilizing image quality, 3D integration, and wavelength.
{"title":"The evolution of CMOS image sensors","authors":"T. Hirayama","doi":"10.1109/ASSCC.2013.6690968","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690968","url":null,"abstract":"Previous video cameras were big and heavy. However, CCD image sensors (CCD-ISs) replaced video camera tubes, so that video cameras became smaller and lighter, and video cameras as consumer products were introduced. Moreover, CCD-ISs created a market for digital still cameras and they replaced film cameras because of they were easy to use. However, CMOS image sensors (CISs) were incorporated into cellular phones that did not require high image resolution. CCD-ISs were then used for digital still cameras; however, their market share drastically declined with the appearance of back illuminated CMOS image sensors (BI-CISs) that had a better signal to noise ratio than CCD-ISs. LOGIC chip stacked BI-CISs were launched after that, which could improve the characteristics of cameras, increase their functions, and enable them to be miniaturized. This paper describes the evolution of CISs and their applications utilizing image quality, 3D integration, and wavelength.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115924299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691059
Xicheng Jiang, Jungwoo Song, D. Cheung, Minsheng Wang, S. Arunachalam
An integrated ultralow EMI Class-D amplifier with a feed-forward ADC and feedback filters is demonstrated in a 180 nm CMOS and wire-bonded package. Circuit and architecture techniques, which enables 1.75W into an 8 Ohm speaker, 105 dB dynamic range, 95% efficiency, 0.004% THD+N, and 15.4 dB margin beyond the EN55022 Class B standard, are discussed.
{"title":"An 8Ω, 1.75W, 95% efficiency, 0.004% THD+N Class-D amplifier with a feed-forward ADC and feedback filters","authors":"Xicheng Jiang, Jungwoo Song, D. Cheung, Minsheng Wang, S. Arunachalam","doi":"10.1109/ASSCC.2013.6691059","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691059","url":null,"abstract":"An integrated ultralow EMI Class-D amplifier with a feed-forward ADC and feedback filters is demonstrated in a 180 nm CMOS and wire-bonded package. Circuit and architecture techniques, which enables 1.75W into an 8 Ohm speaker, 105 dB dynamic range, 95% efficiency, 0.004% THD+N, and 15.4 dB margin beyond the EN55022 Class B standard, are discussed.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691080
Lianhong Zhou, L. Yao, C. Heng, Muthukumaraswamy Annamalai, M. Je, W. K. Han, Lakshmi Sutha Kumar, Y. Guan
An acoustic transmitter employing crystal-less temperature-independent frequency reference and differential modulation has been realized in 1um SOI CMOS process. A temperature-independent switched capacitor based FVC is incorporated within an FLL to provide a stable frequency reference, which in turns generates the acoustic carriers. Differential modulation is proposed to allow drilling noise power cancellation at the receiver end. The FLL generates 3.3MHz output with an inaccuracy less than 2.85% over temperature range of 25 to 300 degree Celsius using digital trimming. Consuming 11mW under 5V supply, the transmitter achieves a data rate of 80bps while occupying an area of 25mm2.
在1um SOI CMOS工艺中实现了一种无晶温无关频率基准和差分调制的声发射机。基于温度无关开关电容的FVC被集成到FLL中，以提供稳定的频率参考，从而产生声载波。差分调制的目的是为了在接收端消除钻井噪声功率。使用数字微调，FLL产生3.3MHz输出，在25至300摄氏度的温度范围内误差小于2.85%。在5V电源下消耗11mW，发射器在占地25mm2的情况下实现80bps的数据速率。
{"title":"25 to 300 Degree celsius 80bps acoustic transmitter based on crystal-less temperature-independent frequency reference with differential modulation for drilling noise power cancellation","authors":"Lianhong Zhou, L. Yao, C. Heng, Muthukumaraswamy Annamalai, M. Je, W. K. Han, Lakshmi Sutha Kumar, Y. Guan","doi":"10.1109/ASSCC.2013.6691080","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691080","url":null,"abstract":"An acoustic transmitter employing crystal-less temperature-independent frequency reference and differential modulation has been realized in 1um SOI CMOS process. A temperature-independent switched capacitor based FVC is incorporated within an FLL to provide a stable frequency reference, which in turns generates the acoustic carriers. Differential modulation is proposed to allow drilling noise power cancellation at the receiver end. The FLL generates 3.3MHz output with an inaccuracy less than 2.85% over temperature range of 25 to 300 degree Celsius using digital trimming. Consuming 11mW under 5V supply, the transmitter achieves a data rate of 80bps while occupying an area of 25mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131817356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691077
Bo Zhao, Yinan Sun, Wei Zou, Y. Lian, Yongpan Liu, Huazhong Yang
This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.
{"title":"An energy efficient fully integrated OOK transceiver SoC for wireless body area networks","authors":"Bo Zhao, Yinan Sun, Wei Zou, Y. Lian, Yongpan Liu, Huazhong Yang","doi":"10.1109/ASSCC.2013.6691077","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691077","url":null,"abstract":"This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127583414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691031
Xin-Hong Qian, Ming-Seng Cheng, Chung-Yu Wu
A near-field 13.56-MHz 20mA inductive energy transmission device with ferrite core spiral coils and CMOS power regulator is designed and tested. The power regulator is composed of active voltage doubler (VD) rectifier and low-dropout regulators (LDOs). In order to avoid large space requirement of coil and further increase its efficiency in the implantable medical devices (IMDs), the coils are constructed in the spiral shape with a ferrite core. In the VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control is implemented to prevent from reverse current conduction and increase the efficiency. Three fully-integrated LDOs with rectifier output voltage of 2V to 1.8V are realized: LDO for analog circuits (ALDO), LDO for digital circuits (DLDO) and LDO for reference-voltage circuits (RLDO). Thus the performance of individual LDO can be optimized. Both ALDO and RLDO have low crosstalk noise from DLDO. The measured ripple voltage of rectifier output is 10.4mV. The power conversion efficiency (PCE) of 85% with 20mA output current. The measured dropout voltage is 384mV. As compared with other designs, the proposed Inductive link power supply has lower ripple voltages and dropout voltage, and higher PCE.
{"title":"A CMOS 13.56-MHz high-efficiency low-dropout-voltage 40-mW inductive link power supply utilizing on-chip delay-compensated voltage doubler rectifier and multiple LDOs for implantable medical devices","authors":"Xin-Hong Qian, Ming-Seng Cheng, Chung-Yu Wu","doi":"10.1109/ASSCC.2013.6691031","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691031","url":null,"abstract":"A near-field 13.56-MHz 20mA inductive energy transmission device with ferrite core spiral coils and CMOS power regulator is designed and tested. The power regulator is composed of active voltage doubler (VD) rectifier and low-dropout regulators (LDOs). In order to avoid large space requirement of coil and further increase its efficiency in the implantable medical devices (IMDs), the coils are constructed in the spiral shape with a ferrite core. In the VD with the comparator, the input offset voltage is adjustable for delay compensation and a start-up control circuit is added to achieve robust start-up mechanism. On-chip delay compensation control is implemented to prevent from reverse current conduction and increase the efficiency. Three fully-integrated LDOs with rectifier output voltage of 2V to 1.8V are realized: LDO for analog circuits (ALDO), LDO for digital circuits (DLDO) and LDO for reference-voltage circuits (RLDO). Thus the performance of individual LDO can be optimized. Both ALDO and RLDO have low crosstalk noise from DLDO. The measured ripple voltage of rectifier output is 10.4mV. The power conversion efficiency (PCE) of 85% with 20mA output current. The measured dropout voltage is 384mV. As compared with other designs, the proposed Inductive link power supply has lower ripple voltages and dropout voltage, and higher PCE.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691047
Haikun Jia, B. Chi, Lixue Kuang, Zhihua Wang
A wide tuning range resonant-mode switchable voltage controlled oscillator (VCO) based on π-type LC network is proposed. By proper configuring the switched negative resistance, the VCO can oscillate at the even mode or odd mode of the π-type LC network, thus the frequency tuning range is greatly increased. The proposed VCO has been implemented in 65 nm CMOS, and achieves a measured tuning range of 39%, from 47.6 to 71.0 GHz. The VCO consumes 10.4mA current from 1.0V power supply, excluding the output buffers. The measured phase noise is -110.3dBc/Hz@47.6 GHz at 10MHz offset.
{"title":"A resonant-mode switchable VCO with 47.6–71.0 GHz tuning range based on π-type LC network","authors":"Haikun Jia, B. Chi, Lixue Kuang, Zhihua Wang","doi":"10.1109/ASSCC.2013.6691047","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691047","url":null,"abstract":"A wide tuning range resonant-mode switchable voltage controlled oscillator (VCO) based on π-type LC network is proposed. By proper configuring the switched negative resistance, the VCO can oscillate at the even mode or odd mode of the π-type LC network, thus the frequency tuning range is greatly increased. The proposed VCO has been implemented in 65 nm CMOS, and achieves a measured tuning range of 39%, from 47.6 to 71.0 GHz. The VCO consumes 10.4mA current from 1.0V power supply, excluding the output buffers. The measured phase noise is -110.3dBc/Hz@47.6 GHz at 10MHz offset.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128349330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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