Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691036
Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen
A 6-bit 1.25GS/s single-channel asynchronous SAR ADC skipping the comparator metastability is presented. A delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range and to accelerate the comparison speed. It compensates the dynamic offset by the redundancy. This ADC in 40nm CMOS technology achieves 37.1dB peak SNDR and consumes 5.3mW at 1.2V supply. It results in an FoM of 73fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.004mm2.
{"title":"A 0.004mm2 single-channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS","authors":"Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen","doi":"10.1109/ASSCC.2013.6691036","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691036","url":null,"abstract":"A 6-bit 1.25GS/s single-channel asynchronous SAR ADC skipping the comparator metastability is presented. A delay-shift technique is proposed to shift the comparator delay to generate the 1.5-bit redundancy range and to accelerate the comparison speed. It compensates the dynamic offset by the redundancy. This ADC in 40nm CMOS technology achieves 37.1dB peak SNDR and consumes 5.3mW at 1.2V supply. It results in an FoM of 73fJ/conversion-step. Due to no extra calibration circuit, the core circuit only occupies an area of 0.004mm2.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129945702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691003
Deepu John
This paper presents a low power ECG recording Sys-tem-on-Chip (SoC) with on-chip low complexity lossless ECG compression for data reduction in wireless/ambulatory ECG sensor devices. The proposed algorithm uses a linear slope predictor to estimate the ECG samples, and uses a novel low complexity dynamic coding-packaging scheme to frame the resulting estimation error into fixed-length 16-bit format. The proposed technique achieves an average compression ratio of 2.25× on MIT/BIH ECG database. Implemented in 0.35 μm process, the compressor uses 0.565 K gates/channel occupying 0.4 mm2 for 4-channel, and consumes 535 nW/channel at 2.4V for ECG sampled at 512 Hz. Small size and ultra-low power consumption makes the proposed technique suitable for wearable ECG sensor application.
{"title":"An ECG-SoC with 535nW/channel lossless data compression for wearable sensors","authors":"Deepu John","doi":"10.1109/ASSCC.2013.6691003","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691003","url":null,"abstract":"This paper presents a low power ECG recording Sys-tem-on-Chip (SoC) with on-chip low complexity lossless ECG compression for data reduction in wireless/ambulatory ECG sensor devices. The proposed algorithm uses a linear slope predictor to estimate the ECG samples, and uses a novel low complexity dynamic coding-packaging scheme to frame the resulting estimation error into fixed-length 16-bit format. The proposed technique achieves an average compression ratio of 2.25× on MIT/BIH ECG database. Implemented in 0.35 μm process, the compressor uses 0.565 K gates/channel occupying 0.4 mm2 for 4-channel, and consumes 535 nW/channel at 2.4V for ECG sampled at 512 Hz. Small size and ultra-low power consumption makes the proposed technique suitable for wearable ECG sensor application.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115953763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691027
Yen-Chen Liu, Meng-Fan Chang, Yu-Fan Lin, Jui-Jen Wu, Che-Ju Yeh, S. Shen, Ping-Cheng Chen, W. Tsai, Y. Chih, S. Natarajan
High-performance mobile chips and MCUs require large-capacity and fast-read embedded nonvolatile/Flash memory (eNVM/eFlash) for code and data storage. Current-mode sense amplifiers (CSA) are commonly used in eNVM due to their fast sensing against large bitline (BL) load and small cell read currents. However, conventional CSAs cannot achieve fast random read access time (TAC) due to significant summed read-path input offsets (IOS-SUM). This work proposes an asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without run-time offset-cancellation operations. A 90nm AVB-CSA 1Mb Flash macro with BL-length test-modes was fabricated. The 512-rows AVB-CSA eFlash macro achieves 3.9ns TAC. The test-mode experiments confirmed that AVB-CSA improves 1.48x in TAC for 2048-rows BL-length. For the first time, a Mb eFlash with long BL achieves sub-4ns TAC.
{"title":"An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme","authors":"Yen-Chen Liu, Meng-Fan Chang, Yu-Fan Lin, Jui-Jen Wu, Che-Ju Yeh, S. Shen, Ping-Cheng Chen, W. Tsai, Y. Chih, S. Natarajan","doi":"10.1109/ASSCC.2013.6691027","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691027","url":null,"abstract":"High-performance mobile chips and MCUs require large-capacity and fast-read embedded nonvolatile/Flash memory (eNVM/eFlash) for code and data storage. Current-mode sense amplifiers (CSA) are commonly used in eNVM due to their fast sensing against large bitline (BL) load and small cell read currents. However, conventional CSAs cannot achieve fast random read access time (TAC) due to significant summed read-path input offsets (IOS-SUM). This work proposes an asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS-SUM and enable high-speed sensing without run-time offset-cancellation operations. A 90nm AVB-CSA 1Mb Flash macro with BL-length test-modes was fabricated. The 512-rows AVB-CSA eFlash macro achieves 3.9ns TAC. The test-mode experiments confirmed that AVB-CSA improves 1.48x in TAC for 2048-rows BL-length. For the first time, a Mb eFlash with long BL achieves sub-4ns TAC.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116631761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690977
Y. Nakase, Y. Ido, T. Oishi, T. Kumamoto, Toru Shimizu
An SIDO boost DC-DC converter operating with a wide input voltage range is proposed for sensor network applications. As the input voltage becomes lower, the inductor current is restricted by on-resistance of a driver transistor. Therefore, longer Ton period does not indicate a lager inductor current. In this condition, Ton period for the lowest input voltage operation is determined as the inductor current reaches 85% of its ideal value. The converter should operate in a continuous conduction mode (CCM) to obtain the maximum power from the input. Toff period is set by feed forward control from Ton period to sustain the output voltages. A test chip fabricated by a 190nm CMOS technology operates at the input voltage range from 80mV to 3V with maintaining the two output voltages of 3V and 5V, respectively. This means that the power of 625μW is substantially supplied from the input of 80mV for inner circuits.
{"title":"Wide input range from 80mV to 3V operation on-chip single-inductor dual-output (SIDO) DC-DC boost converter with self-adjusting clock duty for sensor network applications","authors":"Y. Nakase, Y. Ido, T. Oishi, T. Kumamoto, Toru Shimizu","doi":"10.1109/ASSCC.2013.6690977","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690977","url":null,"abstract":"An SIDO boost DC-DC converter operating with a wide input voltage range is proposed for sensor network applications. As the input voltage becomes lower, the inductor current is restricted by on-resistance of a driver transistor. Therefore, longer Ton period does not indicate a lager inductor current. In this condition, Ton period for the lowest input voltage operation is determined as the inductor current reaches 85% of its ideal value. The converter should operate in a continuous conduction mode (CCM) to obtain the maximum power from the input. Toff period is set by feed forward control from Ton period to sustain the output voltages. A test chip fabricated by a 190nm CMOS technology operates at the input voltage range from 80mV to 3V with maintaining the two output voltages of 3V and 5V, respectively. This means that the power of 625μW is substantially supplied from the input of 80mV for inner circuits.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116654504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691017
Xudong Jiang, Deyong Hu, Y. Tan, C. Leow, J. Chen, W. Shu, S. Wong, Osama Shanaa
A 76-108MHz FM Transmitter emits 120dBμVrms output signal using an embedded antenna on a PCB. A proposed on-chip calibration scheme digitally tunes an on-chip capacitor array to centre the embedded antenna resonance circuit with an external inductor at the desired FM channel. The transmitter achieves a 60dB audio SINAD, better than -45dB LO leakage and -50dB sideband suppression with -30/-55dB ACLR for 200kHz/400kHz offsets, respectively. The out of band spurious emission level for coexistence with other radio bands is very low and mostly around -102 dBm or less. A new on-chip T/R switch capable of handling 4Vpp signal is used to allow both FM TX and RX to share the same embedded antenna. The transmitter adds only 0.2mm^2 die area overhead to an FM TRX SoC in 65nm CMOS and draws 10mA from a 4.2V battery.
{"title":"A compact mobile FM Transmitter with automatic embedded antenna tuning and low spurious emission in 65nm CMOS","authors":"Xudong Jiang, Deyong Hu, Y. Tan, C. Leow, J. Chen, W. Shu, S. Wong, Osama Shanaa","doi":"10.1109/ASSCC.2013.6691017","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691017","url":null,"abstract":"A 76-108MHz FM Transmitter emits 120dBμVrms output signal using an embedded antenna on a PCB. A proposed on-chip calibration scheme digitally tunes an on-chip capacitor array to centre the embedded antenna resonance circuit with an external inductor at the desired FM channel. The transmitter achieves a 60dB audio SINAD, better than -45dB LO leakage and -50dB sideband suppression with -30/-55dB ACLR for 200kHz/400kHz offsets, respectively. The out of band spurious emission level for coexistence with other radio bands is very low and mostly around -102 dBm or less. A new on-chip T/R switch capable of handling 4Vpp signal is used to allow both FM TX and RX to share the same embedded antenna. The transmitter adds only 0.2mm^2 die area overhead to an FM TRX SoC in 65nm CMOS and draws 10mA from a 4.2V battery.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123753912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691006
Xubin Chen, Yun Chen, Yi Li, Yuebin Huang, Xiaoyang Zeng
This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.
{"title":"A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS","authors":"Xubin Chen, Yun Chen, Yi Li, Yuebin Huang, Xiaoyang Zeng","doi":"10.1109/ASSCC.2013.6691006","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691006","url":null,"abstract":"This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114260664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690986
Li Ding, Wen-Lan Wu, Sai-Weng Sin, U. Seng-Pan, R. Martins
This paper proposes acomprehensive background gain and mismatch error calibration technique for split ADC, without injecting any test signal. By employing a comparator threshold random selection method the input/output transfer characteristics of each split ADC channel is different. Based on Least Mean Square (LMS) adaptation the interstage gain error and capacitor mismatch error are corrected. All the estimations and corrections are performed in the digital domain, resulting in slight modifications of the analog circuit. The proposed calibration technique is applied on a 13-bit 60MS/s pipelined ADC. Fabricated in a 90nm CMOS process, the ADC achieves 70.8dB SNDR while consuming 63.8mW. The FoM is 377fJ/step at DC and 452 fJ/step at Nyquist.
{"title":"A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration","authors":"Li Ding, Wen-Lan Wu, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2013.6690986","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690986","url":null,"abstract":"This paper proposes acomprehensive background gain and mismatch error calibration technique for split ADC, without injecting any test signal. By employing a comparator threshold random selection method the input/output transfer characteristics of each split ADC channel is different. Based on Least Mean Square (LMS) adaptation the interstage gain error and capacitor mismatch error are corrected. All the estimations and corrections are performed in the digital domain, resulting in slight modifications of the analog circuit. The proposed calibration technique is applied on a 13-bit 60MS/s pipelined ADC. Fabricated in a 90nm CMOS process, the ADC achieves 70.8dB SNDR while consuming 63.8mW. The FoM is 377fJ/step at DC and 452 fJ/step at Nyquist.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133176659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691054
M. S. Jalali, Clifford Ting, Behrooz Abiri, A. Sheikholeslami, M. Kibune, H. Tamura
This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16" FR4 channel.
{"title":"A 3x blind ADC-based CDR","authors":"M. S. Jalali, Clifford Ting, Behrooz Abiri, A. Sheikholeslami, M. Kibune, H. Tamura","doi":"10.1109/ASSCC.2013.6691054","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691054","url":null,"abstract":"This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16\" FR4 channel.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134297635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6691032
Yuya Hasegawa, K. Tomita, Subaru Ishihara, Ryutaro Honma, H. Ishikuro
A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option.
{"title":"Single-inductor-dual-output wireless power receiver with synchronous pseudo-random-sequence PWM switched rectifiers","authors":"Yuya Hasegawa, K. Tomita, Subaru Ishihara, Ryutaro Honma, H. Ishikuro","doi":"10.1109/ASSCC.2013.6691032","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6691032","url":null,"abstract":"A single-inductor dual-output wireless power delivery receiver for small size battery-less applications is presented. The power delivery system uses two rectifiers connected to a receiving inductor switched by pseudo-random-sequence PWM (PRS-PWM) signal synchronized with induced AC voltage in the receiving inductor. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 %. The maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage (32V) LDMOS option.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"202 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132726427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-23DOI: 10.1109/ASSCC.2013.6690971
V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang
The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.
{"title":"A 28nm 3.6GHz 128 thread SPARC T5 processor and system applications","authors":"V. Krishnaswamy, Jinuk Luke Shin, Sebastian Turullols, J. Hart, G. Konstadinidis, Dawei Huang","doi":"10.1109/ASSCC.2013.6690971","DOIUrl":"https://doi.org/10.1109/ASSCC.2013.6690971","url":null,"abstract":"The SPARC T5 processor implements 16 8-threaded SPARC S3 cores, an 8-MB 16-way set-associative L3 cache, 8 BL8 DDR3-1066 schedulers, and integrated PCIe Gen-3. The processor doubles the performance of the previous generation SPARC T4 CPU and expands support for up to 8 socket systems in a single hop glueless fashion. It is implemented in the TSMC 28nm process using 1.5 billion transistors and a 13 layer metal stack. The chip has a maximum operating frequency of 3.6 GHz.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116914789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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