A reliable aluminium CVD technique for the filling of submicron contacts and vias providing good step coverage has been developed in a load-locked, batch-type, multichamber system. Because of the low resistivity of aluminium the subsequent metallization layer can be realized in the same process sequence. The Al CVD system configured consists of a reactor module, an I/O port, a bake-out annex activation module, a sputter deposition module, and an etch module, all grouped around an evacuated central wafer handling system which transfers wafers, on a single-wafer basis, in a vacuum of 2*10/sup -5/ Pa. The sputter deposition module provides the option to either deposit a sputtered diffusion barrier prior to the CVD film or to cap the CVD film with a Cu-doped sputtered Al layer to further enhance electromigration resistance. For a film thickness of 1 mu m, reflectivities of 55+or-5% are achieved at uniformities of +or-5%. Films exhibit resistivities of 2.8+or-0.2 mu Omega -cm and show good adhesion to most of the commonly used substrates. With a load of 30 wafers for each Al batch reactor, a throughput of 40 wafers per hour can be realized when two Al reactor modules are configured in one system.<>
{"title":"LPCVD of aluminium in a batch-type load-locked multi-chamber processing system","authors":"H.W. Piekaar, L. Kwakman, E. Granneman","doi":"10.1109/VMIC.1989.78014","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78014","url":null,"abstract":"A reliable aluminium CVD technique for the filling of submicron contacts and vias providing good step coverage has been developed in a load-locked, batch-type, multichamber system. Because of the low resistivity of aluminium the subsequent metallization layer can be realized in the same process sequence. The Al CVD system configured consists of a reactor module, an I/O port, a bake-out annex activation module, a sputter deposition module, and an etch module, all grouped around an evacuated central wafer handling system which transfers wafers, on a single-wafer basis, in a vacuum of 2*10/sup -5/ Pa. The sputter deposition module provides the option to either deposit a sputtered diffusion barrier prior to the CVD film or to cap the CVD film with a Cu-doped sputtered Al layer to further enhance electromigration resistance. For a film thickness of 1 mu m, reflectivities of 55+or-5% are achieved at uniformities of +or-5%. Films exhibit resistivities of 2.8+or-0.2 mu Omega -cm and show good adhesion to most of the commonly used substrates. With a load of 30 wafers for each Al batch reactor, a throughput of 40 wafers per hour can be realized when two Al reactor modules are configured in one system.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"28 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120924033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Shishino, T. Nishiwaki, A. Mitsui, S. Imanishi, M. Shiraishi
It was observed that the polycide interconnect formed on reflowed glass opened during heat treatment in VLSI fabrication. In failure analysis, crevices were observed. These crevices originated from cracks in the WSi/sub x/ film. In order to prevent these failures, correlations between the cracks in the WSi/sub x/ interconnect and the properties of the WSi/sub x/ film are examined in detail. Open failures in polycide interconnects are suppressed by decreasing the tensile stress of WSi/sub x/ films as well as by decreasing their fluorine concentration.<>
{"title":"Open circuit failures in CVD-WSi/sub x//poly-Si interconnects","authors":"M. Shishino, T. Nishiwaki, A. Mitsui, S. Imanishi, M. Shiraishi","doi":"10.1109/VMIC.1989.78036","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78036","url":null,"abstract":"It was observed that the polycide interconnect formed on reflowed glass opened during heat treatment in VLSI fabrication. In failure analysis, crevices were observed. These crevices originated from cracks in the WSi/sub x/ film. In order to prevent these failures, correlations between the cracks in the WSi/sub x/ interconnect and the properties of the WSi/sub x/ film are examined in detail. Open failures in polycide interconnects are suppressed by decreasing the tensile stress of WSi/sub x/ films as well as by decreasing their fluorine concentration.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115192727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pulsed-current-induced electromigration failure was studied under various repetition frequencies and current densities. Self-joule-heating of the conductors during stressing was monitored directly by detecting the infrared intensity emitted from the conductor. It was found that there is a critical pulse width for electromigration under pulsed stress conditions which depend on the peak current density and substrate temperature. This fact suggests that a continuous force is needed to cause Al ions to migrate. When a pulse width is sufficiently short, Al ions cannot move and settle in new unstable sites.<>
{"title":"A threshold pulse width for electromigration under pulsed stress conditions","authors":"T. Noguchi, K. Hatanaka, K. Maeguchi","doi":"10.1109/VMIC.1989.78021","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78021","url":null,"abstract":"Pulsed-current-induced electromigration failure was studied under various repetition frequencies and current densities. Self-joule-heating of the conductors during stressing was monitored directly by detecting the infrared intensity emitted from the conductor. It was found that there is a critical pulse width for electromigration under pulsed stress conditions which depend on the peak current density and substrate temperature. This fact suggests that a continuous force is needed to cause Al ions to migrate. When a pulse width is sufficiently short, Al ions cannot move and settle in new unstable sites.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. An aluminum-plug-formation technique achieved by excimer laser irradiation for planarized multilevel metallization is presented. The plug was formed by pyrolytic reactions using pulses from an XeCl excimer laser (150 mJ). The optical pulses are focused on an optical system to increase optical fluence. The optical system redefines and homogenizes the laser beam to a size of 2*2 mm/sup 2/ and is mounted on an X-Y stage which tracks the beam across the sample. A plug formed by four pulses is shown. During the irradiation, the sample was kept at room temperature, and the total of the amount of aluminum was controlled to just fill in each via hole. On the resulting surface insulator, aluminum is not found.<>
{"title":"Aluminum plug formation by excimer laser irradiation for planarized multilevel metallization","authors":"R. Mukai, K. Kobayashi, M. Nakano","doi":"10.1109/VMIC.1989.78049","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78049","url":null,"abstract":"Summary form only given. An aluminum-plug-formation technique achieved by excimer laser irradiation for planarized multilevel metallization is presented. The plug was formed by pyrolytic reactions using pulses from an XeCl excimer laser (150 mJ). The optical pulses are focused on an optical system to increase optical fluence. The optical system redefines and homogenizes the laser beam to a size of 2*2 mm/sup 2/ and is mounted on an X-Y stage which tracks the beam across the sample. A plug formed by four pulses is shown. During the irradiation, the sample was kept at room temperature, and the total of the amount of aluminum was controlled to just fill in each via hole. On the resulting surface insulator, aluminum is not found.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132479687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The effects of chlorine levels on corrosion for various metallization schemes used in a double-metal submicron CMOS process are discussed. Wafers were etched in Applied Materials 8330 using BCl/sub 3//Cl/sub 2/ chemistry. X-ray fluorescence spectroscopy (XRF) was used to determine the chlorine (Cl) and fluorine (F) levels. The authors found that the dominating factor for corrosion, irrespective of the metallization scheme, is the absolute Cl level. The preferred passivation is an in situ F:Cl replacement since a polymer passivation results in higher Cl levels due to entrapment. While eater rinses and N/sub 2/ bakes help with reducing Cl levels, the effect is negligible compared to resist removal, as the majority of the Cl trapped is the resist. The effect of resist type and/or thickness on Cl levels need further investigation.<>
{"title":"Corrosion characteristics of metallization systems with XRF","authors":"N. Parekh, J. Price","doi":"10.1109/VMIC.1989.78059","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78059","url":null,"abstract":"Summary form only given. The effects of chlorine levels on corrosion for various metallization schemes used in a double-metal submicron CMOS process are discussed. Wafers were etched in Applied Materials 8330 using BCl/sub 3//Cl/sub 2/ chemistry. X-ray fluorescence spectroscopy (XRF) was used to determine the chlorine (Cl) and fluorine (F) levels. The authors found that the dominating factor for corrosion, irrespective of the metallization scheme, is the absolute Cl level. The preferred passivation is an in situ F:Cl replacement since a polymer passivation results in higher Cl levels due to entrapment. While eater rinses and N/sub 2/ bakes help with reducing Cl levels, the effect is negligible compared to resist removal, as the majority of the Cl trapped is the resist. The effect of resist type and/or thickness on Cl levels need further investigation.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kozicki, Y. Khawaja, A. Owen, P. Ewen, A. Zakery
The advantages of the use of metal-chalcogenide systems, and the As-S/Ag system in particular, in integrated optics such as optical interconnections are described. The As-S/Ag system has a number of desirable properties which make it attractive for applications in integrated optics, and these are discussed. It is shown that the metal photodissolution effect has an inherently high spatial resolution, well into the submicron range using optical lithography and on the scale of a few tens of nanometers or less with electron-beam exposure. This unusual combination of properties, their easy fabrication in thin- and thick-film form, and the ability to selectively etch either the undoped or doped material make the chalcogenide compounds uniquely appropriate to a variety of applications in integrated optics.<>
介绍了金属硫族化物系统，特别是as - s /Ag系统在集成光学(如光互连)中的优点。本文讨论了As-S/Ag系统在集成光学领域的应用。结果表明，金属光溶解效应具有固有的高空间分辨率，用光学光刻技术可以达到亚微米范围，电子束曝光可以达到几十纳米或更小的尺度。这种不寻常的性质组合，它们在薄膜和厚膜形式下的易于制造，以及选择性蚀刻未掺杂或掺杂材料的能力，使硫系化合物特别适合于集成光学中的各种应用。
{"title":"As-S/Ag systems for integrated optics","authors":"M. Kozicki, Y. Khawaja, A. Owen, P. Ewen, A. Zakery","doi":"10.1109/VMIC.1989.78028","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78028","url":null,"abstract":"The advantages of the use of metal-chalcogenide systems, and the As-S/Ag system in particular, in integrated optics such as optical interconnections are described. The As-S/Ag system has a number of desirable properties which make it attractive for applications in integrated optics, and these are discussed. It is shown that the metal photodissolution effect has an inherently high spatial resolution, well into the submicron range using optical lithography and on the scale of a few tens of nanometers or less with electron-beam exposure. This unusual combination of properties, their easy fabrication in thin- and thick-film form, and the ability to selectively etch either the undoped or doped material make the chalcogenide compounds uniquely appropriate to a variety of applications in integrated optics.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115400100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Abe, Y. Mase, T. Katsura, O. Hirata, T. Yamamoto, S. Koguchi
A novel multilevel interconnection system for bipolar or BiCMOS LSIs was developed. Bias sputtered quartz (BSQ) and plasma CVD SiO(P-SiO) constituted the stacked interlayer, making it possible to smooth high aspect ratio (0.82) topography. The electrical properties of the films and the manufacturing-process damage were investigated. The results show that the stacked structure offers good electrical stability and reliability. This system was successfully applied to real devices.<>
{"title":"High performance multilevel interconnection system with stacked interlayer dielectrics by plasma CVD and bias sputtering","authors":"M. Abe, Y. Mase, T. Katsura, O. Hirata, T. Yamamoto, S. Koguchi","doi":"10.1109/VMIC.1989.78001","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78001","url":null,"abstract":"A novel multilevel interconnection system for bipolar or BiCMOS LSIs was developed. Bias sputtered quartz (BSQ) and plasma CVD SiO(P-SiO) constituted the stacked interlayer, making it possible to smooth high aspect ratio (0.82) topography. The electrical properties of the films and the manufacturing-process damage were investigated. The results show that the stacked structure offers good electrical stability and reliability. This system was successfully applied to real devices.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130066766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of the deposition of dielectric silicon oxide from TEOS in helium/oxygen mixtures in a parallel-plate RF plasma reactor. Under appropriate process conditions, highly directional deposition of low-stress stoichiometric silicon oxide is achieved. The step coverage profiles and the chemical and physical properties of these SiO/sub 2/ films were studied to gain an understanding of the origin of preferentially vertical deposition. The typical deposition conditions used in this study were 1 torr total pressure, 320 degrees C substrate temperature, 1-40% TEOS, and 0-80% O/sub 2/ in low-power-density (0.1-0.4 W/cm/sup 2/) 14 MHz RF discharges. Step coverage, chemical stability and film stress were found to be most dependent on the O/sub 2/:TEOS gas flow ratio. This dependence can be explained by the various effects involved in the oxide deposition mechanism.<>
{"title":"Directional deposition of dielectric silicon oxide by plasma enhanced TEOS process","authors":"J. Hsieh, D.E. Ibbotson, J. Mucha, D. Flamm","doi":"10.1109/VMIC.1989.78002","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78002","url":null,"abstract":"A description is given of the deposition of dielectric silicon oxide from TEOS in helium/oxygen mixtures in a parallel-plate RF plasma reactor. Under appropriate process conditions, highly directional deposition of low-stress stoichiometric silicon oxide is achieved. The step coverage profiles and the chemical and physical properties of these SiO/sub 2/ films were studied to gain an understanding of the origin of preferentially vertical deposition. The typical deposition conditions used in this study were 1 torr total pressure, 320 degrees C substrate temperature, 1-40% TEOS, and 0-80% O/sub 2/ in low-power-density (0.1-0.4 W/cm/sup 2/) 14 MHz RF discharges. Step coverage, chemical stability and film stress were found to be most dependent on the O/sub 2/:TEOS gas flow ratio. This dependence can be explained by the various effects involved in the oxide deposition mechanism.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125387487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel integrated in situ approach to deposition and planarization of dielectrics is presented. The process uses a multichamber deposition and etch system. A sacrificial layer of boron oxide is deposited by plasma-enhanced deposition over the dielectric material. Boron oxide is observed to flow as deposited, resulting in a planarized surface. After deposition the wafer is transferred under vacuum to the etch chamber where the boron oxide is removed with a 1:1 dielectric-to-boron-oxide etch. This results in a planarized dielectric surface. Effective planarization of 25- mu -wide spacings can be achieved using this process.<>
{"title":"In situ planarization of dielectric surfaces using boron oxide","authors":"J. Marks, K. Law, D. Wang","doi":"10.1109/VMIC.1989.78010","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78010","url":null,"abstract":"A novel integrated in situ approach to deposition and planarization of dielectrics is presented. The process uses a multichamber deposition and etch system. A sacrificial layer of boron oxide is deposited by plasma-enhanced deposition over the dielectric material. Boron oxide is observed to flow as deposited, resulting in a planarized surface. After deposition the wafer is transferred under vacuum to the etch chamber where the boron oxide is removed with a 1:1 dielectric-to-boron-oxide etch. This results in a planarized dielectric surface. Effective planarization of 25- mu -wide spacings can be achieved using this process.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132878980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Fujii, K. Okuyama, S. Moribe, Y. Torii, H. Katto, T. Agatsuma
The electromigration characteristics of a multilayered system were found to be divided into three stages. The mechanism leading to the stages is discussed in terms of the process of microvoid growth during the electromigration stressing and is correlated with the amount of Si precipitation and the size of the grain boundary of Al films, the reaction layer at the interface, and the resistivity of the barrier metal. The experiments were carried out for MoSi, TiN, and TiW film deposited on oxidized Si
{"title":"Comparison of electromigration phenomenon between aluminum interconnection of various multilayered materials","authors":"T. Fujii, K. Okuyama, S. Moribe, Y. Torii, H. Katto, T. Agatsuma","doi":"10.1109/VMIC.1989.78040","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78040","url":null,"abstract":"The electromigration characteristics of a multilayered system were found to be divided into three stages. The mechanism leading to the stages is discussed in terms of the process of microvoid growth during the electromigration stressing and is correlated with the amount of Si precipitation and the size of the grain boundary of Al films, the reaction layer at the interface, and the resistivity of the barrier metal. The experiments were carried out for MoSi, TiN, and TiW film deposited on oxidized Si","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131066079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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