Summary form only given. Gate oxide integrity and n-MOSFET reliability are investigated for the MOS tungsten polycide gate structure. Experimental data show that the degradation is caused by the mechanical stress in polycide film. The mechanical stress generates the traps about 50-AA depth from the gate electrode in the gate oxide. Degradation of polycide gate n-MOSFETs due to hot carriers is accelerated by the existence of these traps in the gate oxide.<>
{"title":"Oxide reliability in tungsten polycide gate electrode","authors":"I. Kurachi, T. Yanai, K. Yoshioka","doi":"10.1109/VMIC.1989.78058","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78058","url":null,"abstract":"Summary form only given. Gate oxide integrity and n-MOSFET reliability are investigated for the MOS tungsten polycide gate structure. Experimental data show that the degradation is caused by the mechanical stress in polycide film. The mechanical stress generates the traps about 50-AA depth from the gate electrode in the gate oxide. Degradation of polycide gate n-MOSFETs due to hot carriers is accelerated by the existence of these traps in the gate oxide.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Manos, F. Pintchovski, J. Klein, E. Travis, B. Boeck, M. Woo, C. Chen, S. Koenigseder, R. Dillard
A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<>
{"title":"A submicron triple-level-metal gate array process utilizing tungsten for 1st level interconnect","authors":"P. Manos, F. Pintchovski, J. Klein, E. Travis, B. Boeck, M. Woo, C. Chen, S. Koenigseder, R. Dillard","doi":"10.1109/VMIC.1989.78074","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78074","url":null,"abstract":"A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An anomalous p/sup +/ contact resistance increase observed under a certain process condition was investigated. It was found the oxidation process condition after ion-implantation for the diffusion layer strongly affects the p/sup +/ contact resistance in the Al-Si-Cu/TiN/Ti barrier metal system. From the analysis of this phenomenon, an improved contact hole process is proposed that simultaneously realizes a self-aligned contact structure to overcome this failure. Megabit EPROMs, utilizing the TiN/Ti system, were fabricated to investigate the interconnection reliability.<>
{"title":"Reliable contact metallization technology with Al-Si-Cu/TiN/Ti system for CMOS VLSIs","authors":"Y. Ohshima, S. Mori, K. Yoshikawa","doi":"10.1109/VMIC.1989.78012","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78012","url":null,"abstract":"An anomalous p/sup +/ contact resistance increase observed under a certain process condition was investigated. It was found the oxidation process condition after ion-implantation for the diffusion layer strongly affects the p/sup +/ contact resistance in the Al-Si-Cu/TiN/Ti barrier metal system. From the analysis of this phenomenon, an improved contact hole process is proposed that simultaneously realizes a self-aligned contact structure to overcome this failure. Megabit EPROMs, utilizing the TiN/Ti system, were fabricated to investigate the interconnection reliability.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121110570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technique is described whereby implantation of silicon through a mask into the intermetal insulator modifies the insulation. After deposition and definition of the upper metal, the implanted regions between metal levels act as voltage programmable links. Application of a voltage between upper and lower metal electrodes causes the implanted insulation to become conductive, producing a low-resistance, planar, vertical connection. Alternatively, these implanted areas can be rendered conducting by exposure to a focused laser beam.<>
{"title":"Multilevel interconnect planarization by voltage and laser programmable links using ion implantation","authors":"T. Herndon, J. Burns, G. H. Chapman, J. Raffel","doi":"10.1109/VMIC.1989.77991","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77991","url":null,"abstract":"A technique is described whereby implantation of silicon through a mask into the intermetal insulator modifies the insulation. After deposition and definition of the upper metal, the implanted regions between metal levels act as voltage programmable links. Application of a voltage between upper and lower metal electrodes causes the implanted insulation to become conductive, producing a low-resistance, planar, vertical connection. Alternatively, these implanted areas can be rendered conducting by exposure to a focused laser beam.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122742119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Klein, F. Pintchovski, W. Paulson, D. Fisher, M. Swenson, Y. See
Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<>
{"title":"Characteristics of a poly-silicon contact plug technology","authors":"J. Klein, F. Pintchovski, W. Paulson, D. Fisher, M. Swenson, Y. See","doi":"10.1109/VMIC.1989.78048","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78048","url":null,"abstract":"Summary form only given. Polysilicon plug technology takes advantage of the desirable properties of LPCVD polysilicon (i.e. conformal step coverage, smooth texture, good etchability) to planarize submicron contacts. In addition, sputtered and CVD barrier metal layers are utilized to ensure good ohmic contact and maintain a low-resistance plug. It is shown that the polysilicon plugs completely fill the contact holes and provide a nearly planar surface for the sputtered aluminum. In addition, the RIS+CVD TiN barrier is highly conformal for all observed contact sizes. The specific contact resistance to n/sup +/ and p/sup +/ doped silicon was found to be less than 5*100/sup -7/ Omega -cm/sup 2/. To titanium silicide, the contact resistance dropped to below 2*10/sup -8/ Omega -cm/sup 2/. The composite resistivity of the polysilicon plug plus CVD and RIS TiN barrier was less than 5*100/sup -4/ Omega -cm/sup 2/. Shallow junction, contact-intensive diode structures exhibited good breakdown voltages and leakage current below 5 nA/cm/sup 2/. These results demonstrate a reproducible contact plug technology suitable for advanced MLM CMOS circuits.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114352607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Mikagi, T. Homma, T. Katoh, K. Tsunenari, Y. Murao
Multilevel gold (Au) metallization was realized for high-speed VLSI devices by a novel combination of selective tungsten CVD (W-CVD) with electroplated Au and a polyimide siloxane (PSI) film developed by the authors. Selective W-CVD was applied to overcome the problem of poor adhesion between Au wiring and PSI film as well as to fill vias. Silane (SiH/sub 4/) reduced selective W-CVD application to Au wiring and an organic dielectric film (PSI) for VLSI devices have been demonstrated for the first time.<>
{"title":"Multilevel gold metallization by use of selective W-CVD and polyimide siloxane film","authors":"K. Mikagi, T. Homma, T. Katoh, K. Tsunenari, Y. Murao","doi":"10.1109/VMIC.1989.78073","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78073","url":null,"abstract":"Multilevel gold (Au) metallization was realized for high-speed VLSI devices by a novel combination of selective tungsten CVD (W-CVD) with electroplated Au and a polyimide siloxane (PSI) film developed by the authors. Selective W-CVD was applied to overcome the problem of poor adhesion between Au wiring and PSI film as well as to fill vias. Silane (SiH/sub 4/) reduced selective W-CVD application to Au wiring and an organic dielectric film (PSI) for VLSI devices have been demonstrated for the first time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Nishida, M. Saito, S. Iijima, T. Kure, E. Sasaki, K. Yagi
In order to integrate half-micron experimental CMOS and BiCMOS LSIs, multilevel interconnection process technology utilizing relatively conventional techniques has been developed. Some design rules are 0.8- mu m metal line and 0.6- mu m space for the first and the second level. To achieve these requirements, dielectric planarization techniques were adopted. Heavily doped BPSG glass flow was used to cover underlying poly steps, and spin-on-glass planarization was used at the metal steps. Tungsten (W) was selected for the first-level wiring. Although the step coverage of the sputtered W film at the reflow tapered 0.6- mu m contact hole was poor, high current capability was observed due to the high electromigration immunity of W. At via holes, step coverage was slightly improved using shallow voltage bias sputtering of Al. Al/TiN layered metallization was used for the second to fourth-level wirings to maintain stress migration immunity. At the third and fourth levels, design rules were widened because of the focus depth.<>
{"title":"Multilevel interconnection for half-micron ULSI's","authors":"T. Nishida, M. Saito, S. Iijima, T. Kure, E. Sasaki, K. Yagi","doi":"10.1109/VMIC.1989.78071","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78071","url":null,"abstract":"In order to integrate half-micron experimental CMOS and BiCMOS LSIs, multilevel interconnection process technology utilizing relatively conventional techniques has been developed. Some design rules are 0.8- mu m metal line and 0.6- mu m space for the first and the second level. To achieve these requirements, dielectric planarization techniques were adopted. Heavily doped BPSG glass flow was used to cover underlying poly steps, and spin-on-glass planarization was used at the metal steps. Tungsten (W) was selected for the first-level wiring. Although the step coverage of the sputtered W film at the reflow tapered 0.6- mu m contact hole was poor, high current capability was observed due to the high electromigration immunity of W. At via holes, step coverage was slightly improved using shallow voltage bias sputtering of Al. Al/TiN layered metallization was used for the second to fourth-level wirings to maintain stress migration immunity. At the third and fourth levels, design rules were widened because of the focus depth.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134593282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. W. Scheckler, D. E. Lyons, A. Neureuther, W. Oldham
An integrated computer-aided-design environment is presented which is suitable for interconnect process design. It displays device cross-sections and electrical performance parameters by linking information from layout, process flow, rigorous topography simulation, and electrical analysis. As a specific example, these CAD tools have been applied to a proposed planarization process to study the topographies resulting from different process parameters and layout mask designs. Exploratory electrical test structures have been developed to help demonstrate topography-induced increases in parasitic effects and to establish the validity of the simulation.<>
{"title":"Process simulation and experiment for RC-parasitics in multilevel metallization","authors":"E. W. Scheckler, D. E. Lyons, A. Neureuther, W. Oldham","doi":"10.1109/VMIC.1989.78034","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78034","url":null,"abstract":"An integrated computer-aided-design environment is presented which is suitable for interconnect process design. It displays device cross-sections and electrical performance parameters by linking information from layout, process flow, rigorous topography simulation, and electrical analysis. As a specific example, these CAD tools have been applied to a proposed planarization process to study the topographies resulting from different process parameters and layout mask designs. Exploratory electrical test structures have been developed to help demonstrate topography-induced increases in parasitic effects and to establish the validity of the simulation.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126643544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Saito, N. Takenaka, S. Ohnishi, A. Ayukawa, K. Miki, K. Sakiyama
Via contact resistance degradation was evaluated by high-resolution transmission electron microscopy. An amorphous layer approximately 2.5 nm in thickness was found between the two levels of aluminum at the via hole. Aluminum, fluorine, oxygen, and silicon were detected in this amorphous layer by using electron probe microanalysis. In evaluating the via hole process, by-products formed during reactive ion etching (RIE) were observed. Such treatments as oxygen plasma and an organic solvent soak did not remove these by-product layers, which were on the order of 20 approximately 50 nm thick on the sidewalls and about 10-nm thick on the aluminum surface at the bottom of the via hole. Electron energy loss spectroscopy showed that the by-products consisted of aluminum fluoride (AlF/sub 3/, AlF/sub 2/) and aluminum oxide (Al/sub 2/O/sub 3/). The addition of oxygen gas to trifluoromethane (CHF/sub 3/) gas in via hole etching has the effect of suppressing the formation of these by-products. RIE at a higher frequency of 13.56 MHz resulted in almost no by-products compared with etching at 380 kHz.<>
{"title":"A fine process control on the via hole of multilevel interconnection","authors":"S. Saito, N. Takenaka, S. Ohnishi, A. Ayukawa, K. Miki, K. Sakiyama","doi":"10.1109/VMIC.1989.78005","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78005","url":null,"abstract":"Via contact resistance degradation was evaluated by high-resolution transmission electron microscopy. An amorphous layer approximately 2.5 nm in thickness was found between the two levels of aluminum at the via hole. Aluminum, fluorine, oxygen, and silicon were detected in this amorphous layer by using electron probe microanalysis. In evaluating the via hole process, by-products formed during reactive ion etching (RIE) were observed. Such treatments as oxygen plasma and an organic solvent soak did not remove these by-product layers, which were on the order of 20 approximately 50 nm thick on the sidewalls and about 10-nm thick on the aluminum surface at the bottom of the via hole. Electron energy loss spectroscopy showed that the by-products consisted of aluminum fluoride (AlF/sub 3/, AlF/sub 2/) and aluminum oxide (Al/sub 2/O/sub 3/). The addition of oxygen gas to trifluoromethane (CHF/sub 3/) gas in via hole etching has the effect of suppressing the formation of these by-products. RIE at a higher frequency of 13.56 MHz resulted in almost no by-products compared with etching at 380 kHz.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126656333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A triple interconnection process suitable for a CMOS 1.2- mu m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P/sub 2/O/sub 5/ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively.<>
{"title":"A triple metal interconnection process for CMOS technology","authors":"P. Cagnoni, F. Gualandris, L. Masini","doi":"10.1109/VMIC.1989.78075","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78075","url":null,"abstract":"A triple interconnection process suitable for a CMOS 1.2- mu m technology device is described. As far as process technology is concerned, planarization was applied at contacts and via I and II levels. In order to avoid silicon grains in the contact and to improve contact resistance, the metallization scheme requires the use of a metallization barrier. The AlSi(1%)Cu(0.5%) alloy was used for the metal I, II, and III interconnection layers. In order to accomplish gettering and deal with stress issues, APCVD PSG 4-m/o P/sub 2/O/sub 5/ and PECVD oxynitride (refractive index 1.75) were used for the final passivation. The triple metal interconnection impact on contact and transistor performances was evaluated by the use of Kelvin measurements and the 10% variation of the normalized transconductance, respectively.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115792731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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