Summary form only given. This study shows that the oxides deposited using tetraethylorthosilicate (TEOS) have electrical characteristics comparable to those of thermally grown oxides, and that TEOS-grown oxides have a lower defect density than thermal oxides grown under similar particle generating conditions. The breakdown data of TEOS films deposited at various temperatures are equivalent to those of thermal oxides of the same thickness provided that films undergo a densification step. The median breakdown field at 9 MV/cm is close to that of 9.5 MV/cm for the thermally grown control samples. Time-dependent breakdown data show TEOS deposited oxides have an order of magnitude longer lifetime than thermally grown oxides, indicating that improved reliability can be expected using a TEOS oxide.<>
{"title":"Deposited oxides for high integrity applications","authors":"D. Freeman, J. R. Monowski, G. Ruggles","doi":"10.1109/VMIC.1989.78056","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78056","url":null,"abstract":"Summary form only given. This study shows that the oxides deposited using tetraethylorthosilicate (TEOS) have electrical characteristics comparable to those of thermally grown oxides, and that TEOS-grown oxides have a lower defect density than thermal oxides grown under similar particle generating conditions. The breakdown data of TEOS films deposited at various temperatures are equivalent to those of thermal oxides of the same thickness provided that films undergo a densification step. The median breakdown field at 9 MV/cm is close to that of 9.5 MV/cm for the thermally grown control samples. Time-dependent breakdown data show TEOS deposited oxides have an order of magnitude longer lifetime than thermally grown oxides, indicating that improved reliability can be expected using a TEOS oxide.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115418550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Drawing on advanced packaging and interconnection schemes along with advances in VLSI technologies, the authors consider some examples of novel interconnection technologies. Novel polymer waveguides requiring only exposure to deep UV to fabricate a waveguide are emphasized as a potentially important material compatible with overlaying complex VLSI circuitry. Superconducting microstrip interconnections are considered. These examples suggest that conventional VLSI silicon technologies will evolve to become the support for the selective introduction of advanced interconnection technologies, yielding within the smaller system volumes of wafer-level systems the heterogeneous mixture of technologies seen in, or being introduced into, conventional, complex systems. It is pointed out that the specific examples used are microfabricated structures on substrates appropriate for achieving narrow features.<>
{"title":"Advanced interconnection technologies and system-level communications functions","authors":"L. Hornak, S. Tewksbury, T. Weidman, E. W. Kwock","doi":"10.1109/VMIC.1989.78024","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78024","url":null,"abstract":"Drawing on advanced packaging and interconnection schemes along with advances in VLSI technologies, the authors consider some examples of novel interconnection technologies. Novel polymer waveguides requiring only exposure to deep UV to fabricate a waveguide are emphasized as a potentially important material compatible with overlaying complex VLSI circuitry. Superconducting microstrip interconnections are considered. These examples suggest that conventional VLSI silicon technologies will evolve to become the support for the selective introduction of advanced interconnection technologies, yielding within the smaller system volumes of wafer-level systems the heterogeneous mixture of technologies seen in, or being introduced into, conventional, complex systems. It is pointed out that the specific examples used are microfabricated structures on substrates appropriate for achieving narrow features.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114393500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electromigration life testing of multisegment test structures involves the measurement and analysis of space- and time-variant stress temperature distributions. A technique using the concept of a thermal coupling matrix was developed which allows an accurate (>
{"title":"Chip-level electromigration measurement technique for multi-segmented interconnect test structures","authors":"N. Zamani, J. Dhiman, M. Buehler","doi":"10.1109/VMIC.1989.78023","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78023","url":null,"abstract":"Electromigration life testing of multisegment test structures involves the measurement and analysis of space- and time-variant stress temperature distributions. A technique using the concept of a thermal coupling matrix was developed which allows an accurate (<or=0.5 degrees C) determination of each metal segment temperature during stress test. In the data analysis, each segment failure time is adjusted to the target stress temperature. This results in more accurate values for the calculated electromigration parameters.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"30 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Planar thin-film stacks comprising 750-nm Al-1%Cu/100-nm TiW/100-nm SiO/sub 2/ were subjected to a 25-ns excimer laser pulse (XeCl, 308 nm) at an optical fluence of 3.5 to 5.0 J/cm/sup 2/ at a substrate temperature of 250 degrees to 400 degrees C, and a number of the important film properties were measured. Resultant grain sizes ranged from 2 mu m to in excess of 300 mu m, the largest grains corresponding to the highest fluence/temperature condition. The melting of the Al-Cu films was found to eliminate hillock growth completely during subsequent furnace annealing (450 degrees C). Laser processing at the higher fluence condition (5.0 J/cm/sup 2/) produced large (>30%) increases in layer resistivity. Ultramicrohardness was found to range from 39 to 52 kg/mm/sup 2/ for the treated films. Accelerated stress testing revealed no significant difference in open-circuit electromigration resistance between the as-deposited and the majority of the laser-processed Al-Cu films. However, one particular group of laser-melted samples (3.5 J/cm/sup 2/, 400 degrees C) demonstrated lifetimes at least 10 times greater than those of the other sample groups. Specular reflectivity, impurity distribution, and layer morphology were also examined.<>
{"title":"Excimer laser processing of Al-1%Cu/TiW interconnect layers","authors":"E. Broadbent, K. Ritz, P. Maillot, E. Ong","doi":"10.1109/VMIC.1989.77993","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77993","url":null,"abstract":"Planar thin-film stacks comprising 750-nm Al-1%Cu/100-nm TiW/100-nm SiO/sub 2/ were subjected to a 25-ns excimer laser pulse (XeCl, 308 nm) at an optical fluence of 3.5 to 5.0 J/cm/sup 2/ at a substrate temperature of 250 degrees to 400 degrees C, and a number of the important film properties were measured. Resultant grain sizes ranged from 2 mu m to in excess of 300 mu m, the largest grains corresponding to the highest fluence/temperature condition. The melting of the Al-Cu films was found to eliminate hillock growth completely during subsequent furnace annealing (450 degrees C). Laser processing at the higher fluence condition (5.0 J/cm/sup 2/) produced large (>30%) increases in layer resistivity. Ultramicrohardness was found to range from 39 to 52 kg/mm/sup 2/ for the treated films. Accelerated stress testing revealed no significant difference in open-circuit electromigration resistance between the as-deposited and the majority of the laser-processed Al-Cu films. However, one particular group of laser-melted samples (3.5 J/cm/sup 2/, 400 degrees C) demonstrated lifetimes at least 10 times greater than those of the other sample groups. Specular reflectivity, impurity distribution, and layer morphology were also examined.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125765390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The evaporation of Al onto a heated TiW- or TiN-coated substrate is used to planarize topography. The final temperature of 450 degrees C provides enough Al mobility to planarize 2- mu m-wide features. The deposition of 1.5-2.0 times the feature depth with a >250/450 degrees C two-temperature process and a deposition rate approximately=100 AA/s gives good planarization uniformity over >6-cm wafer radius. Submicron trenches are planarized without voids, whereas windows with h/w>1 have voids. Also, 1- mu m-deep trenches are filled, whereas 2- mu m-deep trenches are not filled with a similar process. Scanning electron microscopy correlates planarization and via filling with the evaporation process and substrate topography. The effect of high-temperature evaporation on materials integrity is studied with diode leakage measurements. At 450 degrees C for <2 min required for the second step, there is no Al/(TiW or TiN)/Si interaction. However, the process is close to the failure temperature of the 1000-AA-thick (less than or approximately equal to 500 AA thick in 1 mu m features) TiW barrier layer since Al spiking is seen when the final step is >or approximately=500 degrees C.<>
{"title":"Planarized aluminum deposition of TiW and TiN layers by high temperature evaporation","authors":"G. Georgiou, K. Cheung, R. Liu","doi":"10.1109/VMIC.1989.77990","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77990","url":null,"abstract":"The evaporation of Al onto a heated TiW- or TiN-coated substrate is used to planarize topography. The final temperature of 450 degrees C provides enough Al mobility to planarize 2- mu m-wide features. The deposition of 1.5-2.0 times the feature depth with a >250/450 degrees C two-temperature process and a deposition rate approximately=100 AA/s gives good planarization uniformity over >6-cm wafer radius. Submicron trenches are planarized without voids, whereas windows with h/w>1 have voids. Also, 1- mu m-deep trenches are filled, whereas 2- mu m-deep trenches are not filled with a similar process. Scanning electron microscopy correlates planarization and via filling with the evaporation process and substrate topography. The effect of high-temperature evaporation on materials integrity is studied with diode leakage measurements. At 450 degrees C for <2 min required for the second step, there is no Al/(TiW or TiN)/Si interaction. However, the process is close to the failure temperature of the 1000-AA-thick (less than or approximately equal to 500 AA thick in 1 mu m features) TiW barrier layer since Al spiking is seen when the final step is >or approximately=500 degrees C.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129857929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A major prerequisite for voidless planarization is the initial formation of a smooth continuous aluminum film on the walls of the vias. Thermal control diffusion length can then be used to transport metal from the top surface into the features. This has been achieved using a high throughput, multistep process on an ECLIPSE sputtering system. The initial substrate temperature determines the film thickness requirements for complete film coalescence. A smooth continuous film can be produced within the first step 250 AA if deposited below 200 degrees C. At higher temperatures a continuous film may not be formed until a much larger amount of aluminum is deposited, and shadowing of the opening may occur before via filling can be done. Once the continuous coating is formed, wafer temperature is elevated to a level where surface mobility is greatly enhanced: typically between 400 degrees C and 500 degrees C.<>
{"title":"Multi-step aluminum planarization process","authors":"A. Aronson, J. Roberts, K. Armstrong, I. Wagner","doi":"10.1109/VMIC.1989.78055","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78055","url":null,"abstract":"Summary form only given. A major prerequisite for voidless planarization is the initial formation of a smooth continuous aluminum film on the walls of the vias. Thermal control diffusion length can then be used to transport metal from the top surface into the features. This has been achieved using a high throughput, multistep process on an ECLIPSE sputtering system. The initial substrate temperature determines the film thickness requirements for complete film coalescence. A smooth continuous film can be produced within the first step 250 AA if deposited below 200 degrees C. At higher temperatures a continuous film may not be formed until a much larger amount of aluminum is deposited, and shadowing of the opening may occur before via filling can be done. Once the continuous coating is formed, wafer temperature is elevated to a level where surface mobility is greatly enhanced: typically between 400 degrees C and 500 degrees C.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130714660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A silicate-type spin-on-glass (SOG) was used to planarize topography prior to metal deposition. SOG was chosen for this application because of the simplicity associated with processing. The topography smoothing capability was shown to be comparable to that of flowed CVD oxide. It was found that curing the SOG in a dry oxygen ambient caused the film to densify poorly and to result in inferior dielectric properties. Performing the cure in a steam ambient, however, resulted in films with dielectric properties similar to those of CVD oxide films. This dielectric was used successfully in a 1.0- mu m double-level metal process without degrading device performance. It was shown that the film does not need to be fully densified in order to be used in this application. Temperature/humidity testing showed no anomalous effects to devices due to moisture absorption or film delamination.<>
{"title":"Premetal planarization using spin-on-dielectric","authors":"F. Whitwer, T. Davies, C. Lage","doi":"10.1109/VMIC.1989.78011","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78011","url":null,"abstract":"A silicate-type spin-on-glass (SOG) was used to planarize topography prior to metal deposition. SOG was chosen for this application because of the simplicity associated with processing. The topography smoothing capability was shown to be comparable to that of flowed CVD oxide. It was found that curing the SOG in a dry oxygen ambient caused the film to densify poorly and to result in inferior dielectric properties. Performing the cure in a steam ambient, however, resulted in films with dielectric properties similar to those of CVD oxide films. This dielectric was used successfully in a 1.0- mu m double-level metal process without degrading device performance. It was shown that the film does not need to be fully densified in order to be used in this application. Temperature/humidity testing showed no anomalous effects to devices due to moisture absorption or film delamination.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134275192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The application of spin-on-glass (SOG) planarization at both the polysilicon and first metal level in a 1- mu m CMOS process developed for the manufacture of ASIC devices is described. At the polysilicon level, SOG planarization is considered for future applications since the planarization can be optimized for performance and reliability almost independently of the salicide module which is an integral part of the process. This is possible because SOG planarization is essentially a low-temperature process which does not result in degradation of the salicide. Its performance is compared to that achieved with BPSG planarization under first metal. Above first metal, SOG is used in the process for reasons of manufacturability. The performance is compared to that achieved using a previously developed resist etchback process. For both applications, SOG shows excellent performance, as illustrated by electrical data. The SOG deposition process is discussed along with relevant materials data.<>
介绍了一种用于制造ASIC器件的1 μ m CMOS工艺在多晶硅和第一金属水平上的玻璃自旋(SOG)平面化应用。在多晶硅层面，SOG平面化被认为是未来的应用，因为平面化可以优化性能和可靠性，几乎独立于salicide模块，这是该工艺的一个组成部分。这是可能的，因为SOG平面化本质上是一个低温过程，不会导致水杨酸的降解。将其性能与第一金属下的BPSG平面化技术进行了比较。在第一种金属之上，由于可制造性的原因，在工艺中使用SOG。将其性能与先前开发的抗蚀剂蚀刻工艺进行了比较。对于这两种应用，SOG表现出优异的性能，如电气数据所示。讨论了SOG的沉积过程，并提供了相关的材料数据。
{"title":"SOG planarization for polysilicon and first metal interconnect in a one micron CMOS process","authors":"L. Forester, A. Butler, G. Schets","doi":"10.1109/VMIC.1989.78008","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78008","url":null,"abstract":"The application of spin-on-glass (SOG) planarization at both the polysilicon and first metal level in a 1- mu m CMOS process developed for the manufacture of ASIC devices is described. At the polysilicon level, SOG planarization is considered for future applications since the planarization can be optimized for performance and reliability almost independently of the salicide module which is an integral part of the process. This is possible because SOG planarization is essentially a low-temperature process which does not result in degradation of the salicide. Its performance is compared to that achieved with BPSG planarization under first metal. Above first metal, SOG is used in the process for reasons of manufacturability. The performance is compared to that achieved using a previously developed resist etchback process. For both applications, SOG shows excellent performance, as illustrated by electrical data. The SOG deposition process is discussed along with relevant materials data.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. An improved process that uses a novel thermal flow/thermal setting polymer that can planarize even the largest geometries after a reflow at 200 degrees C is described. The planarization properties of this novel polymer were determined by coating it over 1.0- mu m step heights of different widths. The step heights over the line structure before and after the polymer coating were measured using a profilometer. A 1.2- mu m thick coating was used in these studies. The planarization etch was carried out in a reactive-ion-etching system. The etch rates of SiON depended weakly on the oxygen content, while the etch rates of the new organic material are a strong function of the oxygen content. Due to local loading effects, the etch rate ratio of the polymer to the CVD dielectric film cannot be maintained at a 1:1 ratio as measured by test wafers. In fact, the ratio has to be considerably less than 1 to give a planarized surface.<>
{"title":"An improved etchback planarization process using a super planarizing spin-on sacrificial layer","authors":"C. Ting, P. Pai, Zbignew Sobczack","doi":"10.1109/VMIC.1989.78045","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78045","url":null,"abstract":"Summary form only given. An improved process that uses a novel thermal flow/thermal setting polymer that can planarize even the largest geometries after a reflow at 200 degrees C is described. The planarization properties of this novel polymer were determined by coating it over 1.0- mu m step heights of different widths. The step heights over the line structure before and after the polymer coating were measured using a profilometer. A 1.2- mu m thick coating was used in these studies. The planarization etch was carried out in a reactive-ion-etching system. The etch rates of SiON depended weakly on the oxygen content, while the etch rates of the new organic material are a strong function of the oxygen content. Due to local loading effects, the etch rate ratio of the polymer to the CVD dielectric film cannot be maintained at a 1:1 ratio as measured by test wafers. In fact, the ratio has to be considerably less than 1 to give a planarized surface.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129235881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.D. Colgate, G.J. Palenik, V. E. House, D. Schoenfeld, C. Simon
Summary form only given. Area-selective metal-organic chemical vapor deposition (MOCVD) of gold thin films has been achieved on tungsten patterned on VLSI-type silicon wafers. Scanning Auger spectroscopy of the wafer deposition areas displays virtual exclusion of gold deposits on silicious regions with 4000-AA-thick gold films of high feature resolution covering the tungsten patterns. The films were deposited by exposing the heated wafer (T<500 degrees C) to an ambient of (C/sub 2/H/sub 5/)/sub 3/PAuCl vapor for 1 h.<>
{"title":"Area selective gold MOCVD for VLSI electronics","authors":"S.D. Colgate, G.J. Palenik, V. E. House, D. Schoenfeld, C. Simon","doi":"10.1109/VMIC.1989.78052","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78052","url":null,"abstract":"Summary form only given. Area-selective metal-organic chemical vapor deposition (MOCVD) of gold thin films has been achieved on tungsten patterned on VLSI-type silicon wafers. Scanning Auger spectroscopy of the wafer deposition areas displays virtual exclusion of gold deposits on silicious regions with 4000-AA-thick gold films of high feature resolution covering the tungsten patterns. The films were deposited by exposing the heated wafer (T<500 degrees C) to an ambient of (C/sub 2/H/sub 5/)/sub 3/PAuCl vapor for 1 h.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121390357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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