D. Moy, M. Schadt, C. Hu, F. Kaufman, A. Ray, N. Mazzeo, E. Baran, D. Pearson
Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. A structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti/Al(2.5%Cu)/Si metal lines patterned by reactive ion etching. This structure has been successfully implemented both on BEOL test sites and in device runs to fabricate a selectively scaled 0.5- mu m-channel-length 64-kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal to or better than that achieved with metal lift-off processing. Functional testing of the 64-kb SRAM produced many chips with better than 90% yield, which is also equal to or better than that achieved with a nonplanarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2. No degradation of device characteristics due to the BEOL processing could be detected.<>
{"title":"A two-level metal fully planarized interconnect structure implemented on a 64 kb CMOS SRAM","authors":"D. Moy, M. Schadt, C. Hu, F. Kaufman, A. Ray, N. Mazzeo, E. Baran, D. Pearson","doi":"10.1109/VMIC.1989.78072","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78072","url":null,"abstract":"Planarization of VLSI interconnect structures is recognized as a crucial element in advanced BEOL. A structure is presented which uses full oxide planarization before the first and second metal layers, W studs for contacts and interlevel vias, and Ti/Al(2.5%Cu)/Si metal lines patterned by reactive ion etching. This structure has been successfully implemented both on BEOL test sites and in device runs to fabricate a selectively scaled 0.5- mu m-channel-length 64-kb high-performance CMOS SRAM chip. Electrical testing results show contact resistances and metal test site yields equal to or better than that achieved with metal lift-off processing. Functional testing of the 64-kb SRAM produced many chips with better than 90% yield, which is also equal to or better than that achieved with a nonplanarized lift-off process. Use of the M2 level in this chip design as a bit line strap reduced access time from 11 ns without M2 to roughly 6 ns with M2. No degradation of device characteristics due to the BEOL processing could be detected.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127980438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The potential of high-T/sub c/ superconductive interconnects in CMOS-based digital systems is examined theoretically using system simulation, a new design tool for electronic packages and systems. A 1.5- mu m-technology CMOS processor, with 500000 circuits partitioned into 25 chips packaged as a single multichip module, is examined. The best implementation with superconductive interconnects at 77 K has a cycle time of 9.6 ns, which is about six times faster than the baseline design with normal metal (Al, Cu) interconnects at 300 K.<>
{"title":"Potential of low temperature CMOS with normal and superconductive interconnect","authors":"J. Krusius, W. E. Pence","doi":"10.1109/VMIC.1989.78026","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78026","url":null,"abstract":"The potential of high-T/sub c/ superconductive interconnects in CMOS-based digital systems is examined theoretically using system simulation, a new design tool for electronic packages and systems. A 1.5- mu m-technology CMOS processor, with 500000 circuits partitioned into 25 chips packaged as a single multichip module, is examined. The best implementation with superconductive interconnects at 77 K has a cycle time of 9.6 ns, which is about six times faster than the baseline design with normal metal (Al, Cu) interconnects at 300 K.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A new technique for studying aluminum microstructure is introduced. It utilizes reactive ion etching (RIE) to delineate the Al grain structure so that it can be clearly seen using a scanning electron microscope (SEM). The RIE/SEM technique produces identical results of the average Al grain radius and the grain size distribution as those obtained using transmission electron microscopy (TEM). The advantage of this technique over TEM is that sample preparation is greatly simplified and a large contiguous area can be studied. Previous studies of the Al microstructure, using TEM, have shown that there is a drastic increase in the electromigration median-time-to-fail (MTTF) as the Al grain diameter approaches the metal line width. The phenomenon is known as the bamboo effect. The authors present Al microstructure data from electromigration lines using RIE/SEM technique to show an additional cause for the increase in MTTF hidden in the bamboo effect. The total number of grains, triple points, bamboo grains, and electromigration MTTF were measured from Al-1%Si metal electromigration lots. The results show that the number of triple points is a more critical factor in electromigration performance than the number of bamboo grains.<>
{"title":"Microstructural effect on the electromigration of aluminum interconnects","authors":"K. Wu, P. Jupiter, W. Baerg","doi":"10.1109/VMIC.1989.78057","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78057","url":null,"abstract":"Summary form only given. A new technique for studying aluminum microstructure is introduced. It utilizes reactive ion etching (RIE) to delineate the Al grain structure so that it can be clearly seen using a scanning electron microscope (SEM). The RIE/SEM technique produces identical results of the average Al grain radius and the grain size distribution as those obtained using transmission electron microscopy (TEM). The advantage of this technique over TEM is that sample preparation is greatly simplified and a large contiguous area can be studied. Previous studies of the Al microstructure, using TEM, have shown that there is a drastic increase in the electromigration median-time-to-fail (MTTF) as the Al grain diameter approaches the metal line width. The phenomenon is known as the bamboo effect. The authors present Al microstructure data from electromigration lines using RIE/SEM technique to show an additional cause for the increase in MTTF hidden in the bamboo effect. The total number of grains, triple points, bamboo grains, and electromigration MTTF were measured from Al-1%Si metal electromigration lots. The results show that the number of triple points is a more critical factor in electromigration performance than the number of bamboo grains.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The film properties from a sputtering system utilizing separately cryopumped chambers for loading, etching, heating, and deposition were evaluated using designed experiments. This system provided unique aluminum-silicon doped films in response to traditional processing setpoints used in batch or even closed-coupled, single-wafer-deposited, common vacuum systems. Due to this and process constraints, 12 film properties were characterized as a function of three key inputs utilizing the designed experimental approach. The reason for altering the standard film was to achieve a transparent metal film that would be equal in all other aspects to the current metal film. This would allow the use of either the new sputter system or the one being used now without any change in processing the film through the photoresist and etch process flows.<>
{"title":"Sputtered film characteristics evaluated through designed experiments","authors":"B. M. Roberts, C.M. Dalton","doi":"10.1109/VMIC.1989.78050","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78050","url":null,"abstract":"Summary form only given. The film properties from a sputtering system utilizing separately cryopumped chambers for loading, etching, heating, and deposition were evaluated using designed experiments. This system provided unique aluminum-silicon doped films in response to traditional processing setpoints used in batch or even closed-coupled, single-wafer-deposited, common vacuum systems. Due to this and process constraints, 12 film properties were characterized as a function of three key inputs utilizing the designed experimental approach. The reason for altering the standard film was to achieve a transparent metal film that would be equal in all other aspects to the current metal film. This would allow the use of either the new sputter system or the one being used now without any change in processing the film through the photoresist and etch process flows.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117197689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A self-aligned vertical Kelvin test resistor structure, which not only eliminates the horizontal current crowding but also avoids the misalignment error, is proposed and used to measure p/sub c/ of Al and Ti on Si. For the Al(1%Si)/n/sup +/-Si contact system, a specific contact resistivity of 1*10/sup -7/ Omega -cm/sup 2/ has been measured. For the TiSi/sub 2/ contacts, the TiSi/sub 2/(direct-reaction)/n/sup +/-Si contact offers a lower p/sub c/ than that of the coevaporated TiSi/sub 2//n/sup +/-Si contact, and p/sub c/ does not change even after the contacts are annealed to 900 degrees C.<>
{"title":"A self-aligned vertical Kelvin test structure to measure contact resistivities of Al and Ti on Si","authors":"W. Yang, T. F. Lei, C. Lee","doi":"10.1109/VMIC.1989.78030","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78030","url":null,"abstract":"A self-aligned vertical Kelvin test resistor structure, which not only eliminates the horizontal current crowding but also avoids the misalignment error, is proposed and used to measure p/sub c/ of Al and Ti on Si. For the Al(1%Si)/n/sup +/-Si contact system, a specific contact resistivity of 1*10/sup -7/ Omega -cm/sup 2/ has been measured. For the TiSi/sub 2/ contacts, the TiSi/sub 2/(direct-reaction)/n/sup +/-Si contact offers a lower p/sub c/ than that of the coevaporated TiSi/sub 2//n/sup +/-Si contact, and p/sub c/ does not change even after the contacts are annealed to 900 degrees C.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128680641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A summary of various types of SOG materials and their properties is presented. The authors correlate these properties with molecular structure and constituents such as phosphorous and methyl dopants. Process integration issues associated with each type of SOG material are also discussed.<>
{"title":"Understanding of spin-on-glass (SOG) properties from their molecular structure","authors":"C. Chiang, D. Fraser","doi":"10.1109/VMIC.1989.78000","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78000","url":null,"abstract":"A summary of various types of SOG materials and their properties is presented. The authors correlate these properties with molecular structure and constituents such as phosphorous and methyl dopants. Process integration issues associated with each type of SOG material are also discussed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132006333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A report is presented on Ti as an antireflective coating (ARC) to solve the problems encountered using excimer lasers to melt and planarize an Al film. The composite metal film consists of 100-AA Ti on 0.5-1- mu m Al on 1000-AA Ti:W, where Ti is the ARC and Ti:W serves as both a wetting layer and a diffusion barrier. The absorptivity at 308 nm of this composite film has been measured as 0.4, which is about five times higher than that of Al. The introduction Ti ARC widens the process window (via-fill to ablation) from +or-6-8 to more than +or-20%. ARC does not improve the via-fill limit: the temperature of sufficient Al flow to fill contact windows is not lowered. Rather, the wider process window is achieved by pushing the ablation limit towards a higher laser fluence range. It is concluded that 100-AA Ti is not a desirable ARC. However, the value of an ARC in widening the process window is very important to laser planarization and has been demonstrated.<>
只提供摘要形式。本文报道了Ti作为一种抗反射涂层(ARC)来解决准分子激光熔化和平化铝膜时遇到的问题。复合金属膜由100-AA Ti和0.5-1- μ m Al和1000-AA Ti:W组成，其中Ti为ARC, Ti:W既是润湿层又是扩散屏障。该复合膜在308 nm处的吸光率为0.4，约为Al的5倍。Ti电弧的引入将工艺窗口(通过填充到烧蚀)从+or-6-8扩大到+or-20%以上。电弧并不能提高通过填充的限制:足够的铝流填充接触窗口的温度没有降低。相反，更宽的工艺窗口是通过将烧蚀极限推向更高的激光通量范围来实现的。结果表明，100-AA Ti不是理想的电弧。然而，电弧在扩大工艺窗口方面的价值对激光平面化非常重要，并已得到证实。
{"title":"The use of Ti as an antireflective coating for the laser planarization of Al for VLSI metallization","authors":"Y. Lai, R. Liu, K. Cheung, R. Heim","doi":"10.1109/VMIC.1989.78064","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78064","url":null,"abstract":"Summary form only given. A report is presented on Ti as an antireflective coating (ARC) to solve the problems encountered using excimer lasers to melt and planarize an Al film. The composite metal film consists of 100-AA Ti on 0.5-1- mu m Al on 1000-AA Ti:W, where Ti is the ARC and Ti:W serves as both a wetting layer and a diffusion barrier. The absorptivity at 308 nm of this composite film has been measured as 0.4, which is about five times higher than that of Al. The introduction Ti ARC widens the process window (via-fill to ablation) from +or-6-8 to more than +or-20%. ARC does not improve the via-fill limit: the temperature of sufficient Al flow to fill contact windows is not lowered. Rather, the wider process window is achieved by pushing the ablation limit towards a higher laser fluence range. It is concluded that 100-AA Ti is not a desirable ARC. However, the value of an ARC in widening the process window is very important to laser planarization and has been demonstrated.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129281319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Chiang, M. Lee, D. Fraser, L.C. Yip, S. Mittal, K. Wu
The authors report the interaction of an aluminium film with its underlying LPCVD dielectric film. The LPCVD film absorbs moisture in the atmospheric environment and causes severe degradation in subsequently deposited metal films. The addition of phosphorus appears to have two competing effects: enhancement of water absorption and densification of the film. The authors have identified deposition temperature, plasma power density, and ion bombardment as parameters for improving dielectric film stability. Modifying the oxide network by doping the glass and/or providing energy during oxide deposition improves the dielectric integrity, and this type of stable dielectric film is very essential for a multilevel interconnect system.<>
{"title":"Interaction of metal with underlying dielectric films in multilevel interconnect systems","authors":"C. Chiang, M. Lee, D. Fraser, L.C. Yip, S. Mittal, K. Wu","doi":"10.1109/VMIC.1989.78039","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78039","url":null,"abstract":"The authors report the interaction of an aluminium film with its underlying LPCVD dielectric film. The LPCVD film absorbs moisture in the atmospheric environment and causes severe degradation in subsequently deposited metal films. The addition of phosphorus appears to have two competing effects: enhancement of water absorption and densification of the film. The authors have identified deposition temperature, plasma power density, and ion bombardment as parameters for improving dielectric film stability. Modifying the oxide network by doping the glass and/or providing energy during oxide deposition improves the dielectric integrity, and this type of stable dielectric film is very essential for a multilevel interconnect system.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126488235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An atmospheric-pressure CVD technology using TEOS, ozone, and new organometallic doping sources, such as tris(trimethylsilil)borate, ((CH/sub 3/)/sub 3/SiO)/sub 3/B, is described. This technology offers excellent dielectric films with respect to step coverage, film stress, moisture resistance, and thermal flow characteristics. Nondoped silicon dioxide and BSG films are deposited to cover conformably even a deeply trenched substrate. They can be used as a dielectric film between a polysilicon and an aluminum layer or between aluminum layers without any planarization process. BPSG films showed good step coverage, and could be smoothly reflowed at a low temperature.<>
{"title":"Dielectric film deposition by atmospheric pressure and low temperature CVD using TEOS, ozone, and new organometallic doping sources","authors":"Y. Nishimoto, N. Tokumasu, K. Fujino, K. Maeda","doi":"10.1109/VMIC.1989.77998","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77998","url":null,"abstract":"An atmospheric-pressure CVD technology using TEOS, ozone, and new organometallic doping sources, such as tris(trimethylsilil)borate, ((CH/sub 3/)/sub 3/SiO)/sub 3/B, is described. This technology offers excellent dielectric films with respect to step coverage, film stress, moisture resistance, and thermal flow characteristics. Nondoped silicon dioxide and BSG films are deposited to cover conformably even a deeply trenched substrate. They can be used as a dielectric film between a polysilicon and an aluminum layer or between aluminum layers without any planarization process. BPSG films showed good step coverage, and could be smoothly reflowed at a low temperature.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"50 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114019016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. An AlSi/TiW metal system with enhanced performance, which is expected to upgrade AlSi/TiW metallization, has been developed. The standard VLSI process is followed for the contact formation. Before the AlSi deposition, TiW is deposited and annealed, using rapid thermal annealing (RTA), at temperatures ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively, low-temperature alloy is then treated either by furnace annealing or RTA. The average p/sup +/ contact resistance for a 1.2- mu m*1.2- mu m contact is about 25 Omega as compared to 80 Omega for the conventional process. No junction degradation is observed at all for this higher-temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C for 30 min is twice as large as that for samples alloyed at 410 degrees C, for 30 min or 425 degrees C for 40 s with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<>
{"title":"Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process","authors":"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan","doi":"10.1109/VMIC.1989.78053","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78053","url":null,"abstract":"Summary form only given. An AlSi/TiW metal system with enhanced performance, which is expected to upgrade AlSi/TiW metallization, has been developed. The standard VLSI process is followed for the contact formation. Before the AlSi deposition, TiW is deposited and annealed, using rapid thermal annealing (RTA), at temperatures ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively, low-temperature alloy is then treated either by furnace annealing or RTA. The average p/sup +/ contact resistance for a 1.2- mu m*1.2- mu m contact is about 25 Omega as compared to 80 Omega for the conventional process. No junction degradation is observed at all for this higher-temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C for 30 min is twice as large as that for samples alloyed at 410 degrees C, for 30 min or 425 degrees C for 40 s with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127653054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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