A ballistic deposition technique, SIMBAD, has been developed and used to simulate sputter deposition of metal over a 2- mu m step and over 1- mu m vias of various geometries. In addition to generating step coverage and surface profiles at different stages of growth, SIMBAD provides further information unattainable through conventional film growth simulation packages. Predictions of local film density and microstructure are presented, and low-density regions occurring on the sidewalls and in corners of steps and vias are analyzed.<>
{"title":"Simulation of density variation and step coverage for via metallization","authors":"T. Smy, R. Tait, K. Westra, M. Brett","doi":"10.1109/VMIC.1989.78033","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78033","url":null,"abstract":"A ballistic deposition technique, SIMBAD, has been developed and used to simulate sputter deposition of metal over a 2- mu m step and over 1- mu m vias of various geometries. In addition to generating step coverage and surface profiles at different stages of growth, SIMBAD provides further information unattainable through conventional film growth simulation packages. Predictions of local film density and microstructure are presented, and low-density regions occurring on the sidewalls and in corners of steps and vias are analyzed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Room-temperature bias electron cyclotron resonance plasma deposition of both carbon- and silicon-based planarization materials has been demonstrated. Planarization layers of amorphous hydrogenated carbon (a-C:H) have been deposited from 1-butene and 1,3-butadiene. Oxide and aluminum features 1- mu m deep by 2- mu m wide have been planarized to less than 50 nm in height using 1.2- mu m-thick a-C:H films. Silicon dioxide layers have been deposited using a mixture of N/sub 2/O, Ar, and 5% SiH/sub 4/ diluted in N/sub 2/. Using films nominally 1.5 mu m thick, 800-nm-deep topography can be reduced to less than 50 nm for lines as wide as 3 mu m. The planarizing SiO/sub 2/ layers have been characterized using ellipsometry and Auger electron spectroscopy and found to have a refractive index and stoichiometry comparable to those of thermally grown gate oxide. The time necessary for planarization and the final film thickness are dependent upon the aspect ratio of the features to be planarized and the deposition conditions.<>
{"title":"Planarizing a-C:H and SiO/sub 2/ films prepared by bias electron cyclotron resonance plasma deposition","authors":"M. Horn, S. Pang, M. Rothschild","doi":"10.1109/VMIC.1989.78007","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78007","url":null,"abstract":"Room-temperature bias electron cyclotron resonance plasma deposition of both carbon- and silicon-based planarization materials has been demonstrated. Planarization layers of amorphous hydrogenated carbon (a-C:H) have been deposited from 1-butene and 1,3-butadiene. Oxide and aluminum features 1- mu m deep by 2- mu m wide have been planarized to less than 50 nm in height using 1.2- mu m-thick a-C:H films. Silicon dioxide layers have been deposited using a mixture of N/sub 2/O, Ar, and 5% SiH/sub 4/ diluted in N/sub 2/. Using films nominally 1.5 mu m thick, 800-nm-deep topography can be reduced to less than 50 nm for lines as wide as 3 mu m. The planarizing SiO/sub 2/ layers have been characterized using ellipsometry and Auger electron spectroscopy and found to have a refractive index and stoichiometry comparable to those of thermally grown gate oxide. The time necessary for planarization and the final film thickness are dependent upon the aspect ratio of the features to be planarized and the deposition conditions.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115102228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel contact fill scheme using a silicide plug has been developed. The scheme combines selective epitaxial Si growth (SEG) and silicide formation to form selective silicide contact plugs. Silicide plugs can be implemented in both n/sup +/ and p/sup +/ contacts with low contact resistance, high temperature stability, and good planarity. TEM and electrical measurements show that the above approach can be used to fill contact depth up to 1 mu m and contact aspect ratio up to 1. The lack of a silicidation stop and the incomplete epi-Si consumption are two issues to be solved. For deeper contacts or contacts with higher aspect ratio, postsilicidation plug implantations become necessary to guarantee low contact resistances.<>
{"title":"The use of selective silicide plugs for submicron contact fill","authors":"C. Wei, V. Murali, M. Dass, D. Fraser, J. Borland","doi":"10.1109/VMIC.1989.78016","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78016","url":null,"abstract":"A novel contact fill scheme using a silicide plug has been developed. The scheme combines selective epitaxial Si growth (SEG) and silicide formation to form selective silicide contact plugs. Silicide plugs can be implemented in both n/sup +/ and p/sup +/ contacts with low contact resistance, high temperature stability, and good planarity. TEM and electrical measurements show that the above approach can be used to fill contact depth up to 1 mu m and contact aspect ratio up to 1. The lack of a silicidation stop and the incomplete epi-Si consumption are two issues to be solved. For deeper contacts or contacts with higher aspect ratio, postsilicidation plug implantations become necessary to guarantee low contact resistances.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121756540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Fu, E. Travis, S. Sun, C. L. Grove, R. Pyle, F. Pintchovski, P. Schani
The electromigration resistance for the Al-Cu-Si alloy/titanium nitride/titanium silicide barrier contact system was evaluated as a function of the deposited Ti thickness (0-1000 AA). Both the conventional constant current stress and current ramping stress were applied. It was found that the electromigration resistance of the contact structure increases with the Ti thickness monotonically, although the rate of increase reduces drastically once the Ti thickness exceeds 400 AA. At a Ti thickness of 1000 AA, the mean time to failure is more than an order of magnitude longer than that of contacts without the titanium nitride barrier. There is an excellent correlation between the result derived from conventional constant current stress and that from the current ramping stress. The current ramp method, therefore, can be used as a relative reliability indicator for contact structures on wafer-level tests. Thermal stress data show that an adequate margin of thermal stability exists for contact structures at all Ti thicknesses (>or=200 AA). Accordingly, a process window for the Ti thickness in this technology can be defined depending on the requirement of electromigration resistance for contacts.<>
{"title":"Ti-thickness dependent electromigration resistance of the Al-Cu-Si/TiN/sub x//TiSi/sub y/ barrier contact system","authors":"K. Fu, E. Travis, S. Sun, C. L. Grove, R. Pyle, F. Pintchovski, P. Schani","doi":"10.1109/VMIC.1989.78035","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78035","url":null,"abstract":"The electromigration resistance for the Al-Cu-Si alloy/titanium nitride/titanium silicide barrier contact system was evaluated as a function of the deposited Ti thickness (0-1000 AA). Both the conventional constant current stress and current ramping stress were applied. It was found that the electromigration resistance of the contact structure increases with the Ti thickness monotonically, although the rate of increase reduces drastically once the Ti thickness exceeds 400 AA. At a Ti thickness of 1000 AA, the mean time to failure is more than an order of magnitude longer than that of contacts without the titanium nitride barrier. There is an excellent correlation between the result derived from conventional constant current stress and that from the current ramping stress. The current ramp method, therefore, can be used as a relative reliability indicator for contact structures on wafer-level tests. Thermal stress data show that an adequate margin of thermal stability exists for contact structures at all Ti thicknesses (>or=200 AA). Accordingly, a process window for the Ti thickness in this technology can be defined depending on the requirement of electromigration resistance for contacts.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The selective deposition of CVD tungsten has been extensively studied as a promising technique for filling contacts and vias in semiconductor devices. The immediate need to apply this technology to devices with submicron contacts and vias requires that consideration be given to defect density, probe yield, process yield, and manufacturability. In addition, process control reliability must also be addressed. The authors show the yield effect of selective tungsten deposition as compared to a standard process flow. The 256 K DRAM was chosen as the test vehicle for the study. The most strongly affected electrical parameters were the contact resistances. In some cases degradation was bad enough to cause continuity failure in the functional tests. Across-wafer uniformities and failure analysis results for the different processes are also reported.<>
{"title":"Effect of selective tungsten contact fills on manufacturing issues","authors":"R. Blumenthal, B. Alburn","doi":"10.1109/VMIC.1989.78046","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78046","url":null,"abstract":"Summary form only given. The selective deposition of CVD tungsten has been extensively studied as a promising technique for filling contacts and vias in semiconductor devices. The immediate need to apply this technology to devices with submicron contacts and vias requires that consideration be given to defect density, probe yield, process yield, and manufacturability. In addition, process control reliability must also be addressed. The authors show the yield effect of selective tungsten deposition as compared to a standard process flow. The 256 K DRAM was chosen as the test vehicle for the study. The most strongly affected electrical parameters were the contact resistances. In some cases degradation was bad enough to cause continuity failure in the functional tests. Across-wafer uniformities and failure analysis results for the different processes are also reported.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128665421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. An analytical model for the fringing capacitance is described based on the work of C.-D. Yuan and T. Trick (IEEE Electron Device Lett. vol. EDL-3, p.391-3, 1982) that closely approximates the electric-field configuration at the edges of the line. The author extends this previous work by including in the model the effect of crossing wiring levels and adjacent lines. The model is based on the physics of electric field and therefore is not limited to a specific interconnect technology. It has been used to determine the extent of fringing in various configuration and the point at which adjacent lines modify the fringing capacitance. The equations in the model for the fringing capacitance are not complex and are well suited for interactive CAD applications. Comparison of the results of the analytical model to numerical simulations has shown good agreement over a broad range of dimensions, typically within 15% for separations to crossing levels and adjacent lines down to 1.0 mu m.<>
{"title":"Modeling the fringe capacitance of multilevel VLSI interconnects","authors":"L. Dunlop","doi":"10.1109/VMIC.1989.78043","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78043","url":null,"abstract":"Summary form only given. An analytical model for the fringing capacitance is described based on the work of C.-D. Yuan and T. Trick (IEEE Electron Device Lett. vol. EDL-3, p.391-3, 1982) that closely approximates the electric-field configuration at the edges of the line. The author extends this previous work by including in the model the effect of crossing wiring levels and adjacent lines. The model is based on the physics of electric field and therefore is not limited to a specific interconnect technology. It has been used to determine the extent of fringing in various configuration and the point at which adjacent lines modify the fringing capacitance. The equations in the model for the fringing capacitance are not complex and are well suited for interactive CAD applications. Comparison of the results of the analytical model to numerical simulations has shown good agreement over a broad range of dimensions, typically within 15% for separations to crossing levels and adjacent lines down to 1.0 mu m.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A description is given of spun-on film contour modeling and characterization procedures that can be used to predict the planarization properties presented for resist and spin-on glass (SOG) materials. These parameters are related to spun-on solution properties and can be used to design spin-on film properties and processes to obtain specific planarization results. An equation describing the spin-on film contour is presented. The parameters appearing in the equation can be used to predict planarization properties on any complex topography and with multiple spun-on coatings. SOG films require special modeling considerations due to mass depletion effects, since their thin spun-on film thicknesses are typically much less than the step height.<>
{"title":"Modelling spin-on film planarization properties","authors":"L. White","doi":"10.1109/VMIC.1989.78041","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78041","url":null,"abstract":"Summary form only given. A description is given of spun-on film contour modeling and characterization procedures that can be used to predict the planarization properties presented for resist and spin-on glass (SOG) materials. These parameters are related to spun-on solution properties and can be used to design spin-on film properties and processes to obtain specific planarization results. An equation describing the spin-on film contour is presented. The parameters appearing in the equation can be used to predict planarization properties on any complex topography and with multiple spun-on coatings. SOG films require special modeling considerations due to mass depletion effects, since their thin spun-on film thicknesses are typically much less than the step height.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133750422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Deleonibus, C. Arena, M. Heitzmann, F. Martin, J. Lajzerowicz, F. Vinet
Summary form only given. A comparison is made of the behavior of metal 2 gate NMOS field transistors using three types of double-level aluminum interconnect isolation process for submicron CMOS application. The three insulators used are permanent spin-on-glass (SOG) process, partial etchback SOG process, and totally sacrificial SOG. Six-transistor-cell CMOS 16 K SRAMs laid out with 0.8- mu m design rules have been processed using the three processes. The total etchback process gives the best results, giving values of I/sub cc/ 10 times lower than that obtained in the permanent SOG process.<>
{"title":"Field transistors electrical behaviour in double level aluminum interconnect processes","authors":"S. Deleonibus, C. Arena, M. Heitzmann, F. Martin, J. Lajzerowicz, F. Vinet","doi":"10.1109/VMIC.1989.78060","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78060","url":null,"abstract":"Summary form only given. A comparison is made of the behavior of metal 2 gate NMOS field transistors using three types of double-level aluminum interconnect isolation process for submicron CMOS application. The three insulators used are permanent spin-on-glass (SOG) process, partial etchback SOG process, and totally sacrificial SOG. Six-transistor-cell CMOS 16 K SRAMs laid out with 0.8- mu m design rules have been processed using the three processes. The total etchback process gives the best results, giving values of I/sub cc/ 10 times lower than that obtained in the permanent SOG process.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128626432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The effects of various refractory metal and silicide capping layers on aluminum metallizations are investigated. Ti-Al, Mo-Al, Ta-Al, WSi/sub 2/-Al, and MoSi/sub 2/-Al layered structures are compared in terms of electromigration and stress-induced voiding. The authors have found that the Ti-Al layered structure can suppress stress-induced void formation in underlying Al conductors. The effect of the Ti-Al layered structure on the suppression of stress-induced voiding can be attributed to the formation of the intermetallic compound Al/sub 3/Ti, which prevents plastic deformation of the film. Electromigration results indicate that the capping layers of refractory metals and silicides such as Ti, W, WSi/sub 2/, and MoSi/sub 2/ improve the mean time to failure by 4-10 times compared with Al without capping.<>
{"title":"Comparison of refractory metal and silicide capping effects on aluminum metallizations","authors":"T. Kikkawa, N. Endo, T. Yamazaki, H. Watanabe","doi":"10.1109/VMIC.1989.78038","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78038","url":null,"abstract":"The effects of various refractory metal and silicide capping layers on aluminum metallizations are investigated. Ti-Al, Mo-Al, Ta-Al, WSi/sub 2/-Al, and MoSi/sub 2/-Al layered structures are compared in terms of electromigration and stress-induced voiding. The authors have found that the Ti-Al layered structure can suppress stress-induced void formation in underlying Al conductors. The effect of the Ti-Al layered structure on the suppression of stress-induced voiding can be attributed to the formation of the intermetallic compound Al/sub 3/Ti, which prevents plastic deformation of the film. Electromigration results indicate that the capping layers of refractory metals and silicides such as Ti, W, WSi/sub 2/, and MoSi/sub 2/ improve the mean time to failure by 4-10 times compared with Al without capping.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121048810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The functional yield of a double-level metal CMOS process for fabrication of 5-V VLSI 10K-gate arrays was evaluated with large-area drop-in test structures designed to identify process yield loss mechanisms. The test structure yields were correlated to device functional yields. This analysis was able to quantitatively determine the yield limiting parameters by order of significance. Pareto problem ranking analysis provides specific directions to allocate engineering resources in yield enhancement efforts without first performing extensive failure analysis or experiments, or using intuitive rationale. This method shortens the evaluation cycle for identifying specific problems and solutions by using the product itself to uncover subtle yield relationships in an ongoing manner. This gives a clear direction for yield enhancement. After evaluation of several test parameters, using various yield models, it was determined that the Stapper model provided the best mathematical fit for comparing parametric to functional yields.<>
{"title":"Evolution of functional correlation as an engineering directive for VLSI yield enhancement","authors":"R. Angell, C. Keith, C. Lukasik, J. Monk","doi":"10.1109/VMIC.1989.78032","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78032","url":null,"abstract":"The functional yield of a double-level metal CMOS process for fabrication of 5-V VLSI 10K-gate arrays was evaluated with large-area drop-in test structures designed to identify process yield loss mechanisms. The test structure yields were correlated to device functional yields. This analysis was able to quantitatively determine the yield limiting parameters by order of significance. Pareto problem ranking analysis provides specific directions to allocate engineering resources in yield enhancement efforts without first performing extensive failure analysis or experiments, or using intuitive rationale. This method shortens the evaluation cycle for identifying specific problems and solutions by using the product itself to uncover subtle yield relationships in an ongoing manner. This gives a clear direction for yield enhancement. After evaluation of several test parameters, using various yield models, it was determined that the Stapper model provided the best mathematical fit for comparing parametric to functional yields.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：