A report is presented on the results of a comparative series of experiments conducted on thin polyimide layers, of thicknesses in the range approximately 600 A to >1.5 mu m, containing intentionally introduced and controlled amounts of Na. The levels of Na ranged from undoped (<0.2 p.p.m.) to 200 p.p.m. in the starting stock. These films were characterized using I/V and C/V measurements on MIS structures fabricated on Si wafers. Although the very best PI films has resistivities of approximately 10/sup 16/ Omega -cm the authors feel that, for use for gate isolation, the Na/sup +/ contamination level in the polyimide dielectric would need to be less than 0.2 p.p.m. for stable device operation.<>
{"title":"Electrical properties of polyimides for interlevel isolation and active device gate isolation","authors":"A. Dubey, D. Lile","doi":"10.1109/VMIC.1989.77999","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77999","url":null,"abstract":"A report is presented on the results of a comparative series of experiments conducted on thin polyimide layers, of thicknesses in the range approximately 600 A to >1.5 mu m, containing intentionally introduced and controlled amounts of Na. The levels of Na ranged from undoped (<0.2 p.p.m.) to 200 p.p.m. in the starting stock. These films were characterized using I/V and C/V measurements on MIS structures fabricated on Si wafers. Although the very best PI films has resistivities of approximately 10/sup 16/ Omega -cm the authors feel that, for use for gate isolation, the Na/sup +/ contamination level in the polyimide dielectric would need to be less than 0.2 p.p.m. for stable device operation.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"128 13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131890408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Omega on p-type and 57 Omega on n-type diffusion layers for 0.6- mu m hole diameter and 0.8- mu m hole depth. Moreover, a shallow source/drain junction of 0.15- mu m depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time.<>
{"title":"Low contact resistance polysilicon plug for halfmicron CMOS technology","authors":"T. Hamajima, Y. Sugano","doi":"10.1109/VMIC.1989.78017","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78017","url":null,"abstract":"A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Omega on p-type and 57 Omega on n-type diffusion layers for 0.6- mu m hole diameter and 0.8- mu m hole depth. Moreover, a shallow source/drain junction of 0.15- mu m depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132190531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors have shown that under certain conditions carbon-based spin-on-glasses (SOGs) can cause field inversion leading to failure of devices. The authors formulate a model that explains the leakage. On the basis of this model it is possible to use the carbon-based SOGs in double-metal circuits without field inversion by restricting the amount of SOG by doing an etchback and using a passivation that does not liberate H, such as oxynitride or oxide. Some of the recent dielectric deposition systems can deposit nitride films that evolve little to no H on annealing. It is possible to use inorganic SOGs such as phosphorus-doped silicates and not have the problem at all. However, the issue of cracking with these SOGs is always of concern for reliability. The model raises concerns about the presence of organic compounds in the intermetal dielectric either through the use of organic reactants such as TEOS or inadvertently through the incomplete removal of photoresist during some of the masking steps.<>
{"title":"Field inversion in CMOS double metal circuits due to carbon based SOGs","authors":"D. Pramanik, S. Nariani, G. Spadini","doi":"10.1109/VMIC.1989.78037","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78037","url":null,"abstract":"The authors have shown that under certain conditions carbon-based spin-on-glasses (SOGs) can cause field inversion leading to failure of devices. The authors formulate a model that explains the leakage. On the basis of this model it is possible to use the carbon-based SOGs in double-metal circuits without field inversion by restricting the amount of SOG by doing an etchback and using a passivation that does not liberate H, such as oxynitride or oxide. Some of the recent dielectric deposition systems can deposit nitride films that evolve little to no H on annealing. It is possible to use inorganic SOGs such as phosphorus-doped silicates and not have the problem at all. However, the issue of cracking with these SOGs is always of concern for reliability. The model raises concerns about the presence of organic compounds in the intermetal dielectric either through the use of organic reactants such as TEOS or inadvertently through the incomplete removal of photoresist during some of the masking steps.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The possibility of using amorphous carbon as an encapsulant for integrated circuits is investigated. As this is a low-temperature plasma-deposited carbon film, low stresses result. This reduces the possibility of bond wire breakages and stress on the underlying film. Its low-temperature deposition, chemical inactivity, highly electrical insulating properties, and imperviousness to the passage of contaminating gases, liquids, and ions make it a suitable encapsulant for circuits. These properties also make it a potential replacement for silicon nitride. The possibility of using amorphous carbon as a wire encapsulant at interconnect level is also explored.<>
{"title":"Low temperature plasma amorphous carbon encapsulation for reliable multilevel interconnections-with applications to wafer scale multichip packaging","authors":"J. McDonald, S. Dabral, S. Wu, A. Martı́n, T. Lu","doi":"10.1109/VMIC.1989.77996","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77996","url":null,"abstract":"The possibility of using amorphous carbon as an encapsulant for integrated circuits is investigated. As this is a low-temperature plasma-deposited carbon film, low stresses result. This reduces the possibility of bond wire breakages and stress on the underlying film. Its low-temperature deposition, chemical inactivity, highly electrical insulating properties, and imperviousness to the passage of contaminating gases, liquids, and ions make it a suitable encapsulant for circuits. These properties also make it a potential replacement for silicon nitride. The possibility of using amorphous carbon as a wire encapsulant at interconnect level is also explored.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130676408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Resistive contrast imaging (RCI) is a new failure analysis technique that uses a scanning electron microscope to generate a relative resistance map of an integrated circuit. The RCI map can be used to localize abrupt changes in resistance and verify continuity. Results using RCI on several two-level interconnection devices are described. The images demonstrate how RCI can be used to differentiate between levels and to localize metal shorts and opens. Methods for improving image quality and level differentiation as well as future development work are discussed.<>
{"title":"Resistive contrast imaging applied to multilevel interconnection failure analysis","authors":"E. I. Cole","doi":"10.1109/VMIC.1989.78020","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78020","url":null,"abstract":"Resistive contrast imaging (RCI) is a new failure analysis technique that uses a scanning electron microscope to generate a relative resistance map of an integrated circuit. The RCI map can be used to localize abrupt changes in resistance and verify continuity. Results using RCI on several two-level interconnection devices are described. The images demonstrate how RCI can be used to differentiate between levels and to localize metal shorts and opens. Methods for improving image quality and level differentiation as well as future development work are discussed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pulsed laser melting of Al to improve the contact via coverage in VLSI metallization has been investigated for various laser fluences and substrate temperatures. The authors have characterized how the Al flow phenomenon progresses: from melting (recrystallization and grain growth) to planarization (via covered but not necessarily filled), then to via-fill (solidly plugged), and finally from localized to systematic ablation (material loss). The laser energy densities for these conditions have been quantified and the useful range for VLSI application extracted. Without antireflective coating, the process window is +or-6-8% for 0.5- mu m Al film to fill a 1- mu m via with a vertical wall. Localized ablation of the Al film at the high energy limit has been found to be the key factor that controls the process window. This limitation can be explained by the estimated temperature rise of the Al film from melting to planarization and via-fill conditions: very high at 400-500 degrees C and 700-800 degrees C above the melting temperature, respectively. The issues of VLSI applications such as pattern density sensitivity and device integrity have been examined.<>
{"title":"A study of pulsed laser planarization of aluminum for VLSI metallization","authors":"R. Liu, K. Cheung, W. Lai, R. Heim","doi":"10.1109/VMIC.1989.77992","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77992","url":null,"abstract":"Pulsed laser melting of Al to improve the contact via coverage in VLSI metallization has been investigated for various laser fluences and substrate temperatures. The authors have characterized how the Al flow phenomenon progresses: from melting (recrystallization and grain growth) to planarization (via covered but not necessarily filled), then to via-fill (solidly plugged), and finally from localized to systematic ablation (material loss). The laser energy densities for these conditions have been quantified and the useful range for VLSI application extracted. Without antireflective coating, the process window is +or-6-8% for 0.5- mu m Al film to fill a 1- mu m via with a vertical wall. Localized ablation of the Al film at the high energy limit has been found to be the key factor that controls the process window. This limitation can be explained by the estimated temperature rise of the Al film from melting to planarization and via-fill conditions: very high at 400-500 degrees C and 700-800 degrees C above the melting temperature, respectively. The issues of VLSI applications such as pattern density sensitivity and device integrity have been examined.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123446813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. High-aspect-ratio via filling by rapid thermal melting of Al has been achieved, but with two major drawbacks. Pure or 0.5%-Cu-doped Al films 0.5- to 1.5- mu m thick were deposited on two types of wafer. Some wafers were patterned with 0.75- to 2- mu m-deep windows formed into deposited SiO while others have no topography. The Al films were deposited on 90-nm TiN or TiW layers. TiN, TiW or SiO/sub 2/ capping was used on some wafers. By melting Al deposited on several substrates the authors found that molten Al did not wet TiN. The Al balled up and pulled away from the surface. It seemed to wet W:Ti, however, along with a metallurgical reaction between Al, W, and Si resulting in the formation of several alloys of W and Al, as well as W:(Si,Al)/sub 2/. Although Al melts at 660 degrees C it did not flow until temperatures above 800 degrees C were achieved. However, even at these temperatures via-filling was not observed in 0.5- mu m-thick Al films. The authors found that Al thickness of 1 mu m or more was required for filling micron-size vias. The high temperature required for the Al flow which causes junction degradation and the agglomeration of Al film are two severe drawbacks for using the RTA technique in Al planarization.<>
{"title":"Melt and flow behavior of Al into micron size features using incoherent radiation","authors":"A. Kamgar, R. C. Beairsto","doi":"10.1109/VMIC.1989.78054","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78054","url":null,"abstract":"Summary form only given. High-aspect-ratio via filling by rapid thermal melting of Al has been achieved, but with two major drawbacks. Pure or 0.5%-Cu-doped Al films 0.5- to 1.5- mu m thick were deposited on two types of wafer. Some wafers were patterned with 0.75- to 2- mu m-deep windows formed into deposited SiO while others have no topography. The Al films were deposited on 90-nm TiN or TiW layers. TiN, TiW or SiO/sub 2/ capping was used on some wafers. By melting Al deposited on several substrates the authors found that molten Al did not wet TiN. The Al balled up and pulled away from the surface. It seemed to wet W:Ti, however, along with a metallurgical reaction between Al, W, and Si resulting in the formation of several alloys of W and Al, as well as W:(Si,Al)/sub 2/. Although Al melts at 660 degrees C it did not flow until temperatures above 800 degrees C were achieved. However, even at these temperatures via-filling was not observed in 0.5- mu m-thick Al films. The authors found that Al thickness of 1 mu m or more was required for filling micron-size vias. The high temperature required for the Al flow which causes junction degradation and the agglomeration of Al film are two severe drawbacks for using the RTA technique in Al planarization.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126116069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<>
{"title":"Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process","authors":"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan","doi":"10.1109/vmic.1989.78061","DOIUrl":"https://doi.org/10.1109/vmic.1989.78061","url":null,"abstract":"Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of research on shadow step structures (3S), which are prepatterned, mesa-type geometries that are electrically self-isolating and self-aligning when overlaid with a conducting film. This basic mesa topography has been historically used as a disposable medium for lift-off metallization and other generic patterning forms. A modification of this technique has recently been useful in providing an analytic tool for the maskless evaluation of as-deposited thin-film conductors. On an experimental basis, 3S is being used as an intermediate means to verify the sheet resistivity and tempco of sichrome resistor films. Also, the formation of electromigration patterns is used as a simplified, nonintrusive alternative to the current fabrication method. The 3S technique is being evaluated for other QTAT analyses including the quantifying of physical film stress and Schottky diodes, together with other bulk silicon devices which evaluate metal-silicon interfaces.<>
{"title":"Shadow step structures for the analysis of thin film conductors","authors":"W.C. Rosvold","doi":"10.1109/VMIC.1989.78031","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78031","url":null,"abstract":"A description is given of research on shadow step structures (3S), which are prepatterned, mesa-type geometries that are electrically self-isolating and self-aligning when overlaid with a conducting film. This basic mesa topography has been historically used as a disposable medium for lift-off metallization and other generic patterning forms. A modification of this technique has recently been useful in providing an analytic tool for the maskless evaluation of as-deposited thin-film conductors. On an experimental basis, 3S is being used as an intermediate means to verify the sheet resistivity and tempco of sichrome resistor films. Also, the formation of electromigration patterns is used as a simplified, nonintrusive alternative to the current fabrication method. The 3S technique is being evaluated for other QTAT analyses including the quantifying of physical film stress and Schottky diodes, together with other bulk silicon devices which evaluate metal-silicon interfaces.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133926620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of this discussion is to provide some insight into matters that will affect the technologist's career in the coming decade. The author examines some of these factors from the viewpoint of the integrated circuit technologist. The role of production is assessed along with utilization of active devices on top of the silicon integrated circuit. The author argues that for the technologist, the new devices will introduce requirements for additional materials knowledge, additional processing knowledge, greater complexity of test equipment, and additional failure modes.<>
{"title":"Your future in the technology evolution of the 90's","authors":"G. Madland","doi":"10.1109/VMIC.1989.78070","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78070","url":null,"abstract":"The purpose of this discussion is to provide some insight into matters that will affect the technologist's career in the coming decade. The author examines some of these factors from the viewpoint of the integrated circuit technologist. The role of production is assessed along with utilization of active devices on top of the silicon integrated circuit. The author argues that for the technologist, the new devices will introduce requirements for additional materials knowledge, additional processing knowledge, greater complexity of test equipment, and additional failure modes.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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