Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159328
L. Chu, T. Lin, C. H. Lee, L. T. Tung, W. Lee, R. Chu, C. C. Chang, M. Hong, J. Kwo
Ultra-high vacuum (UHV)-deposited high Ga2O3(Gd2O3) was proved to passivate Ge effectively, as evidenced by comprehensive investigations including structural, chemical, and electrical analyses. The Ga2O3(Gd2O3)/Ge interface is revealed to be abrupt even being subjected to a 500°C anneal, a high κ value of 14.5, a low leakage current density of ∼10−9A/cm2 with a Fowler-Nordheim tunneling behavior, and well-behaved C-V characteristics are achieved. Furthermore, Ge self-aligned pMOSFETs with Al2O3/ Ga2O3(Gd2O3) as the gate dielectrics have demonstrated a high drain current and a peak transconductance up to 252mA/mm and 143mS/mm, respectively, of 1µm-gate length.
{"title":"Metal-oxide-semiconductor devices with UHV-Ga2O3(Gd2O3) on Ge(100)","authors":"L. Chu, T. Lin, C. H. Lee, L. T. Tung, W. Lee, R. Chu, C. C. Chang, M. Hong, J. Kwo","doi":"10.1109/VTSA.2009.5159328","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159328","url":null,"abstract":"Ultra-high vacuum (UHV)-deposited high Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) was proved to passivate Ge effectively, as evidenced by comprehensive investigations including structural, chemical, and electrical analyses. The Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>)/Ge interface is revealed to be abrupt even being subjected to a 500°C anneal, a high κ value of 14.5, a low leakage current density of ∼10<inf>−9</inf>A/cm<sup>2</sup> with a Fowler-Nordheim tunneling behavior, and well-behaved C-V characteristics are achieved. Furthermore, Ge self-aligned pMOSFETs with Al<inf>2</inf>O<inf>3</inf>/ Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) as the gate dielectrics have demonstrated a high drain current and a peak transconductance up to 252mA/mm and 143mS/mm, respectively, of 1µm-gate length.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159333
H. Hsu, T. Liu, Chuan-Ding Lin, Chiu Kuo-Jung, Tiao-Yuan Huang, Horng-Chih Lin
Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and/or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.
{"title":"Tri-gated poly-Si nanowire SONOS devices","authors":"H. Hsu, T. Liu, Chuan-Ding Lin, Chiu Kuo-Jung, Tiao-Yuan Huang, Horng-Chih Lin","doi":"10.1109/VTSA.2009.5159333","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159333","url":null,"abstract":"Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and/or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123318380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159314
D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, G. Ghibaudo
In this study, a new technique to extract the S/D series resistance (Rsd) from the total resistance versus transconductance gain plot Rtot(1/β) is proposed. The technique only requires the measurement of Id(Vgs)|Vgt and β, allowing fast and statistical analysis in an industrial context. Unlike the usual Rtot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for Rsd(Vgs) and the effective mobility reduction factor µeff(Vgt)/µeff(0).
{"title":"A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs","authors":"D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, G. Ghibaudo","doi":"10.1109/VTSA.2009.5159314","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159314","url":null,"abstract":"In this study, a new technique to extract the S/D series resistance (R<inf>sd</inf>) from the total resistance versus transconductance gain plot R<inf>tot</inf>(1/β) is proposed. The technique only requires the measurement of I<inf>d</inf>(V<inf>gs</inf>)|<inf>Vgt</inf> and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R<inf>tot</inf>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<inf>sd</inf>(V<inf>gs</inf>) and the effective mobility reduction factor µ<inf>eff</inf>(V<inf>gt</inf>)/µ<inf>eff</inf>(0).","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159286
P. Feng
Nanoscale devices with mechanical degrees of freedom offer compelling characteristics that make them very attractive for mechanical and quantum logic devices. As we are able to create nanoelectromechanical systems (NEMS) with unprecedented feature sizes, advanced complexity and functionality, and high yield and control (at wafer-scale), they become increasingly interesting for low-power logic and memory, as well as become more meaningful for VLSI. Partly this is driven by NEMS devices' unique merits such as exceptionally large on/off ratio, non-leakage, ultralow switching power, fast speed, and temperature insensitivity. In parallel, this is also an intriguing effort in the quest for the ultimately energy-efficient implementation of logic and computing. In this talk, I shall introduce the Caltech research effort towards these goals, including the recent demonstrations of several generic prototypes of nanoscale electromechanical switching devices, their characteristics and performance, progress on engineering such building blocks for NEMS-based logic and memory, all-mechanical and hybrid NEMS-CMOS, along with discussions and perspectives of technological promises and challenges.
{"title":"Nanoelectromechanical systems for ultra-low-power computing and VLSI","authors":"P. Feng","doi":"10.1109/VTSA.2009.5159286","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159286","url":null,"abstract":"Nanoscale devices with mechanical degrees of freedom offer compelling characteristics that make them very attractive for mechanical and quantum logic devices. As we are able to create nanoelectromechanical systems (NEMS) with unprecedented feature sizes, advanced complexity and functionality, and high yield and control (at wafer-scale), they become increasingly interesting for low-power logic and memory, as well as become more meaningful for VLSI. Partly this is driven by NEMS devices' unique merits such as exceptionally large on/off ratio, non-leakage, ultralow switching power, fast speed, and temperature insensitivity. In parallel, this is also an intriguing effort in the quest for the ultimately energy-efficient implementation of logic and computing. In this talk, I shall introduce the Caltech research effort towards these goals, including the recent demonstrations of several generic prototypes of nanoscale electromechanical switching devices, their characteristics and performance, progress on engineering such building blocks for NEMS-based logic and memory, all-mechanical and hybrid NEMS-CMOS, along with discussions and perspectives of technological promises and challenges.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159335
C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu
The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E≪10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.
{"title":"Reliability study of MANOS with and without a SiO2 buffer layer and BE-MANOS charge-trapping NAND flash devices","authors":"C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159335","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159335","url":null,"abstract":"The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E≪10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159298
Hao-I Yang, C. Chuang, W. Hwang
We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected cells also impacted SRAM RSNM and WM. The leakage currents and virtual supply bounce were reduced, but wake-up time became longer. Longer precharge phase and judicious choice of sense amplifier structure would improve the tolerance to NBTI effects.
{"title":"Impacts of NBTI on SRAM array with power gating structure","authors":"Hao-I Yang, C. Chuang, W. Hwang","doi":"10.1109/VTSA.2009.5159298","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159298","url":null,"abstract":"We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected cells also impacted SRAM RSNM and WM. The leakage currents and virtual supply bounce were reduced, but wake-up time became longer. Longer precharge phase and judicious choice of sense amplifier structure would improve the tolerance to NBTI effects.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159280
C. H. Liu, Y. M. Lin, Y. Sakamoto, R. Yang, D. Yin, P. Chiang, H. Wei, C. Ho, S. H. Chen, H. Hwang, C. Hung, S. Pittikoun, S. Aritome
Multi-Nitridation ONO has been demonstrated for the first time. Significant improvement are obtained in NAND Flash performance and reliability. (1) 1V program voltage reduction owing to 10A EOT (equivalant oxide thickness ) reduction (2) More than 20% tighter cell Vt distribution width can be achieved from ONO bird's beak free due to supressing encroachment of gate re-oxidation by Floating Gate (FG) / top oxide nitridation. And also, (3) good data retention can be realized by applying plasma oxidation on bottom oxide to suppress the trap assisted charge loss. MN-ONO is a promising technology for high density NAND Flash beyond 40nm generation.
{"title":"A novel Multi - Nitridation ONO interpoly dielectric (MN-ONO) for highly reliable and high performance NAND Flash memory","authors":"C. H. Liu, Y. M. Lin, Y. Sakamoto, R. Yang, D. Yin, P. Chiang, H. Wei, C. Ho, S. H. Chen, H. Hwang, C. Hung, S. Pittikoun, S. Aritome","doi":"10.1109/VTSA.2009.5159280","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159280","url":null,"abstract":"Multi-Nitridation ONO has been demonstrated for the first time. Significant improvement are obtained in NAND Flash performance and reliability. (1) 1V program voltage reduction owing to 10A EOT (equivalant oxide thickness ) reduction (2) More than 20% tighter cell Vt distribution width can be achieved from ONO bird's beak free due to supressing encroachment of gate re-oxidation by Floating Gate (FG) / top oxide nitridation. And also, (3) good data retention can be realized by applying plasma oxidation on bottom oxide to suppress the trap assisted charge loss. MN-ONO is a promising technology for high density NAND Flash beyond 40nm generation.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159331
C. Le Royer, A. Pouydebasque, K. Romanjek, V. Barral, M. Vinet, J. Hartmann, E. Augendre, H. Grampeix, L. Lachal, C. Tabone, B. Previtali, R. Truche, F. Allain
We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (vinj) were extracted, demonstrating 22% higher vinj in Ge than in Si.
{"title":"Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity","authors":"C. Le Royer, A. Pouydebasque, K. Romanjek, V. Barral, M. Vinet, J. Hartmann, E. Augendre, H. Grampeix, L. Lachal, C. Tabone, B. Previtali, R. Truche, F. Allain","doi":"10.1109/VTSA.2009.5159331","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159331","url":null,"abstract":"We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (vinj) were extracted, demonstrating 22% higher vinj in Ge than in Si.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114904360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159297
M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of ΦBp of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×1014 atoms-cm−2, leading to lowering of contact resistance at NiSi/p+-Si S/D junction.
{"title":"p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction","authors":"M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo","doi":"10.1109/VTSA.2009.5159297","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159297","url":null,"abstract":"This paper demonstrates the integration of Al segregated NiSi/p<sup>+</sup>-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p<sup>+</sup> S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of Φ<inf>B</inf><sup>p</sup> of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×10<sup>14</sup> atoms-cm<sup>−2</sup>, leading to lowering of contact resistance at NiSi/p<sup>+</sup>-Si S/D junction.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123782358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159325
Y. Chang, W. Chang, H. Chiu, Y. H. Chang, L. T. Tung, C. H. Lee, M. Hong, J. Kwo, J. Hong, C. Tsai
For the first time, inversion-channel GaN MOSFETs using atomic-layer-deposited (ALD) Al2O3 as a gate dielectric have been successfully fabricated, showing well-behaved drain I–V and transfer characteristics. The drain current was scaled with gate length, showing a maximum drain current of 10 mA/mm in a device of 1 µm gate length, at a gate voltage (Vgs) of 8 V and a drain voltage (Vds) of 10V. High Ion/Ioff ratio of 2.5×105 was achieved with a very low off-state leakage of 4×10−13A/µm. In addition, depletion-mode (D-mode) GaN MOSFETs have also been demonstrated, showing a very low on-resistance of 2.5 mΩ⋅cm2, a high mobility of 350 cm2/Vs, and a high maximum drain current of 300 mA/mm in a device of 4 µm gate length.
{"title":"Inversion-channel GaN MOSFET using atomic-layer-deposited Al2O3 as gate dielectric","authors":"Y. Chang, W. Chang, H. Chiu, Y. H. Chang, L. T. Tung, C. H. Lee, M. Hong, J. Kwo, J. Hong, C. Tsai","doi":"10.1109/VTSA.2009.5159325","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159325","url":null,"abstract":"For the first time, inversion-channel GaN MOSFETs using atomic-layer-deposited (ALD) Al<inf>2</inf>O<inf>3</inf> as a gate dielectric have been successfully fabricated, showing well-behaved drain I–V and transfer characteristics. The drain current was scaled with gate length, showing a maximum drain current of 10 mA/mm in a device of 1 µm gate length, at a gate voltage (V<inf>gs</inf>) of 8 V and a drain voltage (V<inf>ds</inf>) of 10V. High I<inf>on</inf>/I<inf>off</inf> ratio of 2.5×10<sup>5</sup> was achieved with a very low off-state leakage of 4×10<sup>−13</sup>A/µm. In addition, depletion-mode (D-mode) GaN MOSFETs have also been demonstrated, showing a very low on-resistance of 2.5 mΩ⋅cm<sup>2</sup>, a high mobility of 350 cm<sup>2</sup>/Vs, and a high maximum drain current of 300 mA/mm in a device of 4 µm gate length.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132734754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：