Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159317
V. Hu, Yu-Sheng Wu, M. Fan, P. Su, C. Chuang
This paper investigates the Static Noise Margin (SNM) of Ultra-Thin-Body (UTB) SOI SRAM cells operating in subthreshold region using analytical solution of Poisson's equation validated with TCAD simulations. An analytical SNM model for UTB SOI SRAM cells operating in subthreshold region is presented. Our results indicate that back-gate bias (Vbg) can mitigate the Read SNM (RSNM) variability of UTB SOI SRAM cells in the subthreshold region, and the improvement of SNM variability is more significant than superthreshold region. Increasing cell β-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in subthreshold region.
本文利用泊松方程的解析解和TCAD仿真验证了在亚阈值区域工作的超薄体SOI SRAM单元的静态噪声裕度(SNM)。提出了UTB SOI SRAM单元在亚阈值区域工作的解析SNM模型。研究结果表明，反向偏置(Vbg)可以降低UTB SOI SRAM细胞在阈下区域的读SNM (RSNM)变异性，且SNM变异性的改善比阈上区域更为显著。增加细胞β比对RSNM的改善有限，对阈下操作的SNM变异性没有好处。UTB SOI 8T SRAM单元在亚阈值区域的RSNM比6T SRAM单元大2倍。
{"title":"Investigation of static noise margin of Ultra-Thin-Body SOI SRAM cells in subthreshold region using analytical solution of poisson's equation","authors":"V. Hu, Yu-Sheng Wu, M. Fan, P. Su, C. Chuang","doi":"10.1109/VTSA.2009.5159317","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159317","url":null,"abstract":"This paper investigates the Static Noise Margin (SNM) of Ultra-Thin-Body (UTB) SOI SRAM cells operating in subthreshold region using analytical solution of Poisson's equation validated with TCAD simulations. An analytical SNM model for UTB SOI SRAM cells operating in subthreshold region is presented. Our results indicate that back-gate bias (Vbg) can mitigate the Read SNM (RSNM) variability of UTB SOI SRAM cells in the subthreshold region, and the improvement of SNM variability is more significant than superthreshold region. Increasing cell β-ratio shows limited improvement on RSNM and has no benefit on SNM variability for subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2X larger than the 6T SRAM cell in subthreshold region.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127190104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159298
Hao-I Yang, C. Chuang, W. Hwang
We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected cells also impacted SRAM RSNM and WM. The leakage currents and virtual supply bounce were reduced, but wake-up time became longer. Longer precharge phase and judicious choice of sense amplifier structure would improve the tolerance to NBTI effects.
{"title":"Impacts of NBTI on SRAM array with power gating structure","authors":"Hao-I Yang, C. Chuang, W. Hwang","doi":"10.1109/VTSA.2009.5159298","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159298","url":null,"abstract":"We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected cells also impacted SRAM RSNM and WM. The leakage currents and virtual supply bounce were reduced, but wake-up time became longer. Longer precharge phase and judicious choice of sense amplifier structure would improve the tolerance to NBTI effects.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159286
P. Feng
Nanoscale devices with mechanical degrees of freedom offer compelling characteristics that make them very attractive for mechanical and quantum logic devices. As we are able to create nanoelectromechanical systems (NEMS) with unprecedented feature sizes, advanced complexity and functionality, and high yield and control (at wafer-scale), they become increasingly interesting for low-power logic and memory, as well as become more meaningful for VLSI. Partly this is driven by NEMS devices' unique merits such as exceptionally large on/off ratio, non-leakage, ultralow switching power, fast speed, and temperature insensitivity. In parallel, this is also an intriguing effort in the quest for the ultimately energy-efficient implementation of logic and computing. In this talk, I shall introduce the Caltech research effort towards these goals, including the recent demonstrations of several generic prototypes of nanoscale electromechanical switching devices, their characteristics and performance, progress on engineering such building blocks for NEMS-based logic and memory, all-mechanical and hybrid NEMS-CMOS, along with discussions and perspectives of technological promises and challenges.
{"title":"Nanoelectromechanical systems for ultra-low-power computing and VLSI","authors":"P. Feng","doi":"10.1109/VTSA.2009.5159286","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159286","url":null,"abstract":"Nanoscale devices with mechanical degrees of freedom offer compelling characteristics that make them very attractive for mechanical and quantum logic devices. As we are able to create nanoelectromechanical systems (NEMS) with unprecedented feature sizes, advanced complexity and functionality, and high yield and control (at wafer-scale), they become increasingly interesting for low-power logic and memory, as well as become more meaningful for VLSI. Partly this is driven by NEMS devices' unique merits such as exceptionally large on/off ratio, non-leakage, ultralow switching power, fast speed, and temperature insensitivity. In parallel, this is also an intriguing effort in the quest for the ultimately energy-efficient implementation of logic and computing. In this talk, I shall introduce the Caltech research effort towards these goals, including the recent demonstrations of several generic prototypes of nanoscale electromechanical switching devices, their characteristics and performance, progress on engineering such building blocks for NEMS-based logic and memory, all-mechanical and hybrid NEMS-CMOS, along with discussions and perspectives of technological promises and challenges.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"156 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132395370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159289
J. Pétry, G. Boccardi, R. Singanamalla, C.S. Liu, K. Xiong, P. Escanes, J. Huguenin, J. Tseng, L. Van Nimwegen, F. Voogt, C. Bulle-lieuwma, M. Muller
Easily integrable cost effective gate first Single Metal Single Dielectric (SMSD) solution based on As implantation into TiN/HfO2 with ∼ 1 nm EOT is presented. A consistent n-type shift of 250 mV down to 35 nm Lg is obtained by As I/I compared to the reference stack. Symmetrical threshold voltages (∼ ±0.5 V) are met for the bulk planar devices using this technique, which would corresponds to low-VT (±0.2V) target for the FD FETs. The possible counter-doping effects were evaluated electrically and physically with backside SIMS. It was found to be negligible implying negligible concentration of As in the channel region. As I/I technique opens up possibility of multiple VT tuning without adding any process complexity.
{"title":"A VFB tunable Single Metal Single Dielectric approach using As I/I into TiN/HfO2 for 32nm node and beyond","authors":"J. Pétry, G. Boccardi, R. Singanamalla, C.S. Liu, K. Xiong, P. Escanes, J. Huguenin, J. Tseng, L. Van Nimwegen, F. Voogt, C. Bulle-lieuwma, M. Muller","doi":"10.1109/VTSA.2009.5159289","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159289","url":null,"abstract":"Easily integrable cost effective gate first Single Metal Single Dielectric (SMSD) solution based on As implantation into TiN/HfO2 with ∼ 1 nm EOT is presented. A consistent n-type shift of 250 mV down to 35 nm Lg is obtained by As I/I compared to the reference stack. Symmetrical threshold voltages (∼ ±0.5 V) are met for the bulk planar devices using this technique, which would corresponds to low-VT (±0.2V) target for the FD FETs. The possible counter-doping effects were evaluated electrically and physically with backside SIMS. It was found to be negligible implying negligible concentration of As in the channel region. As I/I technique opens up possibility of multiple VT tuning without adding any process complexity.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"54 62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159279
S. Z. Rahaman, S. Maikap, C. Lin, T. Wu, Y. S. Chen, P. Tzeng, F. Chen, C. S. Lai, M. Kao, M. Tsai
Low current/voltage (∼10 nA/1.0V) resistive switching memory device in a Cu/Ta2O5/W structure has been proposed. The low resistance state (RLow) of the memory device decreases with increasing the programming current from 10 nA to 1mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (RHigh/RLow) of 5.3×107, good endurance of ≫103 cycles, and excellent retention (≫11 hours) with resistance ratio of ≫ 9×103 can be useful in future non-volatile memory applications.
{"title":"Low current and voltage resistive switching memory device using novel Cu/Ta2O5/W structure","authors":"S. Z. Rahaman, S. Maikap, C. Lin, T. Wu, Y. S. Chen, P. Tzeng, F. Chen, C. S. Lai, M. Kao, M. Tsai","doi":"10.1109/VTSA.2009.5159279","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159279","url":null,"abstract":"Low current/voltage (∼10 nA/1.0V) resistive switching memory device in a Cu/Ta<inf>2</inf>O<inf>5</inf>/W structure has been proposed. The low resistance state (R<inf>Low</inf>) of the memory device decreases with increasing the programming current from 10 nA to 1mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (R<inf>High</inf>/R<inf>Low</inf>) of 5.3×10<sup>7</sup>, good endurance of ≫10<sup>3</sup> cycles, and excellent retention (≫11 hours) with resistance ratio of ≫ 9×10<sup>3</sup> can be useful in future non-volatile memory applications.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159335
C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu
The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E≪10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.
{"title":"Reliability study of MANOS with and without a SiO2 buffer layer and BE-MANOS charge-trapping NAND flash devices","authors":"C.W. Liao, S. Lai, H. Lue, Ming-Jui Yang, C. Shen, Y. Lue, Yu-Fong Huang, J. Hsieh, Szu-Yu Wang, G. Luo, C. Chien, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159335","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159335","url":null,"abstract":"The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E≪10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159280
C. H. Liu, Y. M. Lin, Y. Sakamoto, R. Yang, D. Yin, P. Chiang, H. Wei, C. Ho, S. H. Chen, H. Hwang, C. Hung, S. Pittikoun, S. Aritome
Multi-Nitridation ONO has been demonstrated for the first time. Significant improvement are obtained in NAND Flash performance and reliability. (1) 1V program voltage reduction owing to 10A EOT (equivalant oxide thickness ) reduction (2) More than 20% tighter cell Vt distribution width can be achieved from ONO bird's beak free due to supressing encroachment of gate re-oxidation by Floating Gate (FG) / top oxide nitridation. And also, (3) good data retention can be realized by applying plasma oxidation on bottom oxide to suppress the trap assisted charge loss. MN-ONO is a promising technology for high density NAND Flash beyond 40nm generation.
{"title":"A novel Multi - Nitridation ONO interpoly dielectric (MN-ONO) for highly reliable and high performance NAND Flash memory","authors":"C. H. Liu, Y. M. Lin, Y. Sakamoto, R. Yang, D. Yin, P. Chiang, H. Wei, C. Ho, S. H. Chen, H. Hwang, C. Hung, S. Pittikoun, S. Aritome","doi":"10.1109/VTSA.2009.5159280","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159280","url":null,"abstract":"Multi-Nitridation ONO has been demonstrated for the first time. Significant improvement are obtained in NAND Flash performance and reliability. (1) 1V program voltage reduction owing to 10A EOT (equivalant oxide thickness ) reduction (2) More than 20% tighter cell Vt distribution width can be achieved from ONO bird's beak free due to supressing encroachment of gate re-oxidation by Floating Gate (FG) / top oxide nitridation. And also, (3) good data retention can be realized by applying plasma oxidation on bottom oxide to suppress the trap assisted charge loss. MN-ONO is a promising technology for high density NAND Flash beyond 40nm generation.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159331
C. Le Royer, A. Pouydebasque, K. Romanjek, V. Barral, M. Vinet, J. Hartmann, E. Augendre, H. Grampeix, L. Lachal, C. Tabone, B. Previtali, R. Truche, F. Allain
We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (vinj) were extracted, demonstrating 22% higher vinj in Ge than in Si.
{"title":"Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity","authors":"C. Le Royer, A. Pouydebasque, K. Romanjek, V. Barral, M. Vinet, J. Hartmann, E. Augendre, H. Grampeix, L. Lachal, C. Tabone, B. Previtali, R. Truche, F. Allain","doi":"10.1109/VTSA.2009.5159331","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159331","url":null,"abstract":"We report here experimental investigations on GeOI pMOSFET: Besides the +65% mobility enhancement in narrow channel GeOI pMOSFETs as compared to wide channels, attributed to improved sidewall transport properties, 〈100〉 channel orientation transport is investigated for the first time in Ge (001): unlike Si, no current gain is observed compared to 〈110〉 channel orientation. Finally, ballisticity rates (BR) and source injection velocities (vinj) were extracted, demonstrating 22% higher vinj in Ge than in Si.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114904360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159297
M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of ΦBp of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×1014 atoms-cm−2, leading to lowering of contact resistance at NiSi/p+-Si S/D junction.
{"title":"p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction","authors":"M. Sinha, Rinus Lee, S. N. Devi, G. Lo, E. Chor, Y. Yeo","doi":"10.1109/VTSA.2009.5159297","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159297","url":null,"abstract":"This paper demonstrates the integration of Al segregated NiSi/p<sup>+</sup>-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p<sup>+</sup> S/D region followed by nickel deposition and silicidation. Drive current enhancement of ∼15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of Φ<inf>B</inf><sup>p</sup> of NiSi on p-Si from 0.4 eV to 0.12 eV with low Al dose of 2×10<sup>14</sup> atoms-cm<sup>−2</sup>, leading to lowering of contact resistance at NiSi/p<sup>+</sup>-Si S/D junction.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123782358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159276
M. Nishikawa, K. Okabe, K. Ikeda, N. Tamura, H. Maekawa, M. Umeyama, H. Kurata, M. Kase, K. Hashimoto
We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/µm at Vd = 1.0 V and Ion = 1154 µA/µm was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 µA/µm for Ioff = 100 nA/µm at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective “dual” embedded stressor.
{"title":"Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS","authors":"M. Nishikawa, K. Okabe, K. Ikeda, N. Tamura, H. Maekawa, M. Umeyama, H. Kurata, M. Kase, K. Hashimoto","doi":"10.1109/VTSA.2009.5159276","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159276","url":null,"abstract":"We have developed a device integration scheme for embedded silicon carbon (Si:C) SD structures induced by the solid phase epitaxy (SPE) technique. Our integration scheme comprises a combination of three key processes: carbon ion implantation (I/I) with Ge pre-amorphization implantation (PAI), sRTA and LSA. The guideline of our scheme is as follows. First, carbon I/I with Ge PAI plays large roll in this scheme since we can independently control both damage and stressor. Second, Ge PAI prior to carbon I/I is also performed to realize a steep carbon profile. Third, the embedded Si:C is required to be positioned beneath the Rp of n+dopant to maximally utilize the low resistance deep SD I/I region. Finally, optimizing thermal budget enables us to suppress both carbon clustering and residual defects induced by Ge PAI without a degradation of Vth-rolloff characteristics and a strain relaxation in embedded SiGe (eSiGe) in PMOSFETs. By using this scheme, we have controlled both parasitic resistance and junction leakage current simultaneously. In addition, UV-Raman spectroscopy and HR-XRD clarified the achievement of more than 1 at% effective substitutional carbon concentration by this scheme. Consequently, a 5.1% improvement in Ion of NMOSFETs for Ioff = 100 nA/µm at Vd = 1.0 V and Ion = 1154 µA/µm was obtained. For PMOSFETs, thanks to an optimized annealing process, strain relaxation in eSiGe was avoided, and thus Ion = 818 µA/µm for Ioff = 100 nA/µm at Vdd = 1.0 V, was obtained. We have successfully demonstrated the CMOS integration with a cost-effective “dual” embedded stressor.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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