Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159303
R. Huang, P. W. Liu, E. C. Liu, W. Chiang, S. Tsai, J. Tsai, T. Shen, C. Tsai, C. Tsai, G. H. Ma
In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In addition, the optimized integration scheme can reduce NMOS extension resistance. The main cause is that post e-SiGe clean processes would loss the extension dopant and increases the extension resistance. We successfully reduce the NMOS total resistance 22% compared to control without compromise PMOS device performance.
{"title":"Sub-32nm CMOS technology enhancement for low power applications","authors":"R. Huang, P. W. Liu, E. C. Liu, W. Chiang, S. Tsai, J. Tsai, T. Shen, C. Tsai, C. Tsai, G. H. Ma","doi":"10.1109/VTSA.2009.5159303","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159303","url":null,"abstract":"In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In addition, the optimized integration scheme can reduce NMOS extension resistance. The main cause is that post e-SiGe clean processes would loss the extension dopant and increases the extension resistance. We successfully reduce the NMOS total resistance 22% compared to control without compromise PMOS device performance.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115071149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159272
J. Lorenz, C. Kampen, A. Burenkov, T. Fuhner
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.
{"title":"Impact of lithography variations on advanced CMOS devices","authors":"J. Lorenz, C. Kampen, A. Burenkov, T. Fuhner","doi":"10.1109/VTSA.2009.5159272","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159272","url":null,"abstract":"Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159311
Y. Hsiao, H. Lue, K. Hsieh, Rich Liu, Chih-Yuan Lu
The “junction-free” charge-trapping NAND Flash [1,2] is studied extensively. Simulation results show that the junction-free NAND Flash is scalable beyond 15 nm node (half pitch) with reasonable DC characteristics, while the conventional “with-junction” NAND device shows much worse short-channel effect. Simulation results show that lower p-well doping and smaller space (S) between the WL's are two key factors to enable the higher performance of junction-free NAND device. For the first time, we point out that the parameters of the region under the space (S) such as interface traps (Dit), parasitic trapped charge, and local p-well doping have strong impact on cell characteristics. Experimental results on junction-free BE-SONOS device showed some discrepancy with the simulation that may be due to non-ideal factors under the space. Finally, the feasibility of junction-free device on SOI for the future 3D NAND Flash is also examined.
{"title":"Modeling and scaling evaluation of junction-free charge-trapping NAND flash devices","authors":"Y. Hsiao, H. Lue, K. Hsieh, Rich Liu, Chih-Yuan Lu","doi":"10.1109/VTSA.2009.5159311","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159311","url":null,"abstract":"The “junction-free” charge-trapping NAND Flash [1,2] is studied extensively. Simulation results show that the junction-free NAND Flash is scalable beyond 15 nm node (half pitch) with reasonable DC characteristics, while the conventional “with-junction” NAND device shows much worse short-channel effect. Simulation results show that lower p-well doping and smaller space (S) between the WL's are two key factors to enable the higher performance of junction-free NAND device. For the first time, we point out that the parameters of the region under the space (S) such as interface traps (Dit), parasitic trapped charge, and local p-well doping have strong impact on cell characteristics. Experimental results on junction-free BE-SONOS device showed some discrepancy with the simulation that may be due to non-ideal factors under the space. Finally, the feasibility of junction-free device on SOI for the future 3D NAND Flash is also examined.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159269
M. Hara, H. Aoki, T. Masuzumi, D. Watanabe, C. Kimura, T. Sugino
An effective inhibition with very thin layer is required for Cu/Low-K interconnection of next generation devices. We have achieved an effective suppression of Cu oxidation using adenine as an environmentally friendly material. By using electrochemical measurements, we find that the adenine layer can inhibit Cu oxidation by forming the very thin layer compared with Benzotriazol (BTA) as a conventional Cu inhibitor.
{"title":"Properties of very thin adenine layer with high inhibition for 32nm node Cu/Low-K interconnection","authors":"M. Hara, H. Aoki, T. Masuzumi, D. Watanabe, C. Kimura, T. Sugino","doi":"10.1109/VTSA.2009.5159269","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159269","url":null,"abstract":"An effective inhibition with very thin layer is required for Cu/Low-K interconnection of next generation devices. We have achieved an effective suppression of Cu oxidation using adenine as an environmentally friendly material. By using electrochemical measurements, we find that the adenine layer can inhibit Cu oxidation by forming the very thin layer compared with Benzotriazol (BTA) as a conventional Cu inhibitor.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159284
Y. Yeo
Recent developments in Impact Ionization Transistors (I-MOS) will be discussed here, including strained impact ionization transistors realized on the nanowire or multiple-gate device architecture. I-MOS devices achieve excellent subthreshold swings well below 5 mV/decade at room temperature. Techniques for enhancing impact ionization rate and reducing the breakdown voltage VBD for device performance improvement will be discussed. Challenges faced by I-MOS will be highlighted. Some challenges may be addressed through the strain and materials engineering. Limitations of the I-MOS will also be discussed.
{"title":"Realizing steep subthreshold swing with Impact Ionization Transistors","authors":"Y. Yeo","doi":"10.1109/VTSA.2009.5159284","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159284","url":null,"abstract":"Recent developments in Impact Ionization Transistors (I-MOS) will be discussed here, including strained impact ionization transistors realized on the nanowire or multiple-gate device architecture. I-MOS devices achieve excellent subthreshold swings well below 5 mV/decade at room temperature. Techniques for enhancing impact ionization rate and reducing the breakdown voltage VBD for device performance improvement will be discussed. Challenges faced by I-MOS will be highlighted. Some challenges may be addressed through the strain and materials engineering. Limitations of the I-MOS will also be discussed.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133645929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159323
Cindy Wang, Josephine B. Chang, Chung-Hsun Lin, Arvind Kumar, A. Gehring, Jin Cho, A. Majumdar, A. Bryant, Z. Ren, Kevin K. H. Chan, T. Kanarsky, Xinlin Wang, O. Dokumaci, M. Guillorn, M. Khater, Qingyun Yang, Xi Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Ying Zhang, Dae-gyu Park, C. Ouyang, W. Haensch
The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.
{"title":"FinFET resistance mitigation through design and process optimization","authors":"Cindy Wang, Josephine B. Chang, Chung-Hsun Lin, Arvind Kumar, A. Gehring, Jin Cho, A. Majumdar, A. Bryant, Z. Ren, Kevin K. H. Chan, T. Kanarsky, Xinlin Wang, O. Dokumaci, M. Guillorn, M. Khater, Qingyun Yang, Xi Li, M. Naeem, J. Holt, Y. Moon, J. King, J. Yates, Ying Zhang, Dae-gyu Park, C. Ouyang, W. Haensch","doi":"10.1109/VTSA.2009.5159323","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159323","url":null,"abstract":"The intrinsic FinFET device structure can provide an estimated 10–20% reduction in delay relative to planar FETs at the 22nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall device design optimization. Using FinFETs built at 45nm node dimensions, we have demonstrated FinFETs with an NFET/PFET external resistance of 230/350 Ω-um.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115388662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159330
H. Chin, Xinke Liu, L. Tan, Y. Yeo
We report the first demonstration of a surface channel inversiontype In0.53Ga0.47As n-MOSFET featuring gold-free palladium-germanium (PdGe) ohmic contacts and self-aligned S/D formed by silicon and phosphorus co-implantation. A gate stack comprising TaN/HfAlO/In0.53Ga0.47As is also featured. Excellent transistor output characteristics with high drain current on/off ratio of 104, high peak electron mobility of 1420 cm2/Vs and peak transconductance of 142 mS/mm at gate length of 2 µm were demonstrated. In addition, the integration of low resistance PdGe ohmic contacts on In0.53Ga0.47As alleviates contamination concerns associated with the common use of gold-based contacts on In0.53Ga0.47As.
{"title":"Inversion-type surface channel In0.53]Ga{in0.47As metal-oxide-semiconductor field-effect transistors with metal-gate/high-k dielectric stack and CMOS-compatible PdGe contacts","authors":"H. Chin, Xinke Liu, L. Tan, Y. Yeo","doi":"10.1109/VTSA.2009.5159330","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159330","url":null,"abstract":"We report the first demonstration of a surface channel inversiontype In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET featuring gold-free palladium-germanium (PdGe) ohmic contacts and self-aligned S/D formed by silicon and phosphorus co-implantation. A gate stack comprising TaN/HfAlO/In<inf>0.53</inf>Ga<inf>0.47</inf>As is also featured. Excellent transistor output characteristics with high drain current on/off ratio of 10<sup>4</sup>, high peak electron mobility of 1420 cm<sup>2</sup>/Vs and peak transconductance of 142 mS/mm at gate length of 2 µm were demonstrated. In addition, the integration of low resistance PdGe ohmic contacts on In<inf>0.53</inf>Ga<inf>0.47</inf>As alleviates contamination concerns associated with the common use of gold-based contacts on In<inf>0.53</inf>Ga<inf>0.47</inf>As.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115146984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159293
C. Young, G. Bersuker, P. Khanal, C. Kang, J. Huang, C. Park, P. Kirsch, H. Tseng, R. Jammy
SILC analysis is a powerful tool for the assessment of breakdown characteristics of high-κ devices. By applying the SILC analysis during high field stress, we determined that the degradation mechanism for LaOx capped devices was drastically different as compared to the conventional Hf-based gate stacks. The La atoms diffused into the interfacial layer disrupting the SiO2 structure which may affect the reliability of the La-doped stacks. On the other hand, similar analysis applied to the stacks with the Ru-Al bi-layer gate electrode demonstrated that the Al-contained stacks were similar to that of the baseline samples indicating that Al atoms, which preferentially substitute for Si in SiO2, did not generate defects contributing to SILC.
{"title":"Reliability assessment of low |Vt| metal high-κ gate stacks for high performance applications","authors":"C. Young, G. Bersuker, P. Khanal, C. Kang, J. Huang, C. Park, P. Kirsch, H. Tseng, R. Jammy","doi":"10.1109/VTSA.2009.5159293","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159293","url":null,"abstract":"SILC analysis is a powerful tool for the assessment of breakdown characteristics of high-κ devices. By applying the SILC analysis during high field stress, we determined that the degradation mechanism for LaOx capped devices was drastically different as compared to the conventional Hf-based gate stacks. The La atoms diffused into the interfacial layer disrupting the SiO2 structure which may affect the reliability of the La-doped stacks. On the other hand, similar analysis applied to the stacks with the Ru-Al bi-layer gate electrode demonstrated that the Al-contained stacks were similar to that of the baseline samples indicating that Al atoms, which preferentially substitute for Si in SiO2, did not generate defects contributing to SILC.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123877243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159309
K. Ronse, E. Hendrickx, M. Goethals, R. Jonckheere, G. Vandenberghe
In this paper, the experiences on full field EUVL lithography are reviewed. Besides the imaging performance of the EUV ADT at IMEC, also the progress in resists and reticles are discussed and compared to the production requirements for EUV lithography.
{"title":"Status and challenges of extreme-UV lithography","authors":"K. Ronse, E. Hendrickx, M. Goethals, R. Jonckheere, G. Vandenberghe","doi":"10.1109/VTSA.2009.5159309","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159309","url":null,"abstract":"In this paper, the experiences on full field EUVL lithography are reviewed. Besides the imaging performance of the EUV ADT at IMEC, also the progress in resists and reticles are discussed and compared to the production requirements for EUV lithography.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120830471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159274
Jungwoo Oh, P. Majhi, R. Jammy, R. Joe, A. Dip, T. Sugawara, Y. Akasaka, T. Kaitsuka, T. Arikado, M. Tomoyasu
We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO2 high-k gate dielectrics exhibited low C-V hysteresis (≪10 mV), interface trap density (7.5×1010), and gate leakage current (∼10−2A/cm2 at an EOT of 13.4Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of SiGe channels, which are major causes of the high off-state current of small bandgap energy SiGe pMOSFETs, by improving gate control over the channel.
{"title":"Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si Cap and high-k metal gate stacks","authors":"Jungwoo Oh, P. Majhi, R. Jammy, R. Joe, A. Dip, T. Sugawara, Y. Akasaka, T. Kaitsuka, T. Arikado, M. Tomoyasu","doi":"10.1109/VTSA.2009.5159274","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159274","url":null,"abstract":"We have demonstrated high mobility pMOSFETs on high quality epitaxial SiGe films selectively grown on Si (100) substrates. With a Si cap processed on SiGe channels, HfSiO2 high-k gate dielectrics exhibited low C-V hysteresis (≪10 mV), interface trap density (7.5×1010), and gate leakage current (∼10−2A/cm2 at an EOT of 13.4Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of SiGe channels, which are major causes of the high off-state current of small bandgap energy SiGe pMOSFETs, by improving gate control over the channel.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123690596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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