Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159287
L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans
This paper overviews integration challenges of low-VT gate-first CMOS featuring one metal gate electrode and one host dielectric with Al2O3 and La2O3 cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low VT enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.
{"title":"Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low VT and high performance","authors":"L. Ragnarsson, T. Schram, E. Rohr, F. Sebaai, P. Kelkar, M. Wada, T. Kauerauf, M. Aoulaiche, M. Cho, S. Kubicek, A. Lauwers, T. Hoffmann, P. Absil, S. Biesemans","doi":"10.1109/VTSA.2009.5159287","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159287","url":null,"abstract":"This paper overviews integration challenges of low-V<inf>T</inf> gate-first CMOS featuring one metal gate electrode and one host dielectric with Al<inf>2</inf>O<inf>3</inf> and La<inf>2</inf>O<inf>3</inf> cap-dielectrics for pMOS and nMOS respectively. The advantages and disadvantages of employed low EOT low V<inf>T</inf> enabling technologies are compared with respect to processing simplicity as well as device performance and reliability. The latest state-of-the art SMDD device results are reported.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126604127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159310
K. Parat
NAND Flash cell has scaled by ≫l000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.
{"title":"Recent developments in NAND flash scaling","authors":"K. Parat","doi":"10.1109/VTSA.2009.5159310","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159310","url":null,"abstract":"NAND Flash cell has scaled by ≫l000X in area since its inception over 2 decades ago. There are, however, several scaling challenges that need to be overcome to continue scaling below the 3X node. Many evolutionary and revolutionary approaches, such as high-K inter-poly-dielectric (IPD), engineered tunnel barriers, trap based charge storage devices, as well as 3-D structures are being pursued to overcome these scaling challenges. The paper will discuss some of these challenges and related developments.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128054239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159273
S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima
Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.
通过三维应力模拟和演示，研究了 nFET 沟道宽度上的顶切拉伸 SiN 应力衬垫和大马士革栅极（栅极-最后）工艺组合所引起的局部沟道应力行为。研究发现，去除假栅极会增强栅极长度上的高拉伸沟道应力，尤其是在 STI 旁的沟道边缘。因此，具有窄沟道宽度的大马士革栅 nFET 的驱动能力得到了增强。通过大马士革栅极技术的应力增强效应，在 Ioff = 100 nA/um、Vdd = 1.0 V 和 0.3 um 沟道宽度条件下实现了 1430 uA/um 的高驱动电流。
{"title":"Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner","authors":"S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima","doi":"10.1109/VTSA.2009.5159273","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159273","url":null,"abstract":"Local channel stress behaviors induced by the combination of top-cut tensile SiN stress liner and damascene-gate (gate-last) process on the channel width for nFETs are investigated by using 3D stress simulations and demonstrations. It is found that the dummy-gate removal enhances high tensile channel stress along the gate length, especially at the edge of the channel beside the STI. Therefore, drivability enhancement is performed for damascene-gate nFETs with narrow channel width. High-drive current of 1430 uA/um at Ioff = 100 nA/um, Vdd = 1.0 V and the channel width of 0.3 um is achieved by the stress enhancement effects of the damascene-gate technology.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127470388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159324
D. Grogg, A. Ionescu
This paper reports the low power operation of Vibrating Body Field Effect Transistors as active resonators for communication applications. For the first time we report active resonators operating at 2MHz and 20MHz with power consumption less than 100µW and Quality factors in the order of 3000. This performance opens new applications of devices for wireless sensor networks.
{"title":"Sub-100µW low power operation of Vibrating Body FETs","authors":"D. Grogg, A. Ionescu","doi":"10.1109/VTSA.2009.5159324","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159324","url":null,"abstract":"This paper reports the low power operation of Vibrating Body Field Effect Transistors as active resonators for communication applications. For the first time we report active resonators operating at 2MHz and 20MHz with power consumption less than 100µW and Quality factors in the order of 3000. This performance opens new applications of devices for wireless sensor networks.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129657530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159299
Lan Wei, F. Boeuf, T. Skotnicki, H. Wong
In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.
{"title":"CMOS technology roadmap projection including parasitic effects","authors":"Lan Wei, F. Boeuf, T. Skotnicki, H. Wong","doi":"10.1109/VTSA.2009.5159299","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159299","url":null,"abstract":"In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159290
C. Park, J. Yang, M. Hussain, C. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. Kirsch, B. H. Lee, H. Tseng, R. Jammy
This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.
{"title":"La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application","authors":"C. Park, J. Yang, M. Hussain, C. Kang, J. Huang, P. Sivasubramani, C. Park, K. Tateiwa, Y. Harada, J. Barnett, C. Melvin, G. Bersuker, P. Kirsch, B. H. Lee, H. Tseng, R. Jammy","doi":"10.1109/VTSA.2009.5159290","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159290","url":null,"abstract":"This paper presents results on nMOSFETs with the La-doped high-k/metal gate stack to see its suitability for sub-32nm LSTP and HP applications. The 32nm gate length transistors exhibit an excellent Ion-Ioff characteristic, and the PBTI results meet the 32nm technology node requirement. Furthermore, for the first time, Vt variation in the La-doped high-k/metal gate stack devices is investigated. The results suggest that employing the metal electrode suppresses Vt variability while no additional parameter fluctuations due to La-doping of the high-k dielectric were observed.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134079693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159315
M. Collonge, M. Vinet, M. Ribeiro, J. Pedini, B. Previtali, T. Ernst, S. Bécu, G. Ghibaudo
For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130µJ/m2 are required as well as sub-2.3N/m doubly clamped gate. Experimentally a 0.2N/m suspended silicon nanowire was processed, opening perspectives for device downscaling.
首次提出了累加型悬栅MOSFET的解析模型。对于非常低的功率工作，栅极和栅极氧化物的粘附能需要低至130µJ/m2，以及低于2.3 n /m的双夹紧栅极。实验处理了0.2N/m的悬浮硅纳米线，为器件的缩小尺寸开辟了前景。
{"title":"Analytical modeling of Accumulation-Mode Suspended-Gate MOSFET and process challenges for very low operating power devices","authors":"M. Collonge, M. Vinet, M. Ribeiro, J. Pedini, B. Previtali, T. Ernst, S. Bécu, G. Ghibaudo","doi":"10.1109/VTSA.2009.5159315","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159315","url":null,"abstract":"For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130µJ/m2 are required as well as sub-2.3N/m doubly clamped gate. Experimentally a 0.2N/m suspended silicon nanowire was processed, opening perspectives for device downscaling.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116063674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159312
Jemin Park, C. Hu
Gate-last metal-gate/high-k technology will allow MOSFET scaling to unprecedented levels. When the gate length is small, the dominant capacitance in the MOSFET is the gate to contact-plug capacitance. This is especially so with SAC (self-aligned contact) technology popular with high density memories. This papers proposes a compact SAC gate-last air-spacer structure that yield small size, high speed, and low switching energy. The improvement over the conventional SAC device increases dramatically with scaling.
{"title":"Gate last MOSFET with air spacer and self-aligned contacts for dense memories","authors":"Jemin Park, C. Hu","doi":"10.1109/VTSA.2009.5159312","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159312","url":null,"abstract":"Gate-last metal-gate/high-k technology will allow MOSFET scaling to unprecedented levels. When the gate length is small, the dominant capacitance in the MOSFET is the gate to contact-plug capacitance. This is especially so with SAC (self-aligned contact) technology popular with high density memories. This papers proposes a compact SAC gate-last air-spacer structure that yield small size, high speed, and low switching energy. The improvement over the conventional SAC device increases dramatically with scaling.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121477063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159302
J. Yau, Jin Cai, L. Shi, R. Dennard, Arvind Kumar, Katherine L. Sactlger, A. Reznicek, P. Solomon, Q. Ouyang, S. Koester, W. Haensch
We demonstrate, for the first time, modulation of power-performance of a ring oscillator fabricated on thin-BOX (buried oxide) FD (fully-depleted) SOI using independent backgate controls for nFET and pFET. The thin BOX facilitates an effective modulation of ring characteristics with small (1–2V) independent backgate voltages. Leakage current per stage can be reduced by more than 100× with 30% increase of inverter delay. In addition, the inverter delay can be improved by 15% with 2× increase of the stand-by current. Compatible with conventional CMOS process, our results suggest the baekgate technology, an additional knob for power/performance optimization and variability control, is attractive for continued CMOS scaling.
{"title":"FDSOI CMOS with dual backgate control for performance and power modulation","authors":"J. Yau, Jin Cai, L. Shi, R. Dennard, Arvind Kumar, Katherine L. Sactlger, A. Reznicek, P. Solomon, Q. Ouyang, S. Koester, W. Haensch","doi":"10.1109/VTSA.2009.5159302","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159302","url":null,"abstract":"We demonstrate, for the first time, modulation of power-performance of a ring oscillator fabricated on thin-BOX (buried oxide) FD (fully-depleted) SOI using independent backgate controls for nFET and pFET. The thin BOX facilitates an effective modulation of ring characteristics with small (1–2V) independent backgate voltages. Leakage current per stage can be reduced by more than 100× with 30% increase of inverter delay. In addition, the inverter delay can be improved by 15% with 2× increase of the stand-by current. Compatible with conventional CMOS process, our results suggest the baekgate technology, an additional knob for power/performance optimization and variability control, is attractive for continued CMOS scaling.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131377798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159327
H. Adhikari, H. Harris, Casey Smith, Ji-Woon Yang, B. Coss, S. Parthasarathy, B. Nguyen, P. Patruno, T. Krishnamohan, I. Cayrefourcq, P. Majhi, R. Jammy
Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.
{"title":"High mobility SiGe shell-Si core omega gate pFETS","authors":"H. Adhikari, H. Harris, Casey Smith, Ji-Woon Yang, B. Coss, S. Parthasarathy, B. Nguyen, P. Patruno, T. Krishnamohan, I. Cayrefourcq, P. Majhi, R. Jammy","doi":"10.1109/VTSA.2009.5159327","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159327","url":null,"abstract":"Omega gate type pFETs with SiGe shell-Si core are demonstrated that show 30% mobility enhancement for (110) oriented fins and 46% mobility enhancement for (100) oriented fins compared to Si omega gate devices. Performance improvement is demonstrated because of higher mobility and inherent epitaxial strain, while the external resistance in the two SiGe and Si omega FETs is comparable. Performance can further be improved by uniaxial compressive stress.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124470010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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