Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159281
Yu-Sheng Chen, T. Wu, P. Tzeng, Pang-Shiu Chen, Heng-Yuan Lee, Cha-Hsin Lin, Frederick T. Chen, M. Tsai
A forming-free resistive memory of TiN/Ti/HfO2/TiN with a thin HfO2 film is demonstrated. The as-fabricated device can be operated without additional forming step to initiate the operation. This device with bipolar operation mode shows high speed (∼ 10 ns), robust endurance (≫ 106 times), good data retention (10-year lifetime), enough resistance ratio, and low power consumption. The simple structure and capability of multi-level operation demonstrate RRAM as a high-density memory in the near future.
{"title":"Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation","authors":"Yu-Sheng Chen, T. Wu, P. Tzeng, Pang-Shiu Chen, Heng-Yuan Lee, Cha-Hsin Lin, Frederick T. Chen, M. Tsai","doi":"10.1109/VTSA.2009.5159281","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159281","url":null,"abstract":"A forming-free resistive memory of TiN/Ti/HfO2/TiN with a thin HfO2 film is demonstrated. The as-fabricated device can be operated without additional forming step to initiate the operation. This device with bipolar operation mode shows high speed (∼ 10 ns), robust endurance (≫ 106 times), good data retention (10-year lifetime), enough resistance ratio, and low power consumption. The simple structure and capability of multi-level operation demonstrate RRAM as a high-density memory in the near future.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115140588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159304
T. Poiroux, M. Vinet, F. Nemouchi, V. Carron, Y. Morand, B. Previtali, S. Descombes, L. Tosti, O. Cueto, L. Baud, V. Balan, M. Rivoire, S. Deleonibus, O. Faynot
We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345µA/µm and Ioff=30nA/µm at −1V for a 50nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow specifific contact resistivities as low as 0.1 Ω.µm2.
{"title":"Highly performant FDSOI pMOSFETs with metallic source/drain","authors":"T. Poiroux, M. Vinet, F. Nemouchi, V. Carron, Y. Morand, B. Previtali, S. Descombes, L. Tosti, O. Cueto, L. Baud, V. Balan, M. Rivoire, S. Deleonibus, O. Faynot","doi":"10.1109/VTSA.2009.5159304","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159304","url":null,"abstract":"We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345µA/µm and Ioff=30nA/µm at −1V for a 50nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow specifific contact resistivities as low as 0.1 Ω.µm<sup>2</sup>.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132763629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159316
C. Shen, L. T. Yang, E. Toh, C. Heng, G. Samudra, Y. Yeo
A new non-local algorithm for accurately calculating the band-to-band tunneling current suitable for TCAD semiconductor simulators is proposed in this abstract. The proposed algorithm captures the essential physics of multi-dimensional tunneling in a 2D structure, and is designed to be robust and to achieve independence on the mesh grid. The new algorithm enables accurate modeling of T-FET and investigation of its device physics. Application on T-FET is demonstrated. The physical origin of the saturation of Id-Vd curve of T-FET is analyzed and clarified for the first time.
{"title":"A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET","authors":"C. Shen, L. T. Yang, E. Toh, C. Heng, G. Samudra, Y. Yeo","doi":"10.1109/VTSA.2009.5159316","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159316","url":null,"abstract":"A new non-local algorithm for accurately calculating the band-to-band tunneling current suitable for TCAD semiconductor simulators is proposed in this abstract. The proposed algorithm captures the essential physics of multi-dimensional tunneling in a 2D structure, and is designed to be robust and to achieve independence on the mesh grid. The new algorithm enables accurate modeling of T-FET and investigation of its device physics. Application on T-FET is demonstrated. The physical origin of the saturation of Id-Vd curve of T-FET is analyzed and clarified for the first time.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115825939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159296
Y. Nara
Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.
{"title":"Scaling challenges of MOSFET for 32nm node and beyond","authors":"Y. Nara","doi":"10.1109/VTSA.2009.5159296","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159296","url":null,"abstract":"Scaling challenges for MOSFET fabrication process with design rule of 32nm and below will be reviewed. This paper will especially focus on the scaling issues of conventional planar bulk CMOS technology and discuss about multiple stress engineering, junction engineering and high-k/metal gate stack as key technology boosters to enhance CMOS performance with scaled dimensions.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123422008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159300
B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, L. Witters, S. Biesemans, T. Hoffman
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached at the same time. VT mismatch smaller than 3mV.µm is obtained for narrow (10nm) fins. Reduced speed sensitivity to gate pitch scaling and invertor delay reduced below 10 ps will be demonstrated.
{"title":"The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET","authors":"B. Parvais, A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, A. De Keersgieter, T. Chiarella, C. Kerner, L. Witters, S. Biesemans, T. Hoffman","doi":"10.1109/VTSA.2009.5159300","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159300","url":null,"abstract":"Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached at the same time. VT mismatch smaller than 3mV.µm is obtained for narrow (10nm) fins. Reduced speed sensitivity to gate pitch scaling and invertor delay reduced below 10 ps will be demonstrated.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123827625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159267
K. Uchida, M. Saitoh
This paper reviews the carrier transport mechanisms and stress engineering in advanced nanoscale MOSFETs. First, carrier transport in bulk (100) and (110) MOSFETs is reviewed. Sub-band structure engineering to enhance mobility as well as ballistic current is also examined.
{"title":"Carrier transport and stress engineering in advanced nanoscale MOS transistors","authors":"K. Uchida, M. Saitoh","doi":"10.1109/VTSA.2009.5159267","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159267","url":null,"abstract":"This paper reviews the carrier transport mechanisms and stress engineering in advanced nanoscale MOSFETs. First, carrier transport in bulk (100) and (110) MOSFETs is reviewed. Sub-band structure engineering to enhance mobility as well as ballistic current is also examined.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126582774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated configuration, the function of threshold voltage modulation is investigated.
{"title":"A novel double-gated nanowire TFT and investigation of its size dependency","authors":"Wei-Chen Chen, Chuan-Ding Lin, Horng-Chih Lin, Tiao-Yuan Huang","doi":"10.1109/VTSA.2009.5159320","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159320","url":null,"abstract":"A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated configuration, the function of threshold voltage modulation is investigated.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133896346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, SB-NWTs are comprehensively studied in comparison with SNWTs. The EPs of SB-NWTs are shown to be unpromising and Rlin-SB-NWTs is found to be unexpectedly large, which can both be attributed to SB impact. Then, BL and MR are studied and the improvement of SB-NWTs is investigated. It is found that the SS of SB-NWTs cannot be superior to that of SNWTs and unexpected DIBL/FoM degradation may be induced. In addition, Rlin-SB-NWTs is found to be always worse than Rlin-SNWTs if LSDE of SNWTs is designed to be adequately short (e.g. LSDE≪10nm). The results show that the replacement of SNWTs by SB-NWTs, even the MSB-NWTs and DSSB-NWTs cannot be promising.
{"title":"A comparison study of Silicon Nanowire Transistor with Schottky-Barrier source/drain and doped source/drain","authors":"Zhaoyi Kang, Liangliang Zhang, Runsheng Wang, Ru Huang","doi":"10.1109/VTSA.2009.5159326","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159326","url":null,"abstract":"In this work, SB-NWTs are comprehensively studied in comparison with SNWTs. The EPs of SB-NWTs are shown to be unpromising and Rlin-SB-NWTs is found to be unexpectedly large, which can both be attributed to SB impact. Then, BL and MR are studied and the improvement of SB-NWTs is investigated. It is found that the SS of SB-NWTs cannot be superior to that of SNWTs and unexpected DIBL/FoM degradation may be induced. In addition, Rlin-SB-NWTs is found to be always worse than Rlin-SNWTs if LSDE of SNWTs is designed to be adequately short (e.g. LSDE≪10nm). The results show that the replacement of SNWTs by SB-NWTs, even the MSB-NWTs and DSSB-NWTs cannot be promising.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132485591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159321
Jenny Hu, X. Guan, D. Choi, J. Harris, K. Saraswat, H. Wong
High mobility III–V compounds is a strong contender for extending high performance logic beyond the 22 nm technology node [1–3]. However, demonstrations of exceptional III–V performance required device footprints on the µm-scale despite nm-scale gate lengths, in order to avoid source/drain shorting during contact alloying. The scaling of III–V FETs is severely limited by the unacceptably large lateral diffusion of the multilayer alloyed structures typically used for ohmic contacts [4]. In our recent work, we introduced a novel non-alloyed, highly scalable contact structure through the use of Al as a low workfunction metal on an unpinned Fermi level [5]. We use GaAs as a baseline III–V material, where the developed contact techniques can be extended to InGaAs and InSb, materials which are more technologically important [6]. In this work, we explain in detail the unpinning mechanisms and the rationale for the material selection. We demonstrate the same method can be applied to a variety of metals, Y, Er, Al, Ti, W, and Pt, providing much flexibility in the design of an ideal source/drain contact for III–V HEMTs/MOSFETs and Schottky Barrier FETs.
高迁移率III-V化合物是将高性能逻辑扩展到22纳米技术节点以外的有力竞争者[1-3]。然而，尽管栅极长度为纳米级，但优异的III-V性能的演示需要微米级的器件封装，以避免接触合金过程中的源极/漏极短路。通常用于欧姆接触的多层合金结构的横向扩散大得令人无法接受，这严重限制了III-V型场效应管的缩放[4]。在我们最近的工作中，我们通过使用Al作为非固定费米能级上的低工作功能金属，引入了一种新型的非合金，高度可扩展的接触结构[5]。我们使用砷化镓作为基准III-V材料，其中开发的接触技术可以扩展到InGaAs和InSb，这些材料在技术上更重要[6]。在这项工作中，我们详细解释了解钉机制和材料选择的基本原理。我们证明了相同的方法可以应用于各种金属，Y, Er, Al, Ti, W和Pt，为III-V HEMTs/ mosfet和肖特基势垒fet的理想源极/漏极触点设计提供了很大的灵活性。
{"title":"Fermi level depinning for the design of III–V FET source/drain contacts","authors":"Jenny Hu, X. Guan, D. Choi, J. Harris, K. Saraswat, H. Wong","doi":"10.1109/VTSA.2009.5159321","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159321","url":null,"abstract":"High mobility III–V compounds is a strong contender for extending high performance logic beyond the 22 nm technology node [1–3]. However, demonstrations of exceptional III–V performance required device footprints on the µm-scale despite nm-scale gate lengths, in order to avoid source/drain shorting during contact alloying. The scaling of III–V FETs is severely limited by the unacceptably large lateral diffusion of the multilayer alloyed structures typically used for ohmic contacts [4]. In our recent work, we introduced a novel non-alloyed, highly scalable contact structure through the use of Al as a low workfunction metal on an unpinned Fermi level [5]. We use GaAs as a baseline III–V material, where the developed contact techniques can be extended to InGaAs and InSb, materials which are more technologically important [6]. In this work, we explain in detail the unpinning mechanisms and the rationale for the material selection. We demonstrate the same method can be applied to a variety of metals, Y, Er, Al, Ti, W, and Pt, providing much flexibility in the design of an ideal source/drain contact for III–V HEMTs/MOSFETs and Schottky Barrier FETs.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122867907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159292
C.S. Liu, G. Boccardi, H.Y. Wang, C. Lin, J. Pétry, M. Muller, Z. Li, C. Zhao, C. Yu
Two SMSD gate first planar CMOS devices were demonstrated. Vtn/Vtp= +0.49V/−0.48V were achieved by adjusting TiN to p-like metal and As I/I on nMOS. This enables the equivalent +/−0.2V low Vt target of N22 fully depleted CMOS technologies. Vtn/Vtp= 0.52/− 0.55 were obtained by transforming PVD-TiN/Ti into n-like metal TiN/TiSix for nMOS and by Al I/I on TiN/Ti for pMOS. Al diffusion was facilitated by snowplow effect of TiSix formation on pMOS. As low as 7.3A EOT with decent Jg 6.4E-3 A/cm2 @1.1Vwas obtained.
{"title":"22nm CMOS approaches by PVD TiN or Ti-Silicide as metal gate","authors":"C.S. Liu, G. Boccardi, H.Y. Wang, C. Lin, J. Pétry, M. Muller, Z. Li, C. Zhao, C. Yu","doi":"10.1109/VTSA.2009.5159292","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159292","url":null,"abstract":"Two SMSD gate first planar CMOS devices were demonstrated. Vtn/Vtp= +0.49V/−0.48V were achieved by adjusting TiN to p-like metal and As I/I on nMOS. This enables the equivalent +/−0.2V low Vt target of N22 fully depleted CMOS technologies. Vtn/Vtp= 0.52/− 0.55 were obtained by transforming PVD-TiN/Ti into n-like metal TiN/TiSix for nMOS and by Al I/I on TiN/Ti for pMOS. Al diffusion was facilitated by snowplow effect of TiSix formation on pMOS. As low as 7.3A EOT with decent Jg 6.4E-3 A/cm2 @1.1Vwas obtained.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125642430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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