Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159285
J. Knoch
In recent years tunnel FETs (TFETs) have attracted a great deal of attention [1–9]. The reason for this is that TFETs potentially allow beating the 60mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an onstate performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.
{"title":"Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material","authors":"J. Knoch","doi":"10.1109/VTSA.2009.5159285","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159285","url":null,"abstract":"In recent years tunnel FETs (TFETs) have attracted a great deal of attention [1–9]. The reason for this is that TFETs potentially allow beating the 60mV/dec limit and thus eventually enable lowering the power consumption of ICs. However, TFETs usually exhibit an onstate performance inferior to a conventional MOSFET. Moreover, in order to obtain a superior off-state TFETs must exhibit subthreshold swings substantially smaller than 60mV/dec over several orders of magnitude in current. In the present paper the impact of device structure, dimensions and the choice of material on the performance of TFETs will be discussed. In particular, the use of heterostructures and one-dimensional nanowires will be analyzed in detail.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159318
S. Iyer
In many ways, three dimensional integration presents itself as a logical extension of planar monolithic integration - integration of additional function on the same die. Notwithstanding the remarkable advances in scaling we have witnessed over the last several decades, basic material limitations and lithography have slowed this trend down and the benefits of node to node migration need to be weighed against both technology development costs and complexity as well as the cost of design migration. Another consideration is die size which for high end applications such as high performance processors continues to increase well beyond the sweet spot dictated by yieldability, driven primarily by multiples cores and on-chip memory. Furthermore in such large die, long electrical paths cause significant delay and power draws. To address these limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way we design an SOC or ASIC today. This talk examines at the technology as it stands toady and the challenges going forward. These challenges include the development of fine pitch vertical interconnects and the degrees of integration they would permit. We will focus on the integration of three dimensional memory as the prototypical example of three dimensional integration and describe how these challenges are being met.
{"title":"The promise and implementation of three dimensional integration","authors":"S. Iyer","doi":"10.1109/VTSA.2009.5159318","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159318","url":null,"abstract":"In many ways, three dimensional integration presents itself as a logical extension of planar monolithic integration - integration of additional function on the same die. Notwithstanding the remarkable advances in scaling we have witnessed over the last several decades, basic material limitations and lithography have slowed this trend down and the benefits of node to node migration need to be weighed against both technology development costs and complexity as well as the cost of design migration. Another consideration is die size which for high end applications such as high performance processors continues to increase well beyond the sweet spot dictated by yieldability, driven primarily by multiples cores and on-chip memory. Furthermore in such large die, long electrical paths cause significant delay and power draws. To address these limitations, three dimensional integration must be viewed beyond a simplistic packaging paradigm but rather as extension of silicon integration in the third dimension i.e., the introduction of low resistance, low inductance vertical interconnects between multiple active silicon strata that are co-designed in much the same way we design an SOC or ASIC today. This talk examines at the technology as it stands toady and the challenges going forward. These challenges include the development of fine pitch vertical interconnects and the degrees of integration they would permit. We will focus on the integration of three dimensional memory as the prototypical example of three dimensional integration and describe how these challenges are being met.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125456090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159301
J. Kuo, W. P. Chen, P. Su
We have investigated the low frequency noise characteristics for uniaxial strained PMOSFETs. In the low |Vgst| regime, the 1/f noise is dominated by the carrier-number-fluctuations and the SId/Id2 is increased by the enhanced gm/Id for the strained device. Nevertheless, the SId/I}d2 of the strained device is almost the same as the unstrained one at a given gm/Id. Furthermore, with the application of uniaxial compressive strain, the attenuation length λ is reduced because of the increased out-on-plane effective mass and tunneling barrier height. The reduced λ may result in a smaller SVg. In the high |Vgst| regime, the 1/f noise is dominated by the mobility-fluctuations and the SId/Id2 is increased due to the larger Hooge parameter for the strained device.
{"title":"Investigation of low frequency noise in uniaxial strained PMOSFETs","authors":"J. Kuo, W. P. Chen, P. Su","doi":"10.1109/VTSA.2009.5159301","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159301","url":null,"abstract":"We have investigated the low frequency noise characteristics for uniaxial strained PMOSFETs. In the low |V<inf>gst</inf>| regime, the 1/f noise is dominated by the carrier-number-fluctuations and the S<inf>Id</inf>/<inf>Id</inf><sup>2</sup> is increased by the enhanced g<inf>m</inf>/I<inf>d</inf> for the strained device. Nevertheless, the S<inf>Id</inf>/I}<inf>d</inf><sup>2</sup> of the strained device is almost the same as the unstrained one at a given g<inf>m</inf>/I<inf>d</inf>. Furthermore, with the application of uniaxial compressive strain, the attenuation length λ is reduced because of the increased out-on-plane effective mass and tunneling barrier height. The reduced λ may result in a smaller S<inf>Vg</inf>. In the high |V<inf>gst</inf>| regime, the 1/f noise is dominated by the mobility-fluctuations and the S<inf>Id</inf>/I<inf>d</inf><sup>2</sup> is increased due to the larger Hooge parameter for the strained device.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124871924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159319
L. De Michielis, K. E. Moselund, D. Bouvet, P. Dobrosz, S. Olsen, A. O'Neill, L. Lattanzio, M. Najmzadeh, L. Selmi, A. Ionescu
We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa's and average values of hundreds of MPa's.
{"title":"Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs","authors":"L. De Michielis, K. E. Moselund, D. Bouvet, P. Dobrosz, S. Olsen, A. O'Neill, L. Lattanzio, M. Najmzadeh, L. Selmi, A. Ionescu","doi":"10.1109/VTSA.2009.5159319","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159319","url":null,"abstract":"We report for the first time the optimization of the channel lateral strain profile as a new technological booster for improved performance of multi-gate n-channel MOSFET. We find that quasi-uniform or flat-Gaussian-close-to-the-drain profiles are optimum for the Ion boosting of sub-50nm scaled MOSFETs, while the penalty on Ioff and subthreshold slope is minimum. The reported predictions use realistic lateral uniaxial strain profiles, with peaks up to few GPa's and average values of hundreds of MPa's.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159337
D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy
We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al2O3-Si3N4-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO2, HfSiO, Al2O3, Si3N4) and tunnel stack sequences (SiO2-high-k, SiO2-high-k-SiO2) are compared. New results are as follows: SiO2/Al2O3 (OA) BE-TO and SiO2/Si3N4/SiO2 (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO2-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.
我们首次展示了通过带工程隧道氧化物(BETO)改进的电荷阱闪光TaN-Al2O3-Si3N4-“隧道氧化物(TO)”- si mosfet的程序，擦除和耐久性。比较了几种高钾介质(HfO2、HfSiO、Al2O3、Si3N4)和隧道叠层(SiO2-high-k、SiO2-high-k- sio2)。新的结果如下:SiO2/Al2O3 (OA) BE-TO和SiO2/Si3N4/SiO2 (ONO) BE-TO ΔVth窗口比标准SiO2- to提高了300%。OA和ONO堆栈都能承受至少100K的P/E循环，保持窗口值在4V以上。结果与基于高k导价带偏移的模型一致。BE-TO的擦除效率提高，可以在不牺牲P/E窗口的情况下提高耐用性，因为P/E电压应力较低。这些大而持久的窗口有利于多级单元应用，并可能将TANOS闪存扩展到20nm节点以上。
{"title":"Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance","authors":"D. Gilmer, N. Goel, S. Verma, Hokyung Park, Chanro Park, G. Bersuker, P. Kirsch, K. Saraswat, R. Jammy","doi":"10.1109/VTSA.2009.5159337","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159337","url":null,"abstract":"We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al<inf>2</inf>O<inf>3</inf>-Si<inf>3</inf>N<inf>4</inf>-“Tunnel-oxide (TO)”-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO<inf>2</inf>, HfSiO, Al<inf>2</inf>O<inf>3</inf>, Si<inf>3</inf>N<inf>4</inf>) and tunnel stack sequences (SiO<inf>2</inf>-high-k, SiO<inf>2</inf>-high-k-SiO<inf>2</inf>) are compared. New results are as follows: SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (OA) BE-TO and SiO<inf>2</inf>/Si<inf>3</inf>N<inf>4</inf>/SiO<inf>2</inf> (ONO) BE-TO ΔVth windows improve ≫300% vs. standard SiO<inf>2</inf>-TO. Both OA and ONO stacks endure P/E cycles to at least 100K cycles maintaining a window ≫4V. Results are consistent with a model based on high-k conduction/valence band offsets. Increased erase efficiency for BE-TO enables improved endurance without sacrificing P/E window due to lower P/E voltage stressing. These large, enduring windows are favorable for multi-level cell application and may extend TANOS flash beyond the 20nm node.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130244138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159328
L. Chu, T. Lin, C. H. Lee, L. T. Tung, W. Lee, R. Chu, C. C. Chang, M. Hong, J. Kwo
Ultra-high vacuum (UHV)-deposited high Ga2O3(Gd2O3) was proved to passivate Ge effectively, as evidenced by comprehensive investigations including structural, chemical, and electrical analyses. The Ga2O3(Gd2O3)/Ge interface is revealed to be abrupt even being subjected to a 500°C anneal, a high κ value of 14.5, a low leakage current density of ∼10−9A/cm2 with a Fowler-Nordheim tunneling behavior, and well-behaved C-V characteristics are achieved. Furthermore, Ge self-aligned pMOSFETs with Al2O3/ Ga2O3(Gd2O3) as the gate dielectrics have demonstrated a high drain current and a peak transconductance up to 252mA/mm and 143mS/mm, respectively, of 1µm-gate length.
{"title":"Metal-oxide-semiconductor devices with UHV-Ga2O3(Gd2O3) on Ge(100)","authors":"L. Chu, T. Lin, C. H. Lee, L. T. Tung, W. Lee, R. Chu, C. C. Chang, M. Hong, J. Kwo","doi":"10.1109/VTSA.2009.5159328","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159328","url":null,"abstract":"Ultra-high vacuum (UHV)-deposited high Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) was proved to passivate Ge effectively, as evidenced by comprehensive investigations including structural, chemical, and electrical analyses. The Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>)/Ge interface is revealed to be abrupt even being subjected to a 500°C anneal, a high κ value of 14.5, a low leakage current density of ∼10<inf>−9</inf>A/cm<sup>2</sup> with a Fowler-Nordheim tunneling behavior, and well-behaved C-V characteristics are achieved. Furthermore, Ge self-aligned pMOSFETs with Al<inf>2</inf>O<inf>3</inf>/ Ga<inf>2</inf>O<inf>3</inf>(Gd<inf>2</inf>O<inf>3</inf>) as the gate dielectrics have demonstrated a high drain current and a peak transconductance up to 252mA/mm and 143mS/mm, respectively, of 1µm-gate length.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159314
D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, G. Ghibaudo
In this study, a new technique to extract the S/D series resistance (Rsd) from the total resistance versus transconductance gain plot Rtot(1/β) is proposed. The technique only requires the measurement of Id(Vgs)|Vgt and β, allowing fast and statistical analysis in an industrial context. Unlike the usual Rtot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for Rsd(Vgs) and the effective mobility reduction factor µeff(Vgt)/µeff(0).
{"title":"A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs","authors":"D. Fleury, A. Cros, G. Bidal, H. Brut, E. Josse, G. Ghibaudo","doi":"10.1109/VTSA.2009.5159314","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159314","url":null,"abstract":"In this study, a new technique to extract the S/D series resistance (R<inf>sd</inf>) from the total resistance versus transconductance gain plot R<inf>tot</inf>(1/β) is proposed. The technique only requires the measurement of I<inf>d</inf>(V<inf>gs</inf>)|<inf>Vgt</inf> and β, allowing fast and statistical analysis in an industrial context. Unlike the usual R<inf>tot</inf>(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R<inf>sd</inf>(V<inf>gs</inf>) and the effective mobility reduction factor µ<inf>eff</inf>(V<inf>gt</inf>)/µ<inf>eff</inf>(0).","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"577 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159333
H. Hsu, T. Liu, Chuan-Ding Lin, Chiu Kuo-Jung, Tiao-Yuan Huang, Horng-Chih Lin
Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and/or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.
{"title":"Tri-gated poly-Si nanowire SONOS devices","authors":"H. Hsu, T. Liu, Chuan-Ding Lin, Chiu Kuo-Jung, Tiao-Yuan Huang, Horng-Chih Lin","doi":"10.1109/VTSA.2009.5159333","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159333","url":null,"abstract":"Si nanowire (NW) SONOS devices have recently been demonstrated as a good candidate for high-density non-volatile memory application [1][2]. Owing to the high surface-to-volume ratio of the NW channel, the programming and erasing (P/E) operation of the device could be performed at a lower voltage and much faster speed over the planar counterpart [2]. However, the fabrication of NW devices typically requires advanced lithographic tools and/or complicated process flow. These are not compatible with the manufacturing of flat-panel products where the device feature size is generally several microns or larger. In this work, we propose a simple and cost-effective approach to integrate planar poly-Si thin-film transistors (TFTs) and tri-gated poly-Si NW SONOS devices without resorting to advanced lithographic tools. Greatly enhanced P/E speed with the use of NW structure is clearly demonstrated.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123318380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159295
H. Yu, S. Chang, M. Aoulaiche, B. Kaczer, P. Absil, C. Adelmann, T. Hoffmann, S. Biesemans, C. Wann, Y. Mii
The transistor VT tuning mechanism in metal-gate/high-k (MG/HK) gate stack doped with rare-earth elements (Dysprosium or Dy in this work) is studied in transistors fabricated by either a gate-first or a gate-last approach. Except the commonly believed interface dipole, this work provides additional evidence that the bulk trapping charges can also play an important role in determining the device VT for above-mentioned gate stacks. It is thus suggested that careful design of capping layer thickness as well as the thermal budget for intermixing the capping layer with host dielectrics are necessary to eliminate the impact from bulk trapping charges to the device performance.
{"title":"High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge?","authors":"H. Yu, S. Chang, M. Aoulaiche, B. Kaczer, P. Absil, C. Adelmann, T. Hoffmann, S. Biesemans, C. Wann, Y. Mii","doi":"10.1109/VTSA.2009.5159295","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159295","url":null,"abstract":"The transistor VT tuning mechanism in metal-gate/high-k (MG/HK) gate stack doped with rare-earth elements (Dysprosium or Dy in this work) is studied in transistors fabricated by either a gate-first or a gate-last approach. Except the commonly believed interface dipole, this work provides additional evidence that the bulk trapping charges can also play an important role in determining the device VT for above-mentioned gate stacks. It is thus suggested that careful design of capping layer thickness as well as the thermal budget for intermixing the capping layer with host dielectrics are necessary to eliminate the impact from bulk trapping charges to the device performance.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"7 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-27DOI: 10.1109/VTSA.2009.5159283
J. Rabaey
A large fraction of the average power dissipation of many modern multimedia components and mobile devices is spent in standby mode, scanning for potential input activity. Reducing the dissipation of the “always-on” components is essential to the realization of green devices. The common strategy is to duty-cycle the always-on components. While simple to implement, it comes at the expense of latency. A more effective approach that delivers both low standby-power and almost-zero latency is to exploit ultra low-power wake-up receivers. Combining innovative architectures with state-of-the-art CMOS and MEMS technologies, wake-up receivers have been built that consume less than 50 uW in on-mode. Their availability opens a whole new perspective on standby power management. On one end of the spectrum, they enable green devices to operate in a purely reactive mode, that is they are only turned on when input activity happens. On the other side, they allow for substantial improvements in existing communication protocols such as WiFi and Bluetooth. A number of examples will be presented in the talk. One important message that will emerge from the presentation however is that effective standby power management requires a system vision, and that the ad-hoc component-oriented approach of today will rarely be effective.
{"title":"The standby power challenge: Wake-up receivers to the rescue","authors":"J. Rabaey","doi":"10.1109/VTSA.2009.5159283","DOIUrl":"https://doi.org/10.1109/VTSA.2009.5159283","url":null,"abstract":"A large fraction of the average power dissipation of many modern multimedia components and mobile devices is spent in standby mode, scanning for potential input activity. Reducing the dissipation of the “always-on” components is essential to the realization of green devices. The common strategy is to duty-cycle the always-on components. While simple to implement, it comes at the expense of latency. A more effective approach that delivers both low standby-power and almost-zero latency is to exploit ultra low-power wake-up receivers. Combining innovative architectures with state-of-the-art CMOS and MEMS technologies, wake-up receivers have been built that consume less than 50 uW in on-mode. Their availability opens a whole new perspective on standby power management. On one end of the spectrum, they enable green devices to operate in a purely reactive mode, that is they are only turned on when input activity happens. On the other side, they allow for substantial improvements in existing communication protocols such as WiFi and Bluetooth. A number of examples will be presented in the talk. One important message that will emerge from the presentation however is that effective standby power management requires a system vision, and that the ad-hoc component-oriented approach of today will rarely be effective.","PeriodicalId":309622,"journal":{"name":"2009 International Symposium on VLSI Technology, Systems, and Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126683958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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