Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896945
K. Park, D. Shin, Jun S. Lee, M. Sunwoo
This paper presents a QPSK/16 QAM down stream receiver ASIC chip for LMDS (Local Multipoint Distribution Services) applications. The proposed LMDS chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE (Decision Feedback Equalizer) structure using CMA (Constant Modulus Algorithm). The symbol timing recovery uses the modified parabolic interpolator and the decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.
提出了一种适用于LMDS (Local Multipoint Distribution Services)应用的QPSK/16 QAM下行接收ASIC芯片。该LMDS芯片由盲均衡器、定时恢复块和载波恢复块组成。盲均衡器采用恒模算法的DFE(决策反馈均衡器)结构。符号时序恢复采用改进的抛物线插值器，决策导向载波恢复用于消除载波频率偏移、相位偏移和相位抖动。所实现的LMDS接收器可支持10、20、30和40 Mbps四种数据速率，并可容纳高达10 Mbaud的符号速率。这种符号速率比现有的QAM接收器快。
{"title":"A QPSK/16 QAM receiver chip for LMDS application","authors":"K. Park, D. Shin, Jun S. Lee, M. Sunwoo","doi":"10.1109/APASIC.2000.896945","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896945","url":null,"abstract":"This paper presents a QPSK/16 QAM down stream receiver ASIC chip for LMDS (Local Multipoint Distribution Services) applications. The proposed LMDS chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE (Decision Feedback Equalizer) structure using CMA (Constant Modulus Algorithm). The symbol timing recovery uses the modified parabolic interpolator and the decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130167541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896958
H. Oh, H. Hong, J.I. Lee, S. Park, K. K. Kwon, J. Hwang
This paper reports the oxide-capping process of microlenses in a CMOS image sensor and its effect on wafer test/package yields of the product. CMOS image sensors with 8 /spl mu/m/spl times/8 /spl mu/m pixel size were fabricated by 0.5 /spl mu/m CMOS logic process incorporated with color filter and microlens processes. After the formation of the microlens, a thin oxide film was deposited as a capping material, and finally pad windows were opened. From the analysis of the yield data, it is concluded that the oxide-capping of the microlenses guarantees the stable wafer test yield and also gives rise to noticeable increase of package yield for CMOS image sensors.
{"title":"Enhancement of wafer test/package yields by oxide-capping of microlens in CMOS image sensor","authors":"H. Oh, H. Hong, J.I. Lee, S. Park, K. K. Kwon, J. Hwang","doi":"10.1109/APASIC.2000.896958","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896958","url":null,"abstract":"This paper reports the oxide-capping process of microlenses in a CMOS image sensor and its effect on wafer test/package yields of the product. CMOS image sensors with 8 /spl mu/m/spl times/8 /spl mu/m pixel size were fabricated by 0.5 /spl mu/m CMOS logic process incorporated with color filter and microlens processes. After the formation of the microlens, a thin oxide film was deposited as a capping material, and finally pad windows were opened. From the analysis of the yield data, it is concluded that the oxide-capping of the microlenses guarantees the stable wafer test yield and also gives rise to noticeable increase of package yield for CMOS image sensors.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123311499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896901
Hong-Yi Huang, Teng-Neng Wang
The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C/sup 3/L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified.
{"title":"CMOS capacitor coupling logic (C/sup 3/L) circuits","authors":"Hong-Yi Huang, Teng-Neng Wang","doi":"10.1109/APASIC.2000.896901","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896901","url":null,"abstract":"The multi-valued logic has been drawing considerable attention as a promising candidate for building future integrated circuits. The capacitor coupling technique is one of the effective methods to approach the performance issue. In this paper the capacitor coupling logic (C/sup 3/L) circuit to implement CMOS logic gates is proposed. The multiple inputs NAND, NOR, AOI, and OAI gates can be easily realized using the technique. Furthermore, the carry and sum circuit of a full-adder is designed and verified.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896943
Dong-Hee Kim, Jin-Ku Kang
This paper describes a 1.0 Gbps clock and data recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380-720 MHz. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m CMOS HSPICE simulation.
{"title":"A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector","authors":"Dong-Hee Kim, Jin-Ku Kang","doi":"10.1109/APASIC.2000.896943","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896943","url":null,"abstract":"This paper describes a 1.0 Gbps clock and data recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380-720 MHz. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m CMOS HSPICE simulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128597051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896974
C. Jeong, W. Park, Sang-Woo Kim, T. Han
The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.
{"title":"The design and implementation of CalmlRISC32 floating point unit","authors":"C. Jeong, W. Park, Sang-Woo Kim, T. Han","doi":"10.1109/APASIC.2000.896974","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896974","url":null,"abstract":"The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896899
H. Bui, A. Al-Sheraidah, Yuke Wang
Exclusive-OR and exclusive-NOR gates are important in digital circuits. This paper proposes a new set of low power 4-transistor XOR/XNOR gates. Simulations have been performed on the circuits along with 10 other XOR gates. The results show that the new XOR/XNOR gates consistently consume less power than any other XOR/XNOR gate known at the time of publication. In fact, it consumes up to more than 3 times less power than the complementary CMOS implementation and can have 34% better propagation delay. The static energy-recovery XOR gate, which is the second least power-consuming, dissipates 10% more power than the new gates.
{"title":"New 4-transistor XOR and XNOR designs","authors":"H. Bui, A. Al-Sheraidah, Yuke Wang","doi":"10.1109/APASIC.2000.896899","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896899","url":null,"abstract":"Exclusive-OR and exclusive-NOR gates are important in digital circuits. This paper proposes a new set of low power 4-transistor XOR/XNOR gates. Simulations have been performed on the circuits along with 10 other XOR gates. The results show that the new XOR/XNOR gates consistently consume less power than any other XOR/XNOR gate known at the time of publication. In fact, it consumes up to more than 3 times less power than the complementary CMOS implementation and can have 34% better propagation delay. The static energy-recovery XOR gate, which is the second least power-consuming, dissipates 10% more power than the new gates.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896911
Yun Kim, B. Song, J. Grosspietsch, S. Gillig
An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in redundant binary (RB) to normal binary (NB) conversion in the RB multiplier. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized converters, and complete carry-free multiplication from input to output is achieved. The proposed method significantly reduces the power and the conversion time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35 /spl mu/m CMOS demonstrates that the 54 b/spl times/54 b multiplier consumes only 53.4 mW at 3.3 V for 74 MHz operation.
{"title":"A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm","authors":"Yun Kim, B. Song, J. Grosspietsch, S. Gillig","doi":"10.1109/APASIC.2000.896911","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896911","url":null,"abstract":"An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in redundant binary (RB) to normal binary (NB) conversion in the RB multiplier. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized converters, and complete carry-free multiplication from input to output is achieved. The proposed method significantly reduces the power and the conversion time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35 /spl mu/m CMOS demonstrates that the 54 b/spl times/54 b multiplier consumes only 53.4 mW at 3.3 V for 74 MHz operation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121420894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896940
Young Sae Kim, Wooseok Kang, J. Choi
In this paper, an implementation method to optimize a 1024-bit RSA processor is presented. Basically, the Montgomery algorithm is used and modified considering the large bit modular multiplication. We propose a new architecture for 1024-bit RSA processing in order to reduce the required hardware resources. The new architecture is also fit for an effective I/O interface. We have implemented a single-chip 1024-bit RSA processor based on the modified algorithm and architecture with 0.65-/spl mu/m SOG technology using Verilog HDL. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 43 ms at 50 MHz.
{"title":"Asynchronous implementation of 1024-bit modular processor for RSA cryptosystem","authors":"Young Sae Kim, Wooseok Kang, J. Choi","doi":"10.1109/APASIC.2000.896940","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896940","url":null,"abstract":"In this paper, an implementation method to optimize a 1024-bit RSA processor is presented. Basically, the Montgomery algorithm is used and modified considering the large bit modular multiplication. We propose a new architecture for 1024-bit RSA processing in order to reduce the required hardware resources. The new architecture is also fit for an effective I/O interface. We have implemented a single-chip 1024-bit RSA processor based on the modified algorithm and architecture with 0.65-/spl mu/m SOG technology using Verilog HDL. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 43 ms at 50 MHz.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121530544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896908
R. Chang, Lung-Chih Kuo
We propose a new differential-type CMOS phase frequency detector for a PLL design. The circuit uses two D-FFs and two delay buffers. Besides, it adopts two reset functions R1 and R2 to avoid the UP and DN being logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of the PLL. The detector can greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error the new detector employs delay buffers to shift the phase error. The circuit is simulated by HSPICE with the 0.35 /spl mu/m CMOS technology.
{"title":"A differential type CMOS phase frequency detector","authors":"R. Chang, Lung-Chih Kuo","doi":"10.1109/APASIC.2000.896908","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896908","url":null,"abstract":"We propose a new differential-type CMOS phase frequency detector for a PLL design. The circuit uses two D-FFs and two delay buffers. Besides, it adopts two reset functions R1 and R2 to avoid the UP and DN being logic-1 simultaneously. Thus, any mismatch current of the charge pump circuit will not affect the performance of the PLL. The detector can greatly reduce the dead-zone phenomenon in the phase characteristic, which is important in low-jitter applications. In order to detect the smallest phase error the new detector employs delay buffers to shift the phase error. The circuit is simulated by HSPICE with the 0.35 /spl mu/m CMOS technology.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131419145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896967
Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim
Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. There are many methods for improving TLB performance, such as increasing the number of entries in TLB and supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. Also software must select a proper page-size assignment policy to take advantage of the larger pages. So, we propose a new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to result of comparison and analysis, the proposed method with fewer entries results in similar performance compared with the conventional TLB with many entries. Also in the case of same area size, it is shown that miss ratio of the proposed TLB can be reduced by as much as 90% comparing with conventional fully-associative TLB.
{"title":"A dynamic TLB management structure to support different page sizes","authors":"Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim","doi":"10.1109/APASIC.2000.896967","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896967","url":null,"abstract":"Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. There are many methods for improving TLB performance, such as increasing the number of entries in TLB and supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. Also software must select a proper page-size assignment policy to take advantage of the larger pages. So, we propose a new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to result of comparison and analysis, the proposed method with fewer entries results in similar performance compared with the conventional TLB with many entries. Also in the case of same area size, it is shown that miss ratio of the proposed TLB can be reduced by as much as 90% comparing with conventional fully-associative TLB.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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