Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896894
Kyuyoung Chung, G. Han, Sungho Kang
This paper proposes a CMOS low noise variable gain amplifier (VGA). It describes the noise optimization method of the proposed VGA. The designed VGA provides of a 0 to 21.30 dB gain variation and with bandwidth of 49 MHz. The input reflected noise voltage is 4.84 nV/sqrt-Hz at 1 MHz and noise figure is 14.53 dB(Rs=50 /spl Omega/). The VGA was fabricated using 0.35-/spl mu/m CMOS technology.
{"title":"A 0.35-/spl mu/m CMOS low noise VGA","authors":"Kyuyoung Chung, G. Han, Sungho Kang","doi":"10.1109/APASIC.2000.896894","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896894","url":null,"abstract":"This paper proposes a CMOS low noise variable gain amplifier (VGA). It describes the noise optimization method of the proposed VGA. The designed VGA provides of a 0 to 21.30 dB gain variation and with bandwidth of 49 MHz. The input reflected noise voltage is 4.84 nV/sqrt-Hz at 1 MHz and noise figure is 14.53 dB(Rs=50 /spl Omega/). The VGA was fabricated using 0.35-/spl mu/m CMOS technology.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132971773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896934
Y. Choi, J. Ihm
In a sampled system, a signal that is commonly present on chip that is particularly troublesome if coupled into the reference is a clock at frequency fs/2, where fs is the high-frequency sampling rate. The presence of a signal at frequency fs/2 on the reference will cause spectral components in the signal near fs/2 to mix down into the baseband. Especially in /spl Sigma/-/spl Delta/ modulator the output bit stream will contain large amounts of quantization noise at frequencies around fs/2 and the intermodulation should be minimized to the highest degree to avoid baseband destruction. In this paper a systematic way where a modulator transfer function is modified to reduce intermodulation effect is proposed. Simulations show the effectiveness of the method.
{"title":"A /spl Sigma/-/spl Delta/ modulator architecture reducing intermodulation of tones near f/sub s//2 into the baseband","authors":"Y. Choi, J. Ihm","doi":"10.1109/APASIC.2000.896934","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896934","url":null,"abstract":"In a sampled system, a signal that is commonly present on chip that is particularly troublesome if coupled into the reference is a clock at frequency fs/2, where fs is the high-frequency sampling rate. The presence of a signal at frequency fs/2 on the reference will cause spectral components in the signal near fs/2 to mix down into the baseband. Especially in /spl Sigma/-/spl Delta/ modulator the output bit stream will contain large amounts of quantization noise at frequencies around fs/2 and the intermodulation should be minimized to the highest degree to avoid baseband destruction. In this paper a systematic way where a modulator transfer function is modified to reduce intermodulation effect is proposed. Simulations show the effectiveness of the method.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133755220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896946
S. Woo, K. Lee, G. Cho
A new CMOS Double-Upconverter (DUC) with half-LO for a DTV (Digital TV) tuner is proposed. It converts a wide-band input video RF signal spanning from 48 MHz to 810 MHz to an IF of 932 MHz with half local oscillator frequencies from 490 MHz to 871 MHz. The proposed architecture reduces the local oscillator frequency to half, which enables the integration on a single chip and reduces the overall power consumption. It also makes the image component low with its architectural property devised on the basis of the Weaver architecture. It is implemented with 0.8 /spl mu/m CMOS technology modified for RF applications.
{"title":"A new CMOS double-upconverter with half-LO for DTV tuner","authors":"S. Woo, K. Lee, G. Cho","doi":"10.1109/APASIC.2000.896946","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896946","url":null,"abstract":"A new CMOS Double-Upconverter (DUC) with half-LO for a DTV (Digital TV) tuner is proposed. It converts a wide-band input video RF signal spanning from 48 MHz to 810 MHz to an IF of 932 MHz with half local oscillator frequencies from 490 MHz to 871 MHz. The proposed architecture reduces the local oscillator frequency to half, which enables the integration on a single chip and reduces the overall power consumption. It also makes the image component low with its architectural property devised on the basis of the Weaver architecture. It is implemented with 0.8 /spl mu/m CMOS technology modified for RF applications.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896912
B. Lim, Jin-Ku Kang
A 32 bit wave pipelined adder circuitry using static CMOS plus data aligning logic is presented. The self-timed wave pipelining algorithm was implemented in the circuit design. The data aligning logic in the algorithm consisted of the double edge triggered flip-flop detecting the slowest arrived signal, the aligning signal generator and latches. Using the algorithm, the delay variation of the signals at the output of the 32 bit adder could be controlled under 130 ps rather than 766 ps in a conventional adder. The circuit operates at a data rate of 800 M/bps using 0.25 /spl mu/m CMOS technology with a 2.5 V supply voltage.
提出了一种采用静态CMOS加数据对齐逻辑的32位波流水加法器电路。在电路设计中实现了自定时波流水线算法。算法中的数据对齐逻辑由检测最慢到达信号的双边触发触发器、对齐信号发生器和锁存器组成。利用该算法，可以将32位加法器输出信号的延迟变化控制在130 ps以下，而不是传统加法器的766 ps。该电路采用0.25 /spl mu/ M CMOS技术，在2.5 V电源电压下以800 M/bps的数据速率工作。
{"title":"A self-timed wave pipelined adder using data align method","authors":"B. Lim, Jin-Ku Kang","doi":"10.1109/APASIC.2000.896912","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896912","url":null,"abstract":"A 32 bit wave pipelined adder circuitry using static CMOS plus data aligning logic is presented. The self-timed wave pipelining algorithm was implemented in the circuit design. The data aligning logic in the algorithm consisted of the double edge triggered flip-flop detecting the slowest arrived signal, the aligning signal generator and latches. Using the algorithm, the delay variation of the signals at the output of the 32 bit adder could be controlled under 130 ps rather than 766 ps in a conventional adder. The circuit operates at a data rate of 800 M/bps using 0.25 /spl mu/m CMOS technology with a 2.5 V supply voltage.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114187923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896931
Kab Joo Lee, Seunghan Kim, Shihyeon Park, Youngsoo Yoo
Static-based verification methodologies are employed to minimize iterative simulations due to functional and timing problems after BIST integration into an ASIC. Formal equivalence checking is used to verify if BIST signals are correctly integrated into an ASIC. Static Timing Analysis (STA) is used to verify BIST timing. Two ASICs, implemented using 0.25 /spl mu/m technology, are used to apply static-based verification methodologies. Our experimental results show that static-based verification achieves significant verification speedup compared to simulation. This allows fast and early detection of function and timing errors that may be introduced during BIST integration:.
{"title":"Static-based verification of memory BIST integration","authors":"Kab Joo Lee, Seunghan Kim, Shihyeon Park, Youngsoo Yoo","doi":"10.1109/APASIC.2000.896931","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896931","url":null,"abstract":"Static-based verification methodologies are employed to minimize iterative simulations due to functional and timing problems after BIST integration into an ASIC. Formal equivalence checking is used to verify if BIST signals are correctly integrated into an ASIC. Static Timing Analysis (STA) is used to verify BIST timing. Two ASICs, implemented using 0.25 /spl mu/m technology, are used to apply static-based verification methodologies. Our experimental results show that static-based verification achieves significant verification speedup compared to simulation. This allows fast and early detection of function and timing errors that may be introduced during BIST integration:.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896918
D. Juang, De-Sheng Chen, Jyou-Min Shyu, Ching-Yuang Wu
In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 /spl mu/m TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset.
{"title":"A low-power 1.2 GHz 0.35 /spl mu/m CMOS PLL","authors":"D. Juang, De-Sheng Chen, Jyou-Min Shyu, Ching-Yuang Wu","doi":"10.1109/APASIC.2000.896918","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896918","url":null,"abstract":"In this paper, a low-power high-speed CMOS PLL is presented. The PLL consists of a 1.2-GHz voltage controlled oscillator, a dead-zone free phase frequency detector, a charge pump, and a frequency divider. The circuit was fabricated using 0.35 /spl mu/m TSMC CMOS technology. The total power consumption is 9.6 mW at 1.2-GHz operating frequency with 1.5 V supply voltage. The phase noise is -94 dBc at 10 kHz offset.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121217375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896950
Bong-Il Park, I. Park, C. Kyung
In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.
{"title":"Interface synthesis for IP based design","authors":"Bong-Il Park, I. Park, C. Kyung","doi":"10.1109/APASIC.2000.896950","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896950","url":null,"abstract":"In system-on-a-chip design, interfacing of Intellectual Property (IP) blocks is one of the most important issues. Since most IPs are provided by different vendors, they have different interface schemes and different operating frequencies. In this paper, we propose a new interface synthesis method that enables one not only to handle the interface between IPs with different operating frequencies but also to minimize the hardware resource required for the interface. We have demonstrated the proposed algorithm by applying it to a real design example, MP3 decoder, and verified the IIS-to-PCI protocol converter on a real hardware system.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115882205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896980
S. Eto, H. Akita, K. Isobe, K. Tsuchida, H. Toda, T. Seki
A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of 0.5 mm/sup 2/.
{"title":"A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)","authors":"S. Eto, H. Akita, K. Isobe, K. Tsuchida, H. Toda, T. Seki","doi":"10.1109/APASIC.2000.896980","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896980","url":null,"abstract":"A new Delay Locked Loop (DLL) using a Digital-to-Analog Converter with the Parallel Variable Resister (PVR-DAC) has been developed. The PVR-DAC successfully manages the current controlled-delay element (CCDE) and achieves a fine time-based resolution. The DLL adopting PVR-DAC has been simulated. It realizes a time-based resolution of 18 ps, an operation frequency range of 143 MHz through 333 MHz, with the maximum power consumption of 20 mW at 1.5 V, and also achieves the small circuit area of 0.5 mm/sup 2/.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896964
Sangyeun Cho, Sanghyun Park, Sang-Woo Kim, Yongchun Kim, Seh-Woong Jeong, B. Chung, H. Roh, Chang-Ho Lee, H. Yang, Sung-Ho Kwak, M. Lee
Architecting today's embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISC/sup TM/-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreaker/sup TM/ (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25 /spl mu/m static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISC/sup TM/-32 operates at 130 MHz (under worst conditions) and consumes 150 /spl mu/A/MHz at 2.5 V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISC/sup TM/-32.
{"title":"CalmRISC/sup TM/-32: a 32-bit low-power MCU core","authors":"Sangyeun Cho, Sanghyun Park, Sang-Woo Kim, Yongchun Kim, Seh-Woong Jeong, B. Chung, H. Roh, Chang-Ho Lee, H. Yang, Sung-Ho Kwak, M. Lee","doi":"10.1109/APASIC.2000.896964","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896964","url":null,"abstract":"Architecting today's embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISC/sup TM/-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreaker/sup TM/ (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25 /spl mu/m static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISC/sup TM/-32 operates at 130 MHz (under worst conditions) and consumes 150 /spl mu/A/MHz at 2.5 V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISC/sup TM/-32.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122594399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-28DOI: 10.1109/APASIC.2000.896976
Y. Cha, Chang-Su Park, Gyeong-Yeon Cho, Hyek-Hwan Choi
This paper presents low cost and high code density embedded 16 bit microprocessor. The instruction set is suitable for C compiler and has good code density. It has 7 general purpose resisters and 16-bit fixed length instruction set which has a short length offset and small immediate operand. A 16-bit offset and immediate operand could be extended by using extension register and extension flag. It's implemented with 4200 gates so that it can be substituted for an 8-bit microprocessor.
{"title":"An embedded 16-bit microprocessor","authors":"Y. Cha, Chang-Su Park, Gyeong-Yeon Cho, Hyek-Hwan Choi","doi":"10.1109/APASIC.2000.896976","DOIUrl":"https://doi.org/10.1109/APASIC.2000.896976","url":null,"abstract":"This paper presents low cost and high code density embedded 16 bit microprocessor. The instruction set is suitable for C compiler and has good code density. It has 7 general purpose resisters and 16-bit fixed length instruction set which has a short length offset and small immediate operand. A 16-bit offset and immediate operand could be extended by using extension register and extension flag. It's implemented with 4200 gates so that it can be substituted for an 8-bit microprocessor.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122253320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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