Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521798
G. Lu
European power module manufacturers pioneered the development of a silver sintering technology, called low-temperature joining technology (LTJT) for lead-free chip attach. Sintered chips on substrate are shown to have better performance and significantly higher reliability at chip junction temperature over 175°C. However, the European process is complex requiring pressure of 20 to 40 MPa to lower the sintering temperature of micron-size silver flakes/powder down to around 250°C. A nanomaterial technology involving the use of silver nanoparticles is described to achieve low-temperature sintering without any applied pressure. The nanosilver paste can be readily stencil-printed or dispensed on substrate for die-attach in air or controlled atmosphere at temperature below 260°C and under zero pressure with small power chips or low pressure of 3 MPa with large IGBT (Insulated Gate Bipolar Transistor) chips. Findings on the sintering behavior of the nanosilver paste and properties of the sintered joints are presented to demonstrate the nanosilver-enabled LTJT as a promising lead-free chip-attach solution with improved thermal and electrical performance and thermo-mechanical reliability of power devices and modules. As a specific application example, the nanosilver-enabled LTJT was used to make planar power modules in which both sides of the IGBT chips were bonded by the sintered nanosilver joint. The planar power modules have low parasitic inductances thus less ringing noises from the device-switching action and can be cooled from both sides of the devices to improve heat dissipation. Details on the design and processing of the double-side cooled power modules and test results on their electrical and thermal performance will be presented.
{"title":"“Low-temperature sintering of nanosilver paste for lead-free chip attach”","authors":"G. Lu","doi":"10.1109/IEMT.2012.6521798","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521798","url":null,"abstract":"European power module manufacturers pioneered the development of a silver sintering technology, called low-temperature joining technology (LTJT) for lead-free chip attach. Sintered chips on substrate are shown to have better performance and significantly higher reliability at chip junction temperature over 175°C. However, the European process is complex requiring pressure of 20 to 40 MPa to lower the sintering temperature of micron-size silver flakes/powder down to around 250°C. A nanomaterial technology involving the use of silver nanoparticles is described to achieve low-temperature sintering without any applied pressure. The nanosilver paste can be readily stencil-printed or dispensed on substrate for die-attach in air or controlled atmosphere at temperature below 260°C and under zero pressure with small power chips or low pressure of 3 MPa with large IGBT (Insulated Gate Bipolar Transistor) chips. Findings on the sintering behavior of the nanosilver paste and properties of the sintered joints are presented to demonstrate the nanosilver-enabled LTJT as a promising lead-free chip-attach solution with improved thermal and electrical performance and thermo-mechanical reliability of power devices and modules. As a specific application example, the nanosilver-enabled LTJT was used to make planar power modules in which both sides of the IGBT chips were bonded by the sintered nanosilver joint. The planar power modules have low parasitic inductances thus less ringing noises from the device-switching action and can be cooled from both sides of the devices to improve heat dissipation. Details on the design and processing of the double-side cooled power modules and test results on their electrical and thermal performance will be presented.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521825
A. Ourdjini, I. Aisha, Y. T. Chin
Doping lead-free solders with minor additions of alloying and impurity elements such as Ni, Bi or Zn appears to have major effects on the growth of intermetallics (IMC) in solder joints during reflow soldering between the Sn-Ag-Cu lead-free solders and the surface finish metallurgy. In this paper, the results of the effect of small Nickel additions (0.05 and 0.1 wt%) on intermetallic formation during soldering with Sn-3Ag-0.5Cu (SAC305) are presented. The Ø500μm solder alloys of Sn-3Ag-0.5Cu, Sn-3Ag-0.5Cu-0.05Ni and Sn-3Ag-0.5Cu-0.1Ni were investigated in detail after reflow soldering at 250°C on copper finish and isothermally aged at 150°C for up to 2000 hours. The results show that after reflow soldering, scallop-type Cu6Sn5/ (Cu, Ni)6Sn5 was the only reaction product formed. A strong influence of Ni addition on the growth rate and thickness of the Cu3Sn layer was also observed. Addition of as little as 0.05wt% Ni to SAC305 solder effectively slows down the growth of this Cu3Sn phase while growth of the Cu6Sn5 continued to increase with increasing in aging time.
{"title":"Effect of Nickel addition into Sn-3Ag-0.5Cu on intermetallic compound formation during Soldering on copper","authors":"A. Ourdjini, I. Aisha, Y. T. Chin","doi":"10.1109/IEMT.2012.6521825","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521825","url":null,"abstract":"Doping lead-free solders with minor additions of alloying and impurity elements such as Ni, Bi or Zn appears to have major effects on the growth of intermetallics (IMC) in solder joints during reflow soldering between the Sn-Ag-Cu lead-free solders and the surface finish metallurgy. In this paper, the results of the effect of small Nickel additions (0.05 and 0.1 wt%) on intermetallic formation during soldering with Sn-3Ag-0.5Cu (SAC305) are presented. The Ø500μm solder alloys of Sn-3Ag-0.5Cu, Sn-3Ag-0.5Cu-0.05Ni and Sn-3Ag-0.5Cu-0.1Ni were investigated in detail after reflow soldering at 250°C on copper finish and isothermally aged at 150°C for up to 2000 hours. The results show that after reflow soldering, scallop-type Cu6Sn5/ (Cu, Ni)6Sn5 was the only reaction product formed. A strong influence of Ni addition on the growth rate and thickness of the Cu3Sn layer was also observed. Addition of as little as 0.05wt% Ni to SAC305 solder effectively slows down the growth of this Cu3Sn phase while growth of the Cu6Sn5 continued to increase with increasing in aging time.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521770
S. Chin, E. Erfe
This paper discusses the material selection of a transfer moldable clear compound to be used for packaging Ambient Light Sensors and Proximity Sensors. Several grades of clear molding compound were characterized for their relevant material properties. Carsem's in-house materials lab was utilized to test the different clear compounds and generate data on glass transition temperature (Tg), coefficient of thermal expansion (CTE), saturated moisture concentration (CSAT) and the coefficient of moisture expansion (CME) - a critical material property not usually found in supplier data sheets. After material characterization, stress modeling using Finite Element Analysis was used to study the shear stress versus adhesion strength at the critical interfaces which are prone to delamination. The stress modeling was also extended to study the effect of different leadframe features on the package robustness after MSL before eventually finalizing the leadframe design. Finally, some reliability data is shared towards the end of the paper. This paper demonstrates how material characterization coupled with stress modeling can greatly accelerate the introduction of new products in an ever-changing and dynamic market place.
{"title":"Transparent molding compound study and leadframe design improvement for ambient light and proximity sensor packaging","authors":"S. Chin, E. Erfe","doi":"10.1109/IEMT.2012.6521770","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521770","url":null,"abstract":"This paper discusses the material selection of a transfer moldable clear compound to be used for packaging Ambient Light Sensors and Proximity Sensors. Several grades of clear molding compound were characterized for their relevant material properties. Carsem's in-house materials lab was utilized to test the different clear compounds and generate data on glass transition temperature (Tg), coefficient of thermal expansion (CTE), saturated moisture concentration (CSAT) and the coefficient of moisture expansion (CME) - a critical material property not usually found in supplier data sheets. After material characterization, stress modeling using Finite Element Analysis was used to study the shear stress versus adhesion strength at the critical interfaces which are prone to delamination. The stress modeling was also extended to study the effect of different leadframe features on the package robustness after MSL before eventually finalizing the leadframe design. Finally, some reliability data is shared towards the end of the paper. This paper demonstrates how material characterization coupled with stress modeling can greatly accelerate the introduction of new products in an ever-changing and dynamic market place.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521813
S. R. Chan, F. Tan, R. Mohd-Mokhtar
Power Distribution Network (PDN) is optimized based on conventional AC and DC noise target specification. Large supply noise occurs due to increase in speed and number of I/O running simultaneously. In this paper, an alternate means to quantify supply noise to signal performance is discussed. Discussion focuses on signal performance impact caused by supply noise with different frequency content. Simulation is carried out using transistor model and findings are then correlated through lab measurements. Using USB I/O as a test case, findings conclude that the USB transmitter performance is less sensitive to supply noise at circuit operating frequency (480 MHz) and its harmonic. Hence, excessive AC noise at its less sensitive region will not cause signal eye diagram to fail.
{"title":"Signal sensitivity to supply noise on high-speed I/O","authors":"S. R. Chan, F. Tan, R. Mohd-Mokhtar","doi":"10.1109/IEMT.2012.6521813","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521813","url":null,"abstract":"Power Distribution Network (PDN) is optimized based on conventional AC and DC noise target specification. Large supply noise occurs due to increase in speed and number of I/O running simultaneously. In this paper, an alternate means to quantify supply noise to signal performance is discussed. Discussion focuses on signal performance impact caused by supply noise with different frequency content. Simulation is carried out using transistor model and findings are then correlated through lab measurements. Using USB I/O as a test case, findings conclude that the USB transmitter performance is less sensitive to supply noise at circuit operating frequency (480 MHz) and its harmonic. Hence, excessive AC noise at its less sensitive region will not cause signal eye diagram to fail.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"548 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134371996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521746
S. Krishnan, A. Haseeb, M. Johan
Cu oxides are widely used in various aspects of electronic applications such as superconductor, gas sensor, ferroelectricity and magnetism. In this paper we report a novel method for energy efficient and eco friendly synthesis of CuO nanocomposites with various physical structures and chemical nature. The nanocomposites were produced by pulsed wire explosion in deionized water at 1°C, 10°C, 15°C, 25°C, 35°C, 45°C, 55°C and 60°C. CuO nanocomposites with different morphology were obtained by simply varying the exploding medium temperature. Needle-like CuO nanocrystals were successfully synthesized in deionized water at 60°C. The spherical nanoparticles were highly dispersed with an average size of 20nm while the needle-like nanocrystals were average 70nm in width and 650nm in length. Optical and electronic properties of the needle-like nanostructure were analyzed. The nanocrystals showed p-type semiconductor characteristics. This will enable cost effective large scale synthesis of CuO nanocomposites for various nanoelectronic applications.
{"title":"Synthesis of CuO nanocomposites with various morphologies via pulsed wire explosion","authors":"S. Krishnan, A. Haseeb, M. Johan","doi":"10.1109/IEMT.2012.6521746","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521746","url":null,"abstract":"Cu oxides are widely used in various aspects of electronic applications such as superconductor, gas sensor, ferroelectricity and magnetism. In this paper we report a novel method for energy efficient and eco friendly synthesis of CuO nanocomposites with various physical structures and chemical nature. The nanocomposites were produced by pulsed wire explosion in deionized water at 1°C, 10°C, 15°C, 25°C, 35°C, 45°C, 55°C and 60°C. CuO nanocomposites with different morphology were obtained by simply varying the exploding medium temperature. Needle-like CuO nanocrystals were successfully synthesized in deionized water at 60°C. The spherical nanoparticles were highly dispersed with an average size of 20nm while the needle-like nanocrystals were average 70nm in width and 650nm in length. Optical and electronic properties of the needle-like nanostructure were analyzed. The nanocrystals showed p-type semiconductor characteristics. This will enable cost effective large scale synthesis of CuO nanocomposites for various nanoelectronic applications.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117150214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521786
A. Yamin, N. Shaffiar, W. K. Loh, M. Tamin
The current formulation of stress- and energy-based cohesive zone model (CZM) is extended to account for load reversals. Cyclic degradation of solder/IMC interface properties, namely penalty stiffness, strengths and critical energy release rates follows power-law functions of fatigue cycles. Performance of the extended CZM is examined using finite element (FE) simulation of a single Sn-4Ag-0.5Cu (SAC405) solder interconnect specimen. Strain rate-dependent response of the solder is represented by unified inelastic strain equations (Anand's model) with optimized model parameters for SAC405 solders. The 3D FE model of the specimen is subjected to cyclic relative displacement (Δδ = 0.003 mm, R = 0) so as to induce shear-dominant fatigue loading. Results show that interface crack initiated at the leading edge of the solder/IMC interface on the tool side of the assembly after 22 cycles have elapsed. Bending stress component induced by the solder stand-off height dominates the interface damage process. A straight interface crack front is predicted indicating the relatively brittle nature of the SAC405/Cu6Sn5 interface. The extended formulation of the CZM to account for load reversals has demonstrated the ability to describe the progressive solder/IMC interface damage process consistent with the mechanics of relatively brittle interface fracture.
将目前基于应力和能量的黏聚区模型(CZM)扩展到考虑荷载逆转。焊料/IMC界面性能的循环退化，即惩罚刚度、强度和临界能量释放率遵循疲劳循环的幂律函数。通过对单个Sn-4Ag-0.5Cu (SAC405)焊料互连试件的有限元模拟，研究了扩展后的CZM的性能。采用统一的非弹性应变方程(Anand模型)表示随应变率变化的焊料响应，并对SAC405焊料优化了模型参数。试件的三维有限元模型受循环相对位移作用(Δδ = 0.003 mm, R = 0)，从而诱发剪切为主的疲劳载荷。结果表明，经过22次循环后，在组件的工具侧焊料/IMC界面的前缘开始出现界面裂纹。由焊料隔离高度引起的弯曲应力分量主导了界面损伤过程。结果表明，SAC405/Cu6Sn5界面具有较脆的脆性。考虑载荷逆转的CZM扩展公式已经证明能够描述与相对脆性界面断裂力学一致的渐进焊料/IMC界面损伤过程。
{"title":"Extended cohesive zone model for simulation of solder/IMC interface cyclic damage process in Pb-free solder interconnects","authors":"A. Yamin, N. Shaffiar, W. K. Loh, M. Tamin","doi":"10.1109/IEMT.2012.6521786","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521786","url":null,"abstract":"The current formulation of stress- and energy-based cohesive zone model (CZM) is extended to account for load reversals. Cyclic degradation of solder/IMC interface properties, namely penalty stiffness, strengths and critical energy release rates follows power-law functions of fatigue cycles. Performance of the extended CZM is examined using finite element (FE) simulation of a single Sn-4Ag-0.5Cu (SAC405) solder interconnect specimen. Strain rate-dependent response of the solder is represented by unified inelastic strain equations (Anand's model) with optimized model parameters for SAC405 solders. The 3D FE model of the specimen is subjected to cyclic relative displacement (Δδ = 0.003 mm, R = 0) so as to induce shear-dominant fatigue loading. Results show that interface crack initiated at the leading edge of the solder/IMC interface on the tool side of the assembly after 22 cycles have elapsed. Bending stress component induced by the solder stand-off height dominates the interface damage process. A straight interface crack front is predicted indicating the relatively brittle nature of the SAC405/Cu6Sn5 interface. The extended formulation of the CZM to account for load reversals has demonstrated the ability to describe the progressive solder/IMC interface damage process consistent with the mechanics of relatively brittle interface fracture.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521811
A. S. Zuruzi, H. C. Gardner, N. MacDonald
This paper discusses a novel thermal management approach using nanostructured titania formed on high-aspect ratio micromachined titanium structures. A recently developed dry etching technology, with etch rates of more than 2 μm/min, enables bulk micromachining of titanium using an inductively coupled plasma to define high aspect ratio structures. This technology allows for the development of three-dimensional architectures through the successive stacking and bonding of through-etched titanium foils. Nanostructured titania was formed on high aspect ratio titanium structures using a simple technology involving oxidation in aqueous hydrogen peroxide followed by annealing. These high aspect ratio structures with nanostructured titania surface and titanium core have excellent hydrophilic properties which bodes well for thermal management applications. Compared to those using copper based wick materials, heat pipes using nanostructured titania/Ti ones have better capillary speed characteristics which decays at a slower rate.
{"title":"Tailored nanostructured titania grown on titanium micropillars with outstanding wicking properties for thermal management of microelectronics devices","authors":"A. S. Zuruzi, H. C. Gardner, N. MacDonald","doi":"10.1109/IEMT.2012.6521811","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521811","url":null,"abstract":"This paper discusses a novel thermal management approach using nanostructured titania formed on high-aspect ratio micromachined titanium structures. A recently developed dry etching technology, with etch rates of more than 2 μm/min, enables bulk micromachining of titanium using an inductively coupled plasma to define high aspect ratio structures. This technology allows for the development of three-dimensional architectures through the successive stacking and bonding of through-etched titanium foils. Nanostructured titania was formed on high aspect ratio titanium structures using a simple technology involving oxidation in aqueous hydrogen peroxide followed by annealing. These high aspect ratio structures with nanostructured titania surface and titanium core have excellent hydrophilic properties which bodes well for thermal management applications. Compared to those using copper based wick materials, heat pipes using nanostructured titania/Ti ones have better capillary speed characteristics which decays at a slower rate.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521797
Tee Swee Xian, P. Nanthakumar
3D packaging provides a high level of functional integration in well established package families including BGAs and leadframe packages, by stacking die and using a mix of assembly technologies including wire bonding, flip chip, surface mounted components and passive cooling. Besides that, the package miniaturization has created challenges to a stacked die packages. With wafers thinned down to 100um, conventional die attach process using solder paste or epoxy may not be suitable in this case due to bleed out of paste and bond line thickness (BLT) consistency. Dicing Die Attach Film (DDAF) as alternative has been widely used with its good control of bleed, consistent bond line thickness and simplified operation. The wafer which is mounted with DDAF will be diced into the predetermined die size and the diced chip will be picked and placed directly to a substrate with adhesive at the back. This paper will discuss the major concerns that contribute by the DDAF which is the void at the interface between the DDAF, die and substrate for a BGA stacked die packages. The characteristics of DDAF void and its formation/reduction mechanism are also investigated. Simultaneously the factors such as substrate surface condition, die attach parameter and molding parameter had been evaluated to improve the overall DDAF void performance.
{"title":"Dicing die attach challenges at multi die stack packages","authors":"Tee Swee Xian, P. Nanthakumar","doi":"10.1109/IEMT.2012.6521797","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521797","url":null,"abstract":"3D packaging provides a high level of functional integration in well established package families including BGAs and leadframe packages, by stacking die and using a mix of assembly technologies including wire bonding, flip chip, surface mounted components and passive cooling. Besides that, the package miniaturization has created challenges to a stacked die packages. With wafers thinned down to 100um, conventional die attach process using solder paste or epoxy may not be suitable in this case due to bleed out of paste and bond line thickness (BLT) consistency. Dicing Die Attach Film (DDAF) as alternative has been widely used with its good control of bleed, consistent bond line thickness and simplified operation. The wafer which is mounted with DDAF will be diced into the predetermined die size and the diced chip will be picked and placed directly to a substrate with adhesive at the back. This paper will discuss the major concerns that contribute by the DDAF which is the void at the interface between the DDAF, die and substrate for a BGA stacked die packages. The characteristics of DDAF void and its formation/reduction mechanism are also investigated. Simultaneously the factors such as substrate surface condition, die attach parameter and molding parameter had been evaluated to improve the overall DDAF void performance.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131770026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521820
A. Yeo, F. Che
This paper presents a Cu wire bond process simulation methodology, to model the mechanical response of the die bond pad stack structure, where different geometries, materials and designs are examined. Both contact and bonding (i.e. ultrasonic) stages are simulated to mimic the actual wire bond interconnection process. Different failure criteria such as maximum shear stress theory, maximum normal stress theory, and maximum distortion energy theory are discussed, and compared with the experimental failure observed. Simulation result reveals that maximum normal stress occurred after the contact force loading, while maximum shear stress occurred after the ultrasonic load with bond force. The high stress region calculated is consistent with the failure location observed in the experimental results, which is at the interface of Mx-1 to low-k dielectric layer. It is also found that top Cu metallization (i.e. Mx) with “array of metal via” design underneath the bond pad is detrimental to the pad structure. Increasing Al bond pad thickness, or/and implementing pad coating layer are an effective approach for increasing the bond pad stack strength, especially with increased Ni coating/plating thickness.
{"title":"Numerical & experimental analysis of bond pad stack structure for wire bond interconnection","authors":"A. Yeo, F. Che","doi":"10.1109/IEMT.2012.6521820","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521820","url":null,"abstract":"This paper presents a Cu wire bond process simulation methodology, to model the mechanical response of the die bond pad stack structure, where different geometries, materials and designs are examined. Both contact and bonding (i.e. ultrasonic) stages are simulated to mimic the actual wire bond interconnection process. Different failure criteria such as maximum shear stress theory, maximum normal stress theory, and maximum distortion energy theory are discussed, and compared with the experimental failure observed. Simulation result reveals that maximum normal stress occurred after the contact force loading, while maximum shear stress occurred after the ultrasonic load with bond force. The high stress region calculated is consistent with the failure location observed in the experimental results, which is at the interface of Mx-1 to low-k dielectric layer. It is also found that top Cu metallization (i.e. Mx) with “array of metal via” design underneath the bond pad is detrimental to the pad structure. Increasing Al bond pad thickness, or/and implementing pad coating layer are an effective approach for increasing the bond pad stack strength, especially with increased Ni coating/plating thickness.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129715437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521763
Teck Siang Lim, C. Cheong, S. Tan
Due to rapid growth of the microelectronics industry, the packaged device with smaller, low cost and high power performance becomes a high demand in the market nowadays. To fulfill the market development rate, flip chip interconnection is the most promising packaging solution. In this environment, the National Semiconductor Sdn. Bhd. (a subsidiary of Texas Instruments) performed a qualification run on Thin Shrink Small Outline Package (TSSOP) with Flip Chip on lead frame (FCOL) exposed die back (eDIE) technology. It has been reported that the most detrimental effect on reliability come from solder extrusion and mold adhesion. The solder extrusion observed like a thin sliver “flake” that partially adhered on the polyimide (PI) layer surface. The solder extrusion can be observed from Scanning Acoustical Microscopy (CSAM) image and SEM cross section image which shows as the delamination. The PI layer with isolation, “Island” is designed as a barrier in between two bumps to prevent solder extruded that connect together. To have better barrier effect by optimizing the PI layer thickness and the width size were further evaluated. Preconditioning was performed to screen out the samples with solder extrusion by doing the electrical testing (ATE). The thermal cycling test was proceeded to assess the reliability up to 500 cycles. The results indicated that the samples with the PI isolation passed the ATE without solder extrusion and no solder joint reliability issue observed.
{"title":"Solder extrusion solution and mold adhesion to die surface improvement with PI isolation design for FCOL exposed die technology","authors":"Teck Siang Lim, C. Cheong, S. Tan","doi":"10.1109/IEMT.2012.6521763","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521763","url":null,"abstract":"Due to rapid growth of the microelectronics industry, the packaged device with smaller, low cost and high power performance becomes a high demand in the market nowadays. To fulfill the market development rate, flip chip interconnection is the most promising packaging solution. In this environment, the National Semiconductor Sdn. Bhd. (a subsidiary of Texas Instruments) performed a qualification run on Thin Shrink Small Outline Package (TSSOP) with Flip Chip on lead frame (FCOL) exposed die back (eDIE) technology. It has been reported that the most detrimental effect on reliability come from solder extrusion and mold adhesion. The solder extrusion observed like a thin sliver “flake” that partially adhered on the polyimide (PI) layer surface. The solder extrusion can be observed from Scanning Acoustical Microscopy (CSAM) image and SEM cross section image which shows as the delamination. The PI layer with isolation, “Island” is designed as a barrier in between two bumps to prevent solder extruded that connect together. To have better barrier effect by optimizing the PI layer thickness and the width size were further evaluated. Preconditioning was performed to screen out the samples with solder extrusion by doing the electrical testing (ATE). The thermal cycling test was proceeded to assess the reliability up to 500 cycles. The results indicated that the samples with the PI isolation passed the ATE without solder extrusion and no solder joint reliability issue observed.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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