Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521812
Z. Abdullah, L. Vigneswaran, A. Ang, G. Yuan
In the fast- paced semiconductor industry the need for package solution arises in order to cope with emerging miniaturization trend. As wafer thickness decreases to 100 μm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping not only during grinding but also at subsequent processing steps.Thinner dies will be able to perform faster heat dissipation to the Cu leadframe to improve the Rth and at the same time will be able to improve the Rdson performance. An effort to assemble an Ultra Thin Dies has been made at die bonding using soft solder, solder paste and also Au Sn Diffusion Soldering. This paper discusses the process optimization and challenges being done at die bond process by using multi needles and peel and ramp concept in order to pick and place such a thin dies in the range of chip thickness less than 60 um . Challenges such as die warpage has been minimized by optimizing the impact of vacuum suction during pick and place on the ultra thin wafer since thin die is very flexible and will be very much influence by the vacuum suction force. The other key parameter is the design of the collect vacuum holes which induced the suction force across the chip surface and will influence its stability during pick and place. The two concepts of pick and place using multi needles and peel and ramp have its own advantages and disadvantages. The experiments conducted revealed the capability of the multi needles and peel and ramp and for stable production both concept works in certain chip sizes with its own process limitation. A feasibility study on ultra thin wafer thickness during pick up and assembly process shows the concept used at die bonding can reduces the stress impact exerted on the chip during pick and place with a proper design of die bonding collet, reduction of die warpage and effect of vacuum suction during pick up process. However in order to achieve a stable production a lot of efforts still need to be done and it involves process optimization , die bonding equipment control and front end wafer technology side.
{"title":"Die attach capability on ultra thin wafer thickness for power semiconductor","authors":"Z. Abdullah, L. Vigneswaran, A. Ang, G. Yuan","doi":"10.1109/IEMT.2012.6521812","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521812","url":null,"abstract":"In the fast- paced semiconductor industry the need for package solution arises in order to cope with emerging miniaturization trend. As wafer thickness decreases to 100 μm and below, manufacturing challenges arise. Ultra-thin wafers are less stable and more vulnerable to stresses, and the die can be prone to breaking and warping not only during grinding but also at subsequent processing steps.Thinner dies will be able to perform faster heat dissipation to the Cu leadframe to improve the Rth and at the same time will be able to improve the Rdson performance. An effort to assemble an Ultra Thin Dies has been made at die bonding using soft solder, solder paste and also Au Sn Diffusion Soldering. This paper discusses the process optimization and challenges being done at die bond process by using multi needles and peel and ramp concept in order to pick and place such a thin dies in the range of chip thickness less than 60 um . Challenges such as die warpage has been minimized by optimizing the impact of vacuum suction during pick and place on the ultra thin wafer since thin die is very flexible and will be very much influence by the vacuum suction force. The other key parameter is the design of the collect vacuum holes which induced the suction force across the chip surface and will influence its stability during pick and place. The two concepts of pick and place using multi needles and peel and ramp have its own advantages and disadvantages. The experiments conducted revealed the capability of the multi needles and peel and ramp and for stable production both concept works in certain chip sizes with its own process limitation. A feasibility study on ultra thin wafer thickness during pick up and assembly process shows the concept used at die bonding can reduces the stress impact exerted on the chip during pick and place with a proper design of die bonding collet, reduction of die warpage and effect of vacuum suction during pick up process. However in order to achieve a stable production a lot of efforts still need to be done and it involves process optimization , die bonding equipment control and front end wafer technology side.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123774500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521778
J. Kong, B. E. Cheah, A. H. Tan
This paper investigates the sensitivity of channel termination on vertical side-chip interconnection (VSCI), an alternative high density and low z-height enabler for 3D packaging technology. In this study, the trends of eye height opening, one of the critical signaling parameters, were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance factors. Simulation results show potential solution space for weak receiver termination to achieve >350mV eye height opening (based on 1V supply voltage) at 30Gbps. Key enabling factors and design trade-offs were discussed and summarized in this paper for future design considerations.
{"title":"Sensitivity study of channel termination on vertical side-chip interconnection","authors":"J. Kong, B. E. Cheah, A. H. Tan","doi":"10.1109/IEMT.2012.6521778","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521778","url":null,"abstract":"This paper investigates the sensitivity of channel termination on vertical side-chip interconnection (VSCI), an alternative high density and low z-height enabler for 3D packaging technology. In this study, the trends of eye height opening, one of the critical signaling parameters, were analyzed based on transmission channel length, input rise time, receiver device capacitance and termination resistance factors. Simulation results show potential solution space for weak receiver termination to achieve >350mV eye height opening (based on 1V supply voltage) at 30Gbps. Key enabling factors and design trade-offs were discussed and summarized in this paper for future design considerations.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134502993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521829
H. Leong, Faizal Zulkifli Mohd, M. R. Ibrahim, Wong Boh Kid, N. Khan, Y. B. Kar, L. C. Tan
Insulated Cu wire is the next generation technology in fine pitch and high density wire bonding, which enables wire crossing and touching without concern for wire-to-wire shorts. However, insulated Cu wire bonding is still at the infant stage compared to Cu wire bonding. This study investigates the wire bond process in term of free air ball (FAB) and ball formation using 20μm Cu wire and insulated Cu wire with target bonded ball size about 35μm. Insulated Cu wire needs a different set of EFO setting compared to Cu wire. Spherical and residue free FAB of insulated Cu was able to form with forming gas. With a set electric flame off (EFO) setting, insulated Cu FAB consistently larger than Cu FAB. The experimental results show clearly that the energy required for the FAB formation for insulated Cu wire is ~20% lower than the Cu wire, probably due to the lesser heat loss from the wire during the EFO firing. Key bonding parameters for insulated Cu were EFO current, EFO time, bond power and bond force to meet the required ball size. This study shows that insulated Cu wire requires less demanding ball bond parameters than Cu wire, indicating softer ball which could be favorable for the sensitive bond structures. Bonding strength in term of ball shear and wire pull strength between the insulated Cu wire and Cu wire is very similar. Other key responses such as Al remnant, pad cratering and intermetallic compound have been studied and will be discussed in details in the paper. Our research successfully established good wire bonding process conditions for the insulated Cu wire and subsequently demonstrated that the technology is feasible using presently available wire bonder.
{"title":"Development of insulated Cu wire ball bonding","authors":"H. Leong, Faizal Zulkifli Mohd, M. R. Ibrahim, Wong Boh Kid, N. Khan, Y. B. Kar, L. C. Tan","doi":"10.1109/IEMT.2012.6521829","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521829","url":null,"abstract":"Insulated Cu wire is the next generation technology in fine pitch and high density wire bonding, which enables wire crossing and touching without concern for wire-to-wire shorts. However, insulated Cu wire bonding is still at the infant stage compared to Cu wire bonding. This study investigates the wire bond process in term of free air ball (FAB) and ball formation using 20μm Cu wire and insulated Cu wire with target bonded ball size about 35μm. Insulated Cu wire needs a different set of EFO setting compared to Cu wire. Spherical and residue free FAB of insulated Cu was able to form with forming gas. With a set electric flame off (EFO) setting, insulated Cu FAB consistently larger than Cu FAB. The experimental results show clearly that the energy required for the FAB formation for insulated Cu wire is ~20% lower than the Cu wire, probably due to the lesser heat loss from the wire during the EFO firing. Key bonding parameters for insulated Cu were EFO current, EFO time, bond power and bond force to meet the required ball size. This study shows that insulated Cu wire requires less demanding ball bond parameters than Cu wire, indicating softer ball which could be favorable for the sensitive bond structures. Bonding strength in term of ball shear and wire pull strength between the insulated Cu wire and Cu wire is very similar. Other key responses such as Al remnant, pad cratering and intermetallic compound have been studied and will be discussed in details in the paper. Our research successfully established good wire bonding process conditions for the insulated Cu wire and subsequently demonstrated that the technology is feasible using presently available wire bonder.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521798
G. Lu
European power module manufacturers pioneered the development of a silver sintering technology, called low-temperature joining technology (LTJT) for lead-free chip attach. Sintered chips on substrate are shown to have better performance and significantly higher reliability at chip junction temperature over 175°C. However, the European process is complex requiring pressure of 20 to 40 MPa to lower the sintering temperature of micron-size silver flakes/powder down to around 250°C. A nanomaterial technology involving the use of silver nanoparticles is described to achieve low-temperature sintering without any applied pressure. The nanosilver paste can be readily stencil-printed or dispensed on substrate for die-attach in air or controlled atmosphere at temperature below 260°C and under zero pressure with small power chips or low pressure of 3 MPa with large IGBT (Insulated Gate Bipolar Transistor) chips. Findings on the sintering behavior of the nanosilver paste and properties of the sintered joints are presented to demonstrate the nanosilver-enabled LTJT as a promising lead-free chip-attach solution with improved thermal and electrical performance and thermo-mechanical reliability of power devices and modules. As a specific application example, the nanosilver-enabled LTJT was used to make planar power modules in which both sides of the IGBT chips were bonded by the sintered nanosilver joint. The planar power modules have low parasitic inductances thus less ringing noises from the device-switching action and can be cooled from both sides of the devices to improve heat dissipation. Details on the design and processing of the double-side cooled power modules and test results on their electrical and thermal performance will be presented.
{"title":"“Low-temperature sintering of nanosilver paste for lead-free chip attach”","authors":"G. Lu","doi":"10.1109/IEMT.2012.6521798","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521798","url":null,"abstract":"European power module manufacturers pioneered the development of a silver sintering technology, called low-temperature joining technology (LTJT) for lead-free chip attach. Sintered chips on substrate are shown to have better performance and significantly higher reliability at chip junction temperature over 175°C. However, the European process is complex requiring pressure of 20 to 40 MPa to lower the sintering temperature of micron-size silver flakes/powder down to around 250°C. A nanomaterial technology involving the use of silver nanoparticles is described to achieve low-temperature sintering without any applied pressure. The nanosilver paste can be readily stencil-printed or dispensed on substrate for die-attach in air or controlled atmosphere at temperature below 260°C and under zero pressure with small power chips or low pressure of 3 MPa with large IGBT (Insulated Gate Bipolar Transistor) chips. Findings on the sintering behavior of the nanosilver paste and properties of the sintered joints are presented to demonstrate the nanosilver-enabled LTJT as a promising lead-free chip-attach solution with improved thermal and electrical performance and thermo-mechanical reliability of power devices and modules. As a specific application example, the nanosilver-enabled LTJT was used to make planar power modules in which both sides of the IGBT chips were bonded by the sintered nanosilver joint. The planar power modules have low parasitic inductances thus less ringing noises from the device-switching action and can be cooled from both sides of the devices to improve heat dissipation. Details on the design and processing of the double-side cooled power modules and test results on their electrical and thermal performance will be presented.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124383997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521804
N. Kooy, N. Rahman, K. Mohamed
The recent developments of flexible electronics, biochips, optical devices and micro/nano-electro-mechanical-systems (MEMS/NEMS) have featured various complex three-dimensional or multileveled micro/ nano structures in its designs. However, fabricating these structures using the existing technologies such as photolithography and electron beam lithography (EBL) are time consuming and involved high process costs. Nevertheless, the production of these microstructures at high volume manufacturing scale has led to the demand for a simpler, low-coat and high-throughput technique for patterning process. In the present work, multi-level microstructures (3-levels) with minimum feature size of approximately 50 μm are continuously patterned onto flexible polymer substrate using in-house designed roll-to-roll ultraviolet nanoimprint lithography (R2R-UV-NIL) system. Using a commercially available 50μm-thick polyethylene terephthalate (PET) film as the flexible substrate and SU8-2002 photopolymer as the imprint resist, continuous patterning of the multi-level structures has been demonstrated at speed of 100 mm/min using R2R-UV-NIL imprinting tool. Ten imprints were produced consecutively, where the confocal laser scanning microscopy (CLSM) measurements of the imprints demonstrated the potential of the R2R-UV-NIL technique to replicate multi-level structures, albeit the pattern waviness or plane flatness issue due to the deformation of the soft PDMS mold. With further process optimization and usage of a harder mold material, the R2R-UV-NIL is a promising technique and tool for fabricating complex 3D and multi-level microstructures on flexible substrate for future applications.
{"title":"Patterning of multi-leveled microstructures on flexible polymer substrate using roll-to-roll ultraviolet nanoimprint lithography","authors":"N. Kooy, N. Rahman, K. Mohamed","doi":"10.1109/IEMT.2012.6521804","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521804","url":null,"abstract":"The recent developments of flexible electronics, biochips, optical devices and micro/nano-electro-mechanical-systems (MEMS/NEMS) have featured various complex three-dimensional or multileveled micro/ nano structures in its designs. However, fabricating these structures using the existing technologies such as photolithography and electron beam lithography (EBL) are time consuming and involved high process costs. Nevertheless, the production of these microstructures at high volume manufacturing scale has led to the demand for a simpler, low-coat and high-throughput technique for patterning process. In the present work, multi-level microstructures (3-levels) with minimum feature size of approximately 50 μm are continuously patterned onto flexible polymer substrate using in-house designed roll-to-roll ultraviolet nanoimprint lithography (R2R-UV-NIL) system. Using a commercially available 50μm-thick polyethylene terephthalate (PET) film as the flexible substrate and SU8-2002 photopolymer as the imprint resist, continuous patterning of the multi-level structures has been demonstrated at speed of 100 mm/min using R2R-UV-NIL imprinting tool. Ten imprints were produced consecutively, where the confocal laser scanning microscopy (CLSM) measurements of the imprints demonstrated the potential of the R2R-UV-NIL technique to replicate multi-level structures, albeit the pattern waviness or plane flatness issue due to the deformation of the soft PDMS mold. With further process optimization and usage of a harder mold material, the R2R-UV-NIL is a promising technique and tool for fabricating complex 3D and multi-level microstructures on flexible substrate for future applications.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125259307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521783
Yonggang Jin, J. Teysseyre, A. Liu, G. Goh, S. Yoon
With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.
{"title":"Development of advanced fan-out wafer level package (embedded wafer level BGA)","authors":"Yonggang Jin, J. Teysseyre, A. Liu, G. Goh, S. Yoon","doi":"10.1109/IEMT.2012.6521783","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521783","url":null,"abstract":"With reducing of silicon techno, the pitches and pads at the chip to package interface become important factor. This drives interconnection toward to fan-out packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the 2nd level interconnects. Fan-out WLP has the potential to realize any number of interconnects at any shrink stage of the wafer node technology.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116653001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521759
I. Shohji, R. Arai
The effect of addition of small amount of Ni, Ge and P into Sn-3Ag-0.5Cu lead-free solder was investigated on microstructures and ball shear force of solder ball joints with electroless Ni/Au electrodes. At low shear speed, fracture mainly occurred in solder and ball shear force increased with increasing shear speed regardless of the solder type. At high shear speed, the fracture mode changed from solder fracture to IMC fracture and thus ball shear force decreased. The effect of single Ge addition was negligible on microstructures and ball shear force of the solder ball joints. On the contrary, the single P addition degraded ball shear force. The complex addition of Ni and P was effective to inhibit the degradation of ball shear force by the single P addition.
{"title":"Effect of Ni, Ge and P addition in Sn-Ag-Cu lead-free solder on solder joint properties with electroless Ni/Au electrodes","authors":"I. Shohji, R. Arai","doi":"10.1109/IEMT.2012.6521759","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521759","url":null,"abstract":"The effect of addition of small amount of Ni, Ge and P into Sn-3Ag-0.5Cu lead-free solder was investigated on microstructures and ball shear force of solder ball joints with electroless Ni/Au electrodes. At low shear speed, fracture mainly occurred in solder and ball shear force increased with increasing shear speed regardless of the solder type. At high shear speed, the fracture mode changed from solder fracture to IMC fracture and thus ball shear force decreased. The effect of single Ge addition was negligible on microstructures and ball shear force of the solder ball joints. On the contrary, the single P addition degraded ball shear force. The complex addition of Ni and P was effective to inhibit the degradation of ball shear force by the single P addition.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121639602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521772
M. Tiong, Thiruselvam, R. Tugay
The need to track every lot before and after each process or step into the system is an unavoidable task as this is how the lot is tracked for its location, timeliness and status. In general, the data entry to the system or paperwork may consist of multiple steps and sequence, this would definately contribute and occupy precious production time. This calls for an automated lot transaction system to regain the time wasted and redeploy operator's valuable time to other value added activities.
{"title":"Automated assembly lot transaction","authors":"M. Tiong, Thiruselvam, R. Tugay","doi":"10.1109/IEMT.2012.6521772","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521772","url":null,"abstract":"The need to track every lot before and after each process or step into the system is an unavoidable task as this is how the lot is tracked for its location, timeliness and status. In general, the data entry to the system or paperwork may consist of multiple steps and sequence, this would definately contribute and occupy precious production time. This calls for an automated lot transaction system to regain the time wasted and redeploy operator's valuable time to other value added activities.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521794
R. Balabbo, M. Picardal
Wirebond interconnect reliability in integrated circuit, IC, chip is one of the key characteristic for the IC's performance during its function. One of the common and known interconnect reliability failures is cratering or the Wirebonding or Probing process related damage in bond pad surface and underlying material. This study determined that cratering is not only Wirebond or Probe process induced. Cratering can also be induced by the chemical test preparation, the etching process. Samples for pad cratering test are pulled out after Wirebond. To determine if there is damage in the pad, the wire-pad intermetallic is etched. The complete etching process shows the ball bond lifting and then revealing the pad surface. If not optimized, the etching process in the extreme side or over etch will shift the stress in the pad as the wire lifts. This mean a portion of the pad peels off with the wire resulting to pad damage. This phenomenon was validated in a screening design of experiment, DOE covering temperature before etch start, amount of etching chemicals, volume of samples, and etch time as key input variables. Temperature before etch start was the significant factor at 95% confidence level and was optimized. To avoid over etch; the process should start at 40 degrees Celsius. The cratering test procedure was revised and since then bond pad crater test over rejection was eliminated.
{"title":"Elimination of integrated circuit bond pad crater test over rejection","authors":"R. Balabbo, M. Picardal","doi":"10.1109/IEMT.2012.6521794","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521794","url":null,"abstract":"Wirebond interconnect reliability in integrated circuit, IC, chip is one of the key characteristic for the IC's performance during its function. One of the common and known interconnect reliability failures is cratering or the Wirebonding or Probing process related damage in bond pad surface and underlying material. This study determined that cratering is not only Wirebond or Probe process induced. Cratering can also be induced by the chemical test preparation, the etching process. Samples for pad cratering test are pulled out after Wirebond. To determine if there is damage in the pad, the wire-pad intermetallic is etched. The complete etching process shows the ball bond lifting and then revealing the pad surface. If not optimized, the etching process in the extreme side or over etch will shift the stress in the pad as the wire lifts. This mean a portion of the pad peels off with the wire resulting to pad damage. This phenomenon was validated in a screening design of experiment, DOE covering temperature before etch start, amount of etching chemicals, volume of samples, and etch time as key input variables. Temperature before etch start was the significant factor at 95% confidence level and was optimized. To avoid over etch; the process should start at 40 degrees Celsius. The cratering test procedure was revised and since then bond pad crater test over rejection was eliminated.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128227101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/IEMT.2012.6521833
Jie Wu, T. Rockey, O. Yauw, Liming Shen, B. Chylak
The LED lighting market has grown rapidly in recent years. Silver (Ag) and silver-rich alloy wire are drawing more and more attention in the LED industry because of its better thermal and electrical conductivity, much lower price as well as higher reflectance rate. Being considered as a potential alternative to Au wire in LED packages, the bonding capability of Ag-alloy wire on a LED device was evaluated in this study. The performance of Ag-alloy FAB with and without a cover gas was first studied. Using the bonding results of Au wire as the benchmark, investigation of the bonding capability and reliability of the Ag-alloy wire with and without cover gas was also carried out. Generally, Ag-alloy wire delivers better performance when bonding with a cover gas. During bonding of Ag-alloy wire without a cover gas, degradation of FAB repeatability, ball uniformity and bonding strength were observed. However, for low-end LED devices, bonding of Ag-alloy wire without a cover gas is a possible compromise for more cost savings.
{"title":"Bonding of Ag-alloy wire in LED packages","authors":"Jie Wu, T. Rockey, O. Yauw, Liming Shen, B. Chylak","doi":"10.1109/IEMT.2012.6521833","DOIUrl":"https://doi.org/10.1109/IEMT.2012.6521833","url":null,"abstract":"The LED lighting market has grown rapidly in recent years. Silver (Ag) and silver-rich alloy wire are drawing more and more attention in the LED industry because of its better thermal and electrical conductivity, much lower price as well as higher reflectance rate. Being considered as a potential alternative to Au wire in LED packages, the bonding capability of Ag-alloy wire on a LED device was evaluated in this study. The performance of Ag-alloy FAB with and without a cover gas was first studied. Using the bonding results of Au wire as the benchmark, investigation of the bonding capability and reliability of the Ag-alloy wire with and without cover gas was also carried out. Generally, Ag-alloy wire delivers better performance when bonding with a cover gas. During bonding of Ag-alloy wire without a cover gas, degradation of FAB repeatability, ball uniformity and bonding strength were observed. However, for low-end LED devices, bonding of Ag-alloy wire without a cover gas is a possible compromise for more cost savings.","PeriodicalId":315408,"journal":{"name":"2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116114754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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