Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706666
M.S. Serina, S. Mosin
The digital representation of audio data offers many advantages: high noise-immunity, stability and etc. The application of wavelet transform for audio information compression was investigated in the present research work. The developed software model allowed to find out the influence of different factors for the compression ratio. The initial audio file is compressed in 2-4 times depending on different parameters. Thus the restored file is deformed less than on 10 %
{"title":"Digital Audio Information Compression Using Wavelets","authors":"M.S. Serina, S. Mosin","doi":"10.1109/MIXDES.2006.1706666","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706666","url":null,"abstract":"The digital representation of audio data offers many advantages: high noise-immunity, stability and etc. The application of wavelet transform for audio information compression was investigated in the present research work. The developed software model allowed to find out the influence of different factors for the compression ratio. The initial audio file is compressed in 2-4 times depending on different parameters. Thus the restored file is deformed less than on 10 %","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121622031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706544
T. Jezynski, S. Simrock
The Low-Level Radio Frequency System (LLRF) for the superconducting cavities of the European X-FEL must provide exceptional stability of the accelerating RF field amplitude (0.01%) and phase (0.01 degrees) at a frequency of 1.3 GHz. These requirements must be achieved in pulsed operation mode with one klystron driving 32 cavities. It is thus necessary to design and build a modern LLRF control system, consisting of state of the art hardware and sophisticated control algorithms requiring high gain, low noise, fast and high resolution ADCs (up 16 bits, >100MHz), and high performance data processing using FPGAs and DSPs with low latency. A complete LLRF system must support more than 100 analogue input channels. This paper describes one possible architecture, which will be tested at DESY by the end of 2006.
{"title":"The low level radio frequency system architecture for the european X-FEL","authors":"T. Jezynski, S. Simrock","doi":"10.1109/MIXDES.2006.1706544","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706544","url":null,"abstract":"The Low-Level Radio Frequency System (LLRF) for the superconducting cavities of the European X-FEL must provide exceptional stability of the accelerating RF field amplitude (0.01%) and phase (0.01 degrees) at a frequency of 1.3 GHz. These requirements must be achieved in pulsed operation mode with one klystron driving 32 cavities. It is thus necessary to design and build a modern LLRF control system, consisting of state of the art hardware and sophisticated control algorithms requiring high gain, low noise, fast and high resolution ADCs (up 16 bits, >100MHz), and high performance data processing using FPGAs and DSPs with low latency. A complete LLRF system must support more than 100 analogue input channels. This paper describes one possible architecture, which will be tested at DESY by the end of 2006.","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122121214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706568
E. Yilmaz, G. Dundar
In this work, a new performance oriented module generator is developed. This software, which has new features such as evaluating a cost function using every possible realization and generating modules according to this data, is part of a more general tool, ALG (analog layout generator) (Balkir, 2003). The new tool supports simple module generation; unfolded and folded transistor generation, as well as capacitance reducing merged structure and mismatch reducing interdigitized and common centroid structures
{"title":"A new performance oriented module generator","authors":"E. Yilmaz, G. Dundar","doi":"10.1109/MIXDES.2006.1706568","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706568","url":null,"abstract":"In this work, a new performance oriented module generator is developed. This software, which has new features such as evaluating a cost function using every possible realization and generating modules according to this data, is part of a more general tool, ALG (analog layout generator) (Balkir, 2003). The new tool supports simple module generation; unfolded and folded transistor generation, as well as capacitance reducing merged structure and mismatch reducing interdigitized and common centroid structures","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114972417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706580
A. Seyedi, S. H. Rasouli, A. Amirabadi, A. Afzali-Kusha, C. Lucas, B. Forouzandeh
An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to get a proper transistor sizing. The simulation results proposed in (Jung et al., 2001) is used for the first generation and finally obtained acceptable results
提出了一种基于遗传算法的多米诺逻辑电路优化设计方法。采用基于仿真的遗传算法设计多米诺骨牌逻辑电路，达到较高的精度。根据给定的噪声裕度、时延、漏功率和有功功率，定义了适应度函数，并采用遗传算法确定了合适的晶体管尺寸。(Jung et al.， 2001)中提出的仿真结果用于第一代，最终获得了可接受的结果
{"title":"Design Of Domino Logic Circuits By An Optimization Method","authors":"A. Seyedi, S. H. Rasouli, A. Amirabadi, A. Afzali-Kusha, C. Lucas, B. Forouzandeh","doi":"10.1109/MIXDES.2006.1706580","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706580","url":null,"abstract":"An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to get a proper transistor sizing. The simulation results proposed in (Jung et al., 2001) is used for the first generation and finally obtained acceptable results","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122930074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706659
H. Lin, H. Lin, R. Chang, S.-W. Chen, Chih-Yuan Liao, C.-H. Wu
A high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18mum 1P6M technology at supply voltage of 1.8V
{"title":"A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor","authors":"H. Lin, H. Lin, R. Chang, S.-W. Chen, Chih-Yuan Liao, C.-H. Wu","doi":"10.1109/MIXDES.2006.1706659","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706659","url":null,"abstract":"A high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18mum 1P6M technology at supply voltage of 1.8V","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"63 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120896831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706646
T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka
The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of a little diagnostic resolution. The second step (which is made only in the case of the detection of faults in the first step) is the localization step by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures. The use of two signatures eliminates aliasing of static faults while adding the third signature enables dependable identification of such faults. The theory given in the paper is partially illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable
{"title":"Multi-signature Analysis For Interconnect Test","authors":"T. Garbolino, M. Kopec, K. Gucwa, A. Hlawiczka","doi":"10.1109/MIXDES.2006.1706646","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706646","url":null,"abstract":"The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of a little diagnostic resolution. The second step (which is made only in the case of the detection of faults in the first step) is the localization step by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures. The use of two signatures eliminates aliasing of static faults while adding the third signature enables dependable identification of such faults. The theory given in the paper is partially illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122582765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706667
R. Chaisricharoen, B. Chipipop, B. Sirinaovakul
In this work, the practical response of a very compact version of OTA-based TT biquad which is not suitable to compensate with regular methods, is compensated by the use of SA algorithm. For effective compensation, the OTA nonidealities are precisely defined based on the commercially available OTA, LM13700 from National Semiconductor. The initial solution is obtained via the ordinary method of an analogue filter design based on the utilization of ideal-OTA-based transfer function which provides the response that is much deviated from the desired bandpass response especially in the pole frequency closing to the OTA's finite bandwidth. The Matlab is used as the tool for implementing the compensation process, while the results which are the circuit parameters are being verified by the OrCAD PSPICE simulation. Using the SSE based cost function; the simulation displays the significant improvement of the compensated response compared to the initial solution but still not acceptable. To retrieve the remarkable response, the weighted SSE is utilized while maintaining others parameters
{"title":"Effects Of OTA's Nonidealities On Bandpass Otabased Tow-thomas Biquad And Compensation Via Simulated Annealing Algorithm","authors":"R. Chaisricharoen, B. Chipipop, B. Sirinaovakul","doi":"10.1109/MIXDES.2006.1706667","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706667","url":null,"abstract":"In this work, the practical response of a very compact version of OTA-based TT biquad which is not suitable to compensate with regular methods, is compensated by the use of SA algorithm. For effective compensation, the OTA nonidealities are precisely defined based on the commercially available OTA, LM13700 from National Semiconductor. The initial solution is obtained via the ordinary method of an analogue filter design based on the utilization of ideal-OTA-based transfer function which provides the response that is much deviated from the desired bandpass response especially in the pole frequency closing to the OTA's finite bandwidth. The Matlab is used as the tool for implementing the compensation process, while the results which are the circuit parameters are being verified by the OrCAD PSPICE simulation. Using the SSE based cost function; the simulation displays the significant improvement of the compensated response compared to the initial solution but still not acceptable. To retrieve the remarkable response, the weighted SSE is utilized while maintaining others parameters","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122586642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706592
G. Nagy, A. Poppe
This paper deals with the RF communication issues of low-voltage, low-power autonomous sensors. The sensors gather all or part of the energy needed for their operation from the environment, thus challenging the design engineers to find ultra low-power solutions. A major part of the power consumption of autonomous sensors is drawn by the communication circuitry, thus it is of great importance to find the optimal modulation scheme and structures. Three analog multipliers were investigated from the aspect of consumption and an alternative communication method is also presented
{"title":"Low-voltage, Low-power Solutions For Wireless Autonomous Sensors Aimed For Ami Applications","authors":"G. Nagy, A. Poppe","doi":"10.1109/MIXDES.2006.1706592","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706592","url":null,"abstract":"This paper deals with the RF communication issues of low-voltage, low-power autonomous sensors. The sensors gather all or part of the energy needed for their operation from the environment, thus challenging the design engineers to find ultra low-power solutions. A major part of the power consumption of autonomous sensors is drawn by the communication circuitry, thus it is of great importance to find the optimal modulation scheme and structures. Three analog multipliers were investigated from the aspect of consumption and an alternative communication method is also presented","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115789341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706674
J. Pochmara
We proposed and improved an adaptive neural predistorter, which can automatically compensate for amplifier nonlinearity and thus makes it possible to transmit OFDM signals without incurring intolerable distortions. The neural predistorter utilizes gradient algorithms for its adaptation. Our results indicate clear improvements in performance for neural networks networks incorporating memory into their structure
{"title":"Using neural network for reduction distrotion introduced by power amplifier in digital communication systems","authors":"J. Pochmara","doi":"10.1109/MIXDES.2006.1706674","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706674","url":null,"abstract":"We proposed and improved an adaptive neural predistorter, which can automatically compensate for amplifier nonlinearity and thus makes it possible to transmit OFDM signals without incurring intolerable distortions. The neural predistorter utilizes gradient algorithms for its adaptation. Our results indicate clear improvements in performance for neural networks networks incorporating memory into their structure","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115963347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706617
A. Golda, A. Kos
The paper presents techniques of dynamic control of digital integrated systems performance considering die temperature. The dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS) are taken into account. Allowing for the power-time product (pt) a new predictive method that improves the efficiency of DCT and DFS techniques is introduced
{"title":"Predictive Frequency Control For Low Power Digital Systems","authors":"A. Golda, A. Kos","doi":"10.1109/MIXDES.2006.1706617","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706617","url":null,"abstract":"The paper presents techniques of dynamic control of digital integrated systems performance considering die temperature. The dynamic clock throttling (DCT) and the dynamic frequency scaling (DFS) are taken into account. Allowing for the power-time product (pt) a new predictive method that improves the efficiency of DCT and DFS techniques is introduced","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124133353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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