Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706557
E. Kitonaki, A. Bazigos, M. Bucher, H. Puchner, S. Bhardwaj, Y. Papananos
Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large temperature range. Scaling properties of the technology and the model are illustrated with fits versus channel length and width. The model is also compared to measured capacitance-voltage characteristics. Furthermore, some comparisons to a BSIM3v3 model for the same technology are provided
{"title":"Scaling Issues In An 0.15/spl mu/m CMOS Technology With EKV3.0","authors":"E. Kitonaki, A. Bazigos, M. Bucher, H. Puchner, S. Bhardwaj, Y. Papananos","doi":"10.1109/MIXDES.2006.1706557","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706557","url":null,"abstract":"Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large temperature range. Scaling properties of the technology and the model are illustrated with fits versus channel length and width. The model is also compared to measured capacitance-voltage characteristics. Furthermore, some comparisons to a BSIM3v3 model for the same technology are provided","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126094666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706632
S. Hashemi, N. Masoumi, C. Lucas
This paper presents an optimal clock skew scheduling tolerant to delay uncertainty by using genetic algorithms. In using genetic algorithm two optimization problems are aimed: 1) clock period minimization and 2) tolerance maximization to the delay uncertainty due to the process and environmental parameters variations (PEPV). Application of the proposed clock skew scheduling and topology design on the test circuits demonstrates clock distribution networks with noticeably improved tolerance to delay uncertainty, up to plusmn20% tolerance to power supply variations is reached and the most critical datapath sensitivity to PEPV is improved by a factor of 7, while the system performance degradation is small
{"title":"Optimal Clock Skew Scheduling And Topology Design Tolerant To Delay Uncertainty Using Genetic Algorithms","authors":"S. Hashemi, N. Masoumi, C. Lucas","doi":"10.1109/MIXDES.2006.1706632","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706632","url":null,"abstract":"This paper presents an optimal clock skew scheduling tolerant to delay uncertainty by using genetic algorithms. In using genetic algorithm two optimization problems are aimed: 1) clock period minimization and 2) tolerance maximization to the delay uncertainty due to the process and environmental parameters variations (PEPV). Application of the proposed clock skew scheduling and topology design on the test circuits demonstrates clock distribution networks with noticeably improved tolerance to delay uncertainty, up to plusmn20% tolerance to power supply variations is reached and the most critical datapath sensitivity to PEPV is improved by a factor of 7, while the system performance degradation is small","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128778625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706578
B. Forouzandeh, A. Seyedi
In this paper, the performance of double-edge triggered feedbacked flip-flop (DFFF) in SOI and bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to bulk technology
{"title":"Comparing The Performance Of A Low-power High Speed Flip-flop In Bulk And Soi Technologies","authors":"B. Forouzandeh, A. Seyedi","doi":"10.1109/MIXDES.2006.1706578","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706578","url":null,"abstract":"In this paper, the performance of double-edge triggered feedbacked flip-flop (DFFF) in SOI and bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to bulk technology","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"20 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130293861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706645
S. Yarmolik, V. Yarmolik
The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated
{"title":"Modified Gray And Counter Sequences For Memory Test Address Generation","authors":"S. Yarmolik, V. Yarmolik","doi":"10.1109/MIXDES.2006.1706645","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706645","url":null,"abstract":"The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"159 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128942992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706697
M. Wojtera, B. Sakowicz
Article presents a way of providing a project management support through web based application, using open source solutions. First the architecture is discussed, then consequently layers of the architecture are described, additionally possible further developments are mentioned
{"title":"Web Application For Project Management Based On Open Source Solutions","authors":"M. Wojtera, B. Sakowicz","doi":"10.1109/MIXDES.2006.1706697","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706697","url":null,"abstract":"Article presents a way of providing a project management support through web based application, using open source solutions. First the architecture is discussed, then consequently layers of the architecture are described, additionally possible further developments are mentioned","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121064300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706553
M. Kayal, M. Blagojevic
This paper presents a methodology of a basic analog blocks retargeting from bulk to fully depleted (FD) SOI technology. The design methodology is generally not related to the model used for the circuit simulations. However, the proposed one is closely linked to the EKV MOS model that has been chosen for the FD SOI circuit simulations. Same of EKV parameters are used and expressions along with the gm/I Ddesign approach to demonstrate that the basic analog circuits are simply retargeted from bulk to SOI
{"title":"Design Methodology Based On The Analog Blocks Retargeting From Bulk To FD SOI Using EKV Model","authors":"M. Kayal, M. Blagojevic","doi":"10.1109/MIXDES.2006.1706553","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706553","url":null,"abstract":"This paper presents a methodology of a basic analog blocks retargeting from bulk to fully depleted (FD) SOI technology. The design methodology is generally not related to the model used for the circuit simulations. However, the proposed one is closely linked to the EKV MOS model that has been chosen for the FD SOI circuit simulations. Same of EKV parameters are used and expressions along with the gm/I Ddesign approach to demonstrate that the basic analog circuits are simply retargeted from bulk to SOI","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"258263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123287138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706616
M. Janicki, A. Napieralski
Thermal simulations are an indispensable stage in the design process of modern electronic circuits. This paper is intended to demonstrate how simple parametric thermal analyses of electronic circuits can be performed with reasonable accuracy using an analytical solution of the heat equation. The thermal model solution is found employing the Green's function approach without the use of any sophisticated and expensive numerical solver. The presented thermal simulations investigate the influence of various thermal model parameters on the temperature of a test structure. Similar analyses can be performed during the design of real electronic circuits as to optimise them thermally
{"title":"Parametric Thermal Analyses Of Electronic Circuits With Green's Functions","authors":"M. Janicki, A. Napieralski","doi":"10.1109/MIXDES.2006.1706616","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706616","url":null,"abstract":"Thermal simulations are an indispensable stage in the design process of modern electronic circuits. This paper is intended to demonstrate how simple parametric thermal analyses of electronic circuits can be performed with reasonable accuracy using an analytical solution of the heat equation. The thermal model solution is found employing the Green's function approach without the use of any sophisticated and expensive numerical solver. The presented thermal simulations investigate the influence of various thermal model parameters on the temperature of a test structure. Similar analyses can be performed during the design of real electronic circuits as to optimise them thermally","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130891511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706538
B. Świercz, D. Makowski, A. Napieralski
Modern high-energy physics experiments require sophisticated and complex control systems. The control systems should be able to tolerate radiation generated by high-energy accelerators and thus reliability is important feature. Reliability of control systems depends on hardware and software quality. Hardware solutions are the most effective techniques to protect system against radiation influence. Commercial of the shelf (COTS) elements are used often and protection mechanisms are moved from hardware to software layer, due to cost-effective design. This paper highlights the new approach to protect systems on software level. The protection against soft errors is assured by operating system that is transparent to other applications
{"title":"A novel approach for operating systems protection against single event upset","authors":"B. Świercz, D. Makowski, A. Napieralski","doi":"10.1109/MIXDES.2006.1706538","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706538","url":null,"abstract":"Modern high-energy physics experiments require sophisticated and complex control systems. The control systems should be able to tolerate radiation generated by high-energy accelerators and thus reliability is important feature. Reliability of control systems depends on hardware and software quality. Hardware solutions are the most effective techniques to protect system against radiation influence. Commercial of the shelf (COTS) elements are used often and protection mechanisms are moved from hardware to software layer, due to cost-effective design. This paper highlights the new approach to protect systems on software level. The protection against soft errors is assured by operating system that is transparent to other applications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706688
S. Bermejo, J. Cabestany
Otoliths are calcified structures in the inner ear of fish. The otolith shape changes during a fish's lifetime are particular to individual species. Then, otolith shape can be used to differentiate between species and between fish of the same species. Fishery research has used the growth patterns (i.e. rings) found in these calcified structures to estimate the age of individual fish. However, many factors, such as seasonal variations, temperature, habitat and food, may influence otolith growth. Then, the manual classification of otoliths remains a difficult task, and even experienced examiners can give inaccurate age estimation. We propose to use statistical learning techniques (artificial neural networks) to improve and automate the process. ANN classification methods are evaluated and used with some real otolith databases, giving significant results
{"title":"Otolith Database Analysis For Fish Age Estimation Using Neural Networks Methods","authors":"S. Bermejo, J. Cabestany","doi":"10.1109/MIXDES.2006.1706688","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706688","url":null,"abstract":"Otoliths are calcified structures in the inner ear of fish. The otolith shape changes during a fish's lifetime are particular to individual species. Then, otolith shape can be used to differentiate between species and between fish of the same species. Fishery research has used the growth patterns (i.e. rings) found in these calcified structures to estimate the age of individual fish. However, many factors, such as seasonal variations, temperature, habitat and food, may influence otolith growth. Then, the manual classification of otoliths remains a difficult task, and even experienced examiners can give inaccurate age estimation. We propose to use statistical learning techniques (artificial neural networks) to improve and automate the process. ANN classification methods are evaluated and used with some real otolith databases, giving significant results","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"61 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114108174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706686
A. Olszewski, W. Kuzański
Varicocele testis is considered one of the main reasons for men infertility. Authors presents results of infrared thermography investigations carried on a group of 20 young men aged 13 to 16 who were patients of Clinic of Paediatric Surgery and Oncology, Medical University of Lodz. All of them suffered from left varicocele testis of 3rd degree (ace. to Dubin and Amelar). Obtained infrared images allowed to divide group of 20 patients into two groups: (1) varicocele testis with increased temperature in the area restricted to left neck scrotum ("cold"), (2) varicocele testis with increased temperature in the area spreading on left neck scrotum and both testis ("hot"). Authors showed statistically significant differences between those two groups which meant different stages of illness and resulted in decisions on further clinical treatment
{"title":"Infrared Thermography As A Tool For Early Diagnosis Of Men Infertility Risk","authors":"A. Olszewski, W. Kuzański","doi":"10.1109/MIXDES.2006.1706686","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706686","url":null,"abstract":"Varicocele testis is considered one of the main reasons for men infertility. Authors presents results of infrared thermography investigations carried on a group of 20 young men aged 13 to 16 who were patients of Clinic of Paediatric Surgery and Oncology, Medical University of Lodz. All of them suffered from left varicocele testis of 3rd degree (ace. to Dubin and Amelar). Obtained infrared images allowed to divide group of 20 patients into two groups: (1) varicocele testis with increased temperature in the area restricted to left neck scrotum (\"cold\"), (2) varicocele testis with increased temperature in the area spreading on left neck scrotum and both testis (\"hot\"). Authors showed statistically significant differences between those two groups which meant different stages of illness and resulted in decisions on further clinical treatment","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124037350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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