Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706596
S. Andersson, J. Konopacki, J. Dabrowski, C. Svensson
In this paper we present the noise analysis of an SC filter for RF sampling and downconversion. The filter implementation is made in 0.12mum CMOS and is primarily intended for WLAN in the 2.4 GHz band and with 20 MHz signal bandwidth. The fundamental noise properties of switched capacitor circuits are discussed while deriving the necessary equations needed for the filter noise calculation. The influence of amplifier noise is also discussed, and a technique to remove low-frequency noise and DC offset from the amplifiers is presented. Finally, a noise estimation of a complete RF sampling front-end is made. Our results are verified by simulations using Cadence Spectre RF simulations
本文给出了用于射频采样和下变频的SC滤波器的噪声分析。该滤波器采用0.12 μ m CMOS实现，主要用于2.4 GHz频段和20 MHz信号带宽的WLAN。讨论了开关电容电路的基本噪声特性，并推导了滤波器噪声计算所需的方程。讨论了放大器噪声的影响，提出了一种消除放大器低频噪声和直流偏置的技术。最后，对一个完整的射频采样前端进行了噪声估计。通过Cadence Spectre射频仿真验证了我们的研究结果
{"title":"Noise Analysis And Noise Estimation Of An RF Sampling Front-end Using An SC Decimation Filter","authors":"S. Andersson, J. Konopacki, J. Dabrowski, C. Svensson","doi":"10.1109/MIXDES.2006.1706596","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706596","url":null,"abstract":"In this paper we present the noise analysis of an SC filter for RF sampling and downconversion. The filter implementation is made in 0.12mum CMOS and is primarily intended for WLAN in the 2.4 GHz band and with 20 MHz signal bandwidth. The fundamental noise properties of switched capacitor circuits are discussed while deriving the necessary equations needed for the filter noise calculation. The influence of amplifier noise is also discussed, and a technique to remove low-frequency noise and DC offset from the amplifiers is presented. Finally, a noise estimation of a complete RF sampling front-end is made. Our results are verified by simulations using Cadence Spectre RF simulations","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706613
F. Masana
Die attach contribution to total thermal resistance can be a significant part of its final value. Material choice, bondline thickness, voiding and interface delamination are some of the key factors affecting attachment quality, while process variations may seriously impair the final heat transfer characteristics of finished devices. In this work, we introduce a fast method to monitor die attach interface in finished devices. The measurements are performed onto IGBT's, although the method may be used on any bipolar device by correct choice of measurement setup
{"title":"Die Attach Thermal Monitoring Of IGBT Devices","authors":"F. Masana","doi":"10.1109/MIXDES.2006.1706613","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706613","url":null,"abstract":"Die attach contribution to total thermal resistance can be a significant part of its final value. Material choice, bondline thickness, voiding and interface delamination are some of the key factors affecting attachment quality, while process variations may seriously impair the final heat transfer characteristics of finished devices. In this work, we introduce a fast method to monitor die attach interface in finished devices. The measurements are performed onto IGBT's, although the method may be used on any bipolar device by correct choice of measurement setup","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"46 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706550
B. Cheng, S. Roy, A. Asenov
Device parameter fluctuations - which arise from both the stochastic nature of the manufacturing process, and more fundamentally from the intrinsic discreteness of charge and matter - have become a dominant source of device mismatch in the deca-nanometer regime, and are recognised as a crucial bottleneck to the future yield and performance of circuits and systems. It is likely that a major shift from deterministic design styles to probabilistic design is unavoidable in order to tackle these challenges. Such a change in design style requires the use of statistical compact models, and corresponding techniques for their application. In this paper, a hierarchical device-to-circuit simulation methodology, which can investigate the impact of intrinsic parameter fluctuations on simple circuits has been presented, and its application is demonstrated using a number of examples. These include analyzing the impact of random doping fluctuations on the functionality and reliability of 6-transistor SRAM cells and low swing CMOS circuits. We posit this new approach as a starting point for the design of high quality cell libraries that contain the fluctuation information necessary for design under the constraints of intrinsic parameter fluctuations
{"title":"Impact Of Intrinsic Parameter Fluctuations On Deca-nanometer Circuits, And Circuit Modelling Techniques","authors":"B. Cheng, S. Roy, A. Asenov","doi":"10.1109/MIXDES.2006.1706550","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706550","url":null,"abstract":"Device parameter fluctuations - which arise from both the stochastic nature of the manufacturing process, and more fundamentally from the intrinsic discreteness of charge and matter - have become a dominant source of device mismatch in the deca-nanometer regime, and are recognised as a crucial bottleneck to the future yield and performance of circuits and systems. It is likely that a major shift from deterministic design styles to probabilistic design is unavoidable in order to tackle these challenges. Such a change in design style requires the use of statistical compact models, and corresponding techniques for their application. In this paper, a hierarchical device-to-circuit simulation methodology, which can investigate the impact of intrinsic parameter fluctuations on simple circuits has been presented, and its application is demonstrated using a number of examples. These include analyzing the impact of random doping fluctuations on the functionality and reliability of 6-transistor SRAM cells and low swing CMOS circuits. We posit this new approach as a starting point for the design of high quality cell libraries that contain the fluctuation information necessary for design under the constraints of intrinsic parameter fluctuations","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128457656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706661
J. Chlapinski, S. Marshall
This paper describes implementation for noise removal based on aperture operators. Aperture operators are a subclass of window operators used in automatic filter design. In this implementation, a typical improvement of 30-50% was observed with respect to MSE as compared to well-known median and adaptive Wiener filtering methods
{"title":"Aperture Filters Implementation For Noise Removal","authors":"J. Chlapinski, S. Marshall","doi":"10.1109/MIXDES.2006.1706661","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706661","url":null,"abstract":"This paper describes implementation for noise removal based on aperture operators. Aperture operators are a subclass of window operators used in automatic filter design. In this implementation, a typical improvement of 30-50% was observed with respect to MSE as compared to well-known median and adaptive Wiener filtering methods","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130848582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706545
D. Makowski, M. Grecki, B. Mukherjee, B. Świercz, S. Simrock, A. Napieralski
Bremsstrahlung gamma radiation and photoneutrons are produced during the operation of high energy linear accelerators. The functionality of electronic devices that are placed inside accelerator tunnels can be jeopardized because of the negative influence of generated radiation. Therefore, a radiation monitoring system able to gauge neutron fluence and gamma dose in real time was constructed. Radiation-sensitive dosimeters cooperate with a readout system. The readout continuously measures both types of radiation and sends quantified data to a main computer. The system is also placed in the tunnel, hence it must be insensitive to radiation or able to tolerate induced malfunctions. A few different readout systems were designed. This work presents the application of different readouts designed using commercial of the shelf (COTS) components. The presented hardware was tested with americium-beryllium neutron source. Finally, the systems were irradiated in a linear accelerator tunnel to estimate their immunity and suitability for a long-term reliable operation in the radioactive field
{"title":"The radiation tolerant readout system for srambased neutron detector","authors":"D. Makowski, M. Grecki, B. Mukherjee, B. Świercz, S. Simrock, A. Napieralski","doi":"10.1109/MIXDES.2006.1706545","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706545","url":null,"abstract":"Bremsstrahlung gamma radiation and photoneutrons are produced during the operation of high energy linear accelerators. The functionality of electronic devices that are placed inside accelerator tunnels can be jeopardized because of the negative influence of generated radiation. Therefore, a radiation monitoring system able to gauge neutron fluence and gamma dose in real time was constructed. Radiation-sensitive dosimeters cooperate with a readout system. The readout continuously measures both types of radiation and sends quantified data to a main computer. The system is also placed in the tunnel, hence it must be insensitive to radiation or able to tolerate induced malfunctions. A few different readout systems were designed. This work presents the application of different readouts designed using commercial of the shelf (COTS) components. The presented hardware was tested with americium-beryllium neutron source. Finally, the systems were irradiated in a linear accelerator tunnel to estimate their immunity and suitability for a long-term reliable operation in the radioactive field","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131926836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706679
M. Szpyrka
Using of formal methods at different stages in the embedded system development process may both increase the quality of developed software and reduce the cost of its testing and the debugging. However, formal methods are not widely used in industrial software development. Such a situation could be treated as a result of a lack of suitable tools for fast designing of models and its automatic verification. The presented approach is based on a class of Petri nets called RTCP-nets. The paper focuses on computer tools, that are being developed at AGH University of Science and Technology in Krakow, that support the design and verification of hierarchical RTCP-nets models. A short description of hierarchical RTCP-nets and a survey of main software features are presented in the paper
{"title":"Practical Aspects Of Development Of Embedded Systems With RTCP-nets And Adder Tools","authors":"M. Szpyrka","doi":"10.1109/MIXDES.2006.1706679","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706679","url":null,"abstract":"Using of formal methods at different stages in the embedded system development process may both increase the quality of developed software and reduce the cost of its testing and the debugging. However, formal methods are not widely used in industrial software development. Such a situation could be treated as a result of a lack of suitable tools for fast designing of models and its automatic verification. The presented approach is based on a class of Petri nets called RTCP-nets. The paper focuses on computer tools, that are being developed at AGH University of Science and Technology in Krakow, that support the design and verification of hierarchical RTCP-nets models. A short description of hierarchical RTCP-nets and a survey of main software features are presented in the paper","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133552630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706654
K. Górecki, J. Zarebski
In the paper a new method of an electrothermal analysis of DC-DC converters operating in the steady-state is proposed. This method is based on the elaborated by the authors' electrothermal average model of the diode-transistor switch. This model was verified by comparing SPICE simulated characteristics of the buck and boost converters operating both in the continuous and discontinuous conducting mode obtained by the proposed method and the electrothermal transient analysis
{"title":"Calculations Of Nonisothermal Characteristics Of DC-DC Converters With The Average Models Taken Into Account","authors":"K. Górecki, J. Zarebski","doi":"10.1109/MIXDES.2006.1706654","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706654","url":null,"abstract":"In the paper a new method of an electrothermal analysis of DC-DC converters operating in the steady-state is proposed. This method is based on the elaborated by the authors' electrothermal average model of the diode-transistor switch. This model was verified by comparing SPICE simulated characteristics of the buck and boost converters operating both in the continuous and discontinuous conducting mode obtained by the proposed method and the electrothermal transient analysis","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133756360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706609
A. Bukowiec, A. Barkalov
The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal possible number of bits. In this case only one decoder is used for implementation of the microoperations system. This method permits to minimize a number of outputs of the combinational part of Mealy FSM in comparison with the same characteristic of Mealy FSM with encoding of fields of compatible microoperations
{"title":"Verticalization Of Direct Structural Table In Synthesis Of Mealy FSMS For FPGAs","authors":"A. Bukowiec, A. Barkalov","doi":"10.1109/MIXDES.2006.1706609","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706609","url":null,"abstract":"The method of decreasing of amount of logic in FPGA device that implements the logic circuit of finite state machine (FSM) with Mealy outputs is proposed. Method is based on verticalization of microinstructions in direct structural table (DST). As a result of verticalization all microoperations of direct structural table are compatible ones. It permits to encode each microoperation by code with minimal possible number of bits. In this case only one decoder is used for implementation of the microoperations system. This method permits to minimize a number of outputs of the combinational part of Mealy FSM in comparison with the same characteristic of Mealy FSM with encoding of fields of compatible microoperations","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131269704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706608
R. Dlugosz, K. Iniewski
This paper reviews existing analog-to-digital converters (ADC) and compares them based on the power consumption metric. For applications where power consumption is of utmost importance, a novel 8-bit current mode Successive Approximation ADC (SAR) is proposed. Based on initial simulations made for CMOS 0.35 mum technology, it has been observed that the novel SAR architecture is very flexible i.e. it can be easily tuned to work with different frequencies and different power consumption values. In CMOS 0.35 mum technology the optimum frequency range is 25-350 kS/s, and power dissipation of the analog part of ADC ranges from 40 nW to 550 nW for 1 V power supply. The final post layout simulations of the chip designed in CMOS 0.18 mum technology were made for 0.55 V power supply. Entire (analog and digital circuits) SAR ADC working with the frequency of 250 kHz consumes only 580 nW
{"title":"Ultra Low Power Current-mode Algorithmic Analog-to-digital Converter Implemented In 0.18 /spl mu/m CMOS Technology For Wireless Sensor Network","authors":"R. Dlugosz, K. Iniewski","doi":"10.1109/MIXDES.2006.1706608","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706608","url":null,"abstract":"This paper reviews existing analog-to-digital converters (ADC) and compares them based on the power consumption metric. For applications where power consumption is of utmost importance, a novel 8-bit current mode Successive Approximation ADC (SAR) is proposed. Based on initial simulations made for CMOS 0.35 mum technology, it has been observed that the novel SAR architecture is very flexible i.e. it can be easily tuned to work with different frequencies and different power consumption values. In CMOS 0.35 mum technology the optimum frequency range is 25-350 kS/s, and power dissipation of the analog part of ADC ranges from 40 nW to 550 nW for 1 V power supply. The final post layout simulations of the chip designed in CMOS 0.18 mum technology were made for 0.55 V power supply. Entire (analog and digital circuits) SAR ADC working with the frequency of 250 kHz consumes only 580 nW","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133109410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-22DOI: 10.1109/MIXDES.2006.1706573
S. Soell, B. Porr
As negative feedback in control systems is often not applicable and/or produces undesirable effects, this paper presents an analysis and simulation of a finite impulse response (FIR) sigma delta A/D converter comprising of a voltage controlled oscillator (VCO) and D-flip-flop to digitize data. The FIR sigma delta modulator (SDM) is analyzed in terms of performance and simulation results are given. As an application example conventional condenser microphones are introduced and then improved upon utilizing the FIR sigma delta modulator. Proof-of-concept is given along with simulation results
由于负反馈在控制系统中往往不适用和/或产生不良影响，本文提出了一种由压控振荡器(VCO)和D触发器组成的有限脉冲响应(FIR) σ δ a /D转换器的分析和仿真。对FIR σ δ调制器(SDM)进行了性能分析，并给出了仿真结果。作为应用实例，介绍了传统的电容传声器，并利用FIR σ δ调制器对其进行了改进。给出了概念验证和仿真结果
{"title":"A VCO Based Digital Microphone Utilizing A FIR Sigma Delta Converter","authors":"S. Soell, B. Porr","doi":"10.1109/MIXDES.2006.1706573","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706573","url":null,"abstract":"As negative feedback in control systems is often not applicable and/or produces undesirable effects, this paper presents an analysis and simulation of a finite impulse response (FIR) sigma delta A/D converter comprising of a voltage controlled oscillator (VCO) and D-flip-flop to digitize data. The FIR sigma delta modulator (SDM) is analyzed in terms of performance and simulation results are given. As an application example conventional condenser microphones are introduced and then improved upon utilizing the FIR sigma delta modulator. Proof-of-concept is given along with simulation results","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131380576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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