Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520894
S. Takahashi, T. Onodera, Y. Hayashi, T. Kunio
A new 3-D MCM fabrication technology referred as "Vertically Connected Thin-film Chip (VCTC)" technology, has been developed. The VCTC process consists of chip thinning by CMP, the thinned-chip stacking by polyimide adhesive, and vertical interconnection formation by polyimide dry-etching and gold plating. From the SPICE simulation, short line length is a main factor to realize high-speed inter-chip communication with small delay, so the VCTC technology is effective on high-speed systems.
{"title":"A new 3-D MCM fabrication technology for high-speed chip-to-chip communication: vertically connected thin-film chip (VCTC) technology","authors":"S. Takahashi, T. Onodera, Y. Hayashi, T. Kunio","doi":"10.1109/VLSIT.1995.520894","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520894","url":null,"abstract":"A new 3-D MCM fabrication technology referred as \"Vertically Connected Thin-film Chip (VCTC)\" technology, has been developed. The VCTC process consists of chip thinning by CMP, the thinned-chip stacking by polyimide adhesive, and vertical interconnection formation by polyimide dry-etching and gold plating. From the SPICE simulation, short line length is a main factor to realize high-speed inter-chip communication with small delay, so the VCTC technology is effective on high-speed systems.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122124433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520868
R. Baumann, T. Hossain, E. Smith, S. Murata, H. Kitagawa
The interaction of cosmic ray thermal neutrons and boron is demonstrated as the primary source of radiation in devices containing borophosphosilicate glass (BPSG). Simulations indicated that this source of radiation generates enough charge to induce soft errors in memory devices. The results of a study of DRAM devices also demonstrated that this radiation is capable of inducing soft errors. A simple process change that significantly reduces this source of radiation is proposed.
{"title":"Boron as a primary source of radiation in high density DRAMs","authors":"R. Baumann, T. Hossain, E. Smith, S. Murata, H. Kitagawa","doi":"10.1109/VLSIT.1995.520868","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520868","url":null,"abstract":"The interaction of cosmic ray thermal neutrons and boron is demonstrated as the primary source of radiation in devices containing borophosphosilicate glass (BPSG). Simulations indicated that this source of radiation generates enough charge to induce soft errors in memory devices. The results of a study of DRAM devices also demonstrated that this radiation is capable of inducing soft errors. A simple process change that significantly reduces this source of radiation is proposed.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520851
M. Saito, Y. Kudoh, Y. Homma
A new pressure-controlled two-step TEOS-O/sub 3/ CVD has been developed to provide high quality SiO/sub 2/ films with flow-like step-coverage regardless of the underlying materials. Thin films, initially deposited under a low pressure but high O/sub 3/ concentration prior to the deposition of main films under sub/atmospheric pressure (AP), have as high quality as AP-TEOS-O/sub 3/ films, and eliminate the base material effect. Gap-filling for 0.2-/spl mu/m spaces with a high aspect ratio of 3.1 has been achieved.
{"title":"Pressure-controlled two-step TEOS-O/sub 3/ CVD eliminating the base material effect","authors":"M. Saito, Y. Kudoh, Y. Homma","doi":"10.1109/VLSIT.1995.520851","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520851","url":null,"abstract":"A new pressure-controlled two-step TEOS-O/sub 3/ CVD has been developed to provide high quality SiO/sub 2/ films with flow-like step-coverage regardless of the underlying materials. Thin films, initially deposited under a low pressure but high O/sub 3/ concentration prior to the deposition of main films under sub/atmospheric pressure (AP), have as high quality as AP-TEOS-O/sub 3/ films, and eliminate the base material effect. Gap-filling for 0.2-/spl mu/m spaces with a high aspect ratio of 3.1 has been achieved.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123318291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520845
T. Takewaki, T. Ohmi, T. Nitta
By exposing the giant-grain Cu interconnects in SiH/sub 4/ ambient at 200/spl deg/C and annealing it in Ar ambient at 450/spl deg/C, we have succeeded in performing self-aligned surface-silicide passivation on the Cu interconnects. The surface-silicide passivated giant-grain Cu interconnect exhibits one order of magnitude longer lifetime against electromigration than the non-passivated giant-grain Cu interconnect.
{"title":"A novel self-aligned surface-silicide passivation technology for reliability enhancement in copper interconnects","authors":"T. Takewaki, T. Ohmi, T. Nitta","doi":"10.1109/VLSIT.1995.520845","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520845","url":null,"abstract":"By exposing the giant-grain Cu interconnects in SiH/sub 4/ ambient at 200/spl deg/C and annealing it in Ar ambient at 450/spl deg/C, we have succeeded in performing self-aligned surface-silicide passivation on the Cu interconnects. The surface-silicide passivated giant-grain Cu interconnect exhibits one order of magnitude longer lifetime against electromigration than the non-passivated giant-grain Cu interconnect.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116894251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520860
D. Boulin, W. Mansfield, K. O'Connor, J. Bevk, D. Brasen, M. Cheng, R. Cirelli, S. Eshraghi, M. Green, K. Guinn, S. Hillenius, D. Ibbotson, D. Jacobson, Y.O. Kim, C. King, R. Kistler, F. Klemens, K. Krisch, A. Kornblit, J.T.-C. Lee, L. Manchanda, S. McNevin, S. Moccio, D. Monroe, K. Ng, M. O’Malley, C. Rafferty, G. Schwartz, S. Vaidya, G. Weber, L. Feldman, M. Pinto, T. Itani, T. Tounai, K. Kasama, H. Miyamoto, E. Ikawa, E. Hasagawa, A. Ishitani, H. Ito, T. Horiuchi, S. Saito, M. Nakamae
A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.
{"title":"A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography","authors":"D. Boulin, W. Mansfield, K. O'Connor, J. Bevk, D. Brasen, M. Cheng, R. Cirelli, S. Eshraghi, M. Green, K. Guinn, S. Hillenius, D. Ibbotson, D. Jacobson, Y.O. Kim, C. King, R. Kistler, F. Klemens, K. Krisch, A. Kornblit, J.T.-C. Lee, L. Manchanda, S. McNevin, S. Moccio, D. Monroe, K. Ng, M. O’Malley, C. Rafferty, G. Schwartz, S. Vaidya, G. Weber, L. Feldman, M. Pinto, T. Itani, T. Tounai, K. Kasama, H. Miyamoto, E. Ikawa, E. Hasagawa, A. Ishitani, H. Ito, T. Horiuchi, S. Saito, M. Nakamae","doi":"10.1109/VLSIT.1995.520860","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520860","url":null,"abstract":"A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124144502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520843
K. Ueno, K. Ohto, K. Tsunenari
Half-micron pitch Cu interconnections have been achieved by self-aligned plug (SAP), MOCVD-TiN barrier layer (MBL), and alumina capped oxidation-free structure (ACOS). Low resistance 0.12 /spl mu/m Cu interconnections whose effective resistivity is 1.9 /spl mu//spl Omega/cm have been obtained. Improved thermal stability up to 600/spl deg/C has been achieved for quarter-micron Cu contacts. Cu oxidation has been suppressed without increasing resistance by using a trimethylaluminum (TMA) treatment.
{"title":"A half-micron pitch Cu interconnection technology","authors":"K. Ueno, K. Ohto, K. Tsunenari","doi":"10.1109/VLSIT.1995.520843","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520843","url":null,"abstract":"Half-micron pitch Cu interconnections have been achieved by self-aligned plug (SAP), MOCVD-TiN barrier layer (MBL), and alumina capped oxidation-free structure (ACOS). Low resistance 0.12 /spl mu/m Cu interconnections whose effective resistivity is 1.9 /spl mu//spl Omega/cm have been obtained. Improved thermal stability up to 600/spl deg/C has been achieved for quarter-micron Cu contacts. Cu oxidation has been suppressed without increasing resistance by using a trimethylaluminum (TMA) treatment.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121140648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520850
T. Kosugi, H. Ishii, Y. Arita
We propose a new method to clean heavily-doped p/sup +/-Si surfaces by plasma hydrogenation prior to selective W CVD by using SiH/sub 4/ reduction. This cleaning technology reveals excellent characteristics: the improvement of W adhesion to p/sup +/-Si, low contact resistance, suppression of selectivity loss, and good controllability of Si consumption for p/sup +/- and n/sup +/-Si. Owing to this cleaning technology, we can obtain sufficiently low contact resistivities of 0.3 and 0.1 /spl mu//spl Omega/cm/sup 2/ for p/sup +/and n/sup +/ contacts for 1-/spl mu/m/sup 2/-W-cladding area, respectively. With the plasma hydrogenation cleaning and selective W CVD of SiH/sub 4/ reduction, Si consumption is suppressed to a low value below 14 nm for both types of silicon at 300/spl deg/C.
{"title":"Novel Si surface cleaning technology with plasma hydrogenation and its application to selective CVD-W clad layer formation","authors":"T. Kosugi, H. Ishii, Y. Arita","doi":"10.1109/VLSIT.1995.520850","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520850","url":null,"abstract":"We propose a new method to clean heavily-doped p/sup +/-Si surfaces by plasma hydrogenation prior to selective W CVD by using SiH/sub 4/ reduction. This cleaning technology reveals excellent characteristics: the improvement of W adhesion to p/sup +/-Si, low contact resistance, suppression of selectivity loss, and good controllability of Si consumption for p/sup +/- and n/sup +/-Si. Owing to this cleaning technology, we can obtain sufficiently low contact resistivities of 0.3 and 0.1 /spl mu//spl Omega/cm/sup 2/ for p/sup +/and n/sup +/ contacts for 1-/spl mu/m/sup 2/-W-cladding area, respectively. With the plasma hydrogenation cleaning and selective W CVD of SiH/sub 4/ reduction, Si consumption is suppressed to a low value below 14 nm for both types of silicon at 300/spl deg/C.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132674233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520898
H. Kim, Sang-Bo Lee, D. Choi, J. Shim, Kyu-Han Lee, Kyupil Lee, Kinam Kim, Jong-Woo Park
A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.
采用0.5 /spl μ l /m CMOS技术，在薄膜绝缘体(TFSOI)上制造出完全工作的16M DRAM。据我们所知，这是有史以来密度最高的SOI DRAM。引入LOCOS隔离和局部注入后场氧化(LIF)来抑制NMOS中的边缘晶体管效应。降低S/D注入过程中的n/sup +//p/sup +/剂量是抑制高密度TFSOI-DRAM在漏源击穿电压(BVds)升高的过程中缺陷产生的关键工艺。给出了TFSOI-DRAM在25/spl度/C时电源电压与TRAC的平滑图。在3.0 V Vcc下，RAS的访问时间TRAC为50 ns，比等效的大块硅器件快20%。
{"title":"A high performance 16M DRAM on a thin film SOI","authors":"H. Kim, Sang-Bo Lee, D. Choi, J. Shim, Kyu-Han Lee, Kyupil Lee, Kinam Kim, Jong-Woo Park","doi":"10.1109/VLSIT.1995.520898","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520898","url":null,"abstract":"A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123809998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520848
P. Gilbert, S. Sun
The integration of Poly-Encapsulated LOCOS (PELOX) into a high performance sub-0.5 /spl mu/m thin-film SOI technology is described. The 700 /spl Aring/ (per side) bird's beak encroachment of PELOX eliminates the need for a field implant and results in a significant reduction of the MOSFET narrow width effect. Partially-depleted N+/P+ dual poly gate MOSFET's with 70 /spl Aring/ Tox and 0.35 /spl mu/m Lpoly were fabricated with /spl les/1 /spl mu/m active/isolation pitch. A 40% reduction in power-delay product, compared to bulk CMOS, is achieved with a CMOS ring oscillator propagation-delay of 51 psec at 2 V supply voltage.
{"title":"A PELOX isolated sub-0.5 micron thin-film SOI technology","authors":"P. Gilbert, S. Sun","doi":"10.1109/VLSIT.1995.520848","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520848","url":null,"abstract":"The integration of Poly-Encapsulated LOCOS (PELOX) into a high performance sub-0.5 /spl mu/m thin-film SOI technology is described. The 700 /spl Aring/ (per side) bird's beak encroachment of PELOX eliminates the need for a field implant and results in a significant reduction of the MOSFET narrow width effect. Partially-depleted N+/P+ dual poly gate MOSFET's with 70 /spl Aring/ Tox and 0.35 /spl mu/m Lpoly were fabricated with /spl les/1 /spl mu/m active/isolation pitch. A 40% reduction in power-delay product, compared to bulk CMOS, is achieved with a CMOS ring oscillator propagation-delay of 51 psec at 2 V supply voltage.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134455352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520883
S.A. Ajuria, P. Tobin, B. Nguyen, Y. Limb, T. Mele
The in-situ furnace HCl-based Pyroclean has been shown to remove metallics from silicon surfaces with dramatic efficiency. This paper demonstrates for the first time that, while the Pyroclean effectively reduces initial gate oxide shorts, it can degrade the gate oxide charge-to-breakdown of isolation modules which have not been properly optimized. A comparison of three LOCOS isolation schemes suggests that the Pyroclean preferentially attacks stressed previously roughened silicon. Optimizing the isolation edge to reduce stress and roughness is shown to eliminate deleterious Pyrocleaning effects.
{"title":"Isolation dependence of gate oxide quality at the LOCOS edge using an in-situ HCl-based pre-gate Pyroclean","authors":"S.A. Ajuria, P. Tobin, B. Nguyen, Y. Limb, T. Mele","doi":"10.1109/VLSIT.1995.520883","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520883","url":null,"abstract":"The in-situ furnace HCl-based Pyroclean has been shown to remove metallics from silicon surfaces with dramatic efficiency. This paper demonstrates for the first time that, while the Pyroclean effectively reduces initial gate oxide shorts, it can degrade the gate oxide charge-to-breakdown of isolation modules which have not been properly optimized. A comparison of three LOCOS isolation schemes suggests that the Pyroclean preferentially attacks stressed previously roughened silicon. Optimizing the isolation edge to reduce stress and roughness is shown to eliminate deleterious Pyrocleaning effects.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133671462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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