Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520867
P. Agnello, T. Newman, E. Crabbé, S. Subbanna, É. Ganin, L. Liebmann, J. Comfort, D. Sunderland
In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.
{"title":"Phase edge lithography for sub 0.1 /spl mu/m electrical channel length in a 200 mm full CMOS process","authors":"P. Agnello, T. Newman, E. Crabbé, S. Subbanna, É. Ganin, L. Liebmann, J. Comfort, D. Sunderland","doi":"10.1109/VLSIT.1995.520867","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520867","url":null,"abstract":"In this work a deep-UV stepper is used in conjunction with a phase edge mask to define sub 0.1 /spl mu/m electrical channel length gates in a 200 mm integrated CMOS process. Conventional binary intensity mask deep-UV and mid-UV lithography are other used for other levels. We demonstrate excellent channel length control with the phase edge technique, at channel lengths here-to-fore only achievable by e-beam or X-ray lithography.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134428917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520863
M. Saito, M. Ono, R. Fujimoto, C. Takahashi, H. Tanimoto, N. Ito, T. Ohguro, T. Yoshitomi, H. Momose, H. Iwai
Low noise high-frequency analog operation of small geometry silicon MOSFETs is demonstrated. By scaling gate length down to 0.3-sub 0.1 /spl mu/m regions, excellent low noise figure of 1.5 dB at 2 GHz was obtained with low drain current of 0.3 mA//spl mu/m at f/sub T/ value of 20-65 GHz-the same level as today's high performance silicon bipolar transistors in research level. Even at low voltage operation such as 0.5 V, extremely high cutoff frequency of 48 GHz was realized by sub 0.1 /spl mu/m gate length nMOSFETs. Such low voltage operations allow one order of magnitude smaller power consumption compared with 2 V power supply voltage.
{"title":"Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5 V","authors":"M. Saito, M. Ono, R. Fujimoto, C. Takahashi, H. Tanimoto, N. Ito, T. Ohguro, T. Yoshitomi, H. Momose, H. Iwai","doi":"10.1109/VLSIT.1995.520863","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520863","url":null,"abstract":"Low noise high-frequency analog operation of small geometry silicon MOSFETs is demonstrated. By scaling gate length down to 0.3-sub 0.1 /spl mu/m regions, excellent low noise figure of 1.5 dB at 2 GHz was obtained with low drain current of 0.3 mA//spl mu/m at f/sub T/ value of 20-65 GHz-the same level as today's high performance silicon bipolar transistors in research level. Even at low voltage operation such as 0.5 V, extremely high cutoff frequency of 48 GHz was realized by sub 0.1 /spl mu/m gate length nMOSFETs. Such low voltage operations allow one order of magnitude smaller power consumption compared with 2 V power supply voltage.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114511326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520846
M. Horiuchi, T. Teshima, K. Tokumasu, K. Yamaguchi
An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.
{"title":"High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: /spl Psi/) SOI wafer","authors":"M. Horiuchi, T. Teshima, K. Tokumasu, K. Yamaguchi","doi":"10.1109/VLSIT.1995.520846","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520846","url":null,"abstract":"An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115098668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520891
G. Hemink, T. Tanaka, T. Endoh, S. Aritome, R. Shirota
For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.
{"title":"Fast and accurate programming method for multi-level NAND EEPROMs","authors":"G. Hemink, T. Tanaka, T. Endoh, S. Aritome, R. Shirota","doi":"10.1109/VLSIT.1995.520891","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520891","url":null,"abstract":"For the replacement of conventional hard disks by NAND EEPROMs, a very high density and a high programming speed are required. An increased density can be achieved by using multi-level memory cells. With the new method, using staircase programming pulses combined with a bit-by-bit verify, a very narrow threshold voltage distribution of 0.7 V, necessary for 4-level or 2-bit operation, and a high programming speed of 300 /spl mu/s/page or 590 ns/byte can be obtained.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134613729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520896
W. Krautschneider, F. Hofmann, E. Ruderer, L. Risch
A dynamic gain memory cell has been fabricated which, despite its planar design, can compete with the area requirements of one transistor DRAM cells (1T-cells) built in trench or 3D stacked technology. The described gain cell can be geometrically shrunk because the drain current of scaled down MOS transistors increases resulting in higher signal charge. Another attractive feature of the proposed gain memory cell is that it can be fabricated using a CMOS logic process to bridge the gap between DRAM and CMOS logic technology. Because of its inherent amplification, the gain cell delivers even at supply voltages below 2 V sufficient signal charge making it suitable for low voltage applications.
{"title":"Planar gain cell for low voltage operation and gigabit memories","authors":"W. Krautschneider, F. Hofmann, E. Ruderer, L. Risch","doi":"10.1109/VLSIT.1995.520896","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520896","url":null,"abstract":"A dynamic gain memory cell has been fabricated which, despite its planar design, can compete with the area requirements of one transistor DRAM cells (1T-cells) built in trench or 3D stacked technology. The described gain cell can be geometrically shrunk because the drain current of scaled down MOS transistors increases resulting in higher signal charge. Another attractive feature of the proposed gain memory cell is that it can be fabricated using a CMOS logic process to bridge the gap between DRAM and CMOS logic technology. Because of its inherent amplification, the gain cell delivers even at supply voltages below 2 V sufficient signal charge making it suitable for low voltage applications.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"259 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133138006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520865
G. Thakar, S. Madan, C. Garza, W.L. Krisa, P. Nicollian, J.L. Wise, C. Lee, J. McKee, A. Appel, A. Esquivel, V.M. McNeil, D. Prinslow, B. Riemenschneider, T. Utsumi, R. Eklund, R. Chapman
TiN or organic Bottom AntiReflection Coatings (BARC), polysilicon hammerheads, phase shift masks, quadrupole off-axis illumination I-line lithography at N.A.=0.60, shallow source/drain extenders, LOCOS isolation, and 6 nm gate oxide are used to obtain high performance 0.30 /spl mu/m 2.5 V CMOS with effective channel lengths <0.20 /spl mu/m. The use of BARC reduces off current and improves PMOS hot carrier reliability.
采用TiN或有机底部抗反射涂层(BARC)、多晶硅锤头、相移掩模、四极离轴照明i线光刻(N.A.=0.60)、浅源/漏极扩展器、LOCOS隔离和6 nm栅氧化物，获得了有效通道长度<0.20 /spl mu/m的高性能0.30 /spl mu/m 2.5 V CMOS。BARC的使用减少了关闭电流，提高了PMOS热载流子的可靠性。
{"title":"High performance 0.3 /spl mu/m CMOS using I-line lithography and BARC","authors":"G. Thakar, S. Madan, C. Garza, W.L. Krisa, P. Nicollian, J.L. Wise, C. Lee, J. McKee, A. Appel, A. Esquivel, V.M. McNeil, D. Prinslow, B. Riemenschneider, T. Utsumi, R. Eklund, R. Chapman","doi":"10.1109/VLSIT.1995.520865","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520865","url":null,"abstract":"TiN or organic Bottom AntiReflection Coatings (BARC), polysilicon hammerheads, phase shift masks, quadrupole off-axis illumination I-line lithography at N.A.=0.60, shallow source/drain extenders, LOCOS isolation, and 6 nm gate oxide are used to obtain high performance 0.30 /spl mu/m 2.5 V CMOS with effective channel lengths <0.20 /spl mu/m. The use of BARC reduces off current and improves PMOS hot carrier reliability.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520864
T. Ong, B. Roman, W. Paulson, J. Lin, C. King, J. Hayden, Y. Ku, C. Fu, M. Luo, C. Philbin, M. Rossow, T. Mele, K. Kemp
This paper reports the investigation of low pressure chemical vapor deposition of SiN/sub X/ film for bottom antireflective coating (BARC) application in 0.35 /spl mu/m lithography and below. The SiN/sub X/ material was successfully designed to provide excellent anti-reflective layer which meets various advanced device integration requirements. This BARC process has been found to be manufacturable for deep-UV and I-line lithography.
{"title":"CVD SiN/sub X/ anti-reflective coating for sub-0.5 /spl mu/m lithography","authors":"T. Ong, B. Roman, W. Paulson, J. Lin, C. King, J. Hayden, Y. Ku, C. Fu, M. Luo, C. Philbin, M. Rossow, T. Mele, K. Kemp","doi":"10.1109/VLSIT.1995.520864","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520864","url":null,"abstract":"This paper reports the investigation of low pressure chemical vapor deposition of SiN/sub X/ film for bottom antireflective coating (BARC) application in 0.35 /spl mu/m lithography and below. The SiN/sub X/ material was successfully designed to provide excellent anti-reflective layer which meets various advanced device integration requirements. This BARC process has been found to be manufacturable for deep-UV and I-line lithography.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114190343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520890
R. Khamankar, B. Jiang, R. Tsu, W. Hsu, J. Nulman, S. Summerfelt, M. Anthony, J. Lee
BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.
{"title":"A novel low-temperature process for high dielectric constant BST thin films for ULSI DRAM applications","authors":"R. Khamankar, B. Jiang, R. Tsu, W. Hsu, J. Nulman, S. Summerfelt, M. Anthony, J. Lee","doi":"10.1109/VLSIT.1995.520890","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520890","url":null,"abstract":"BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116001311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520873
W. Frank
The photoresist selectivity is known to increase by changing from chlorine- to bromine-based etchants. Therefore, skipping to iodine-based etchants should result in further enhancement of photoresist selectivity. This is corroborated by a very high photoresist selectivity of the iodine-based etchant HI. Since HI is also the only iodine containing compound with a sufficient vapor pressure for plasma etching, HI should be the etchant of choice for a new aluminum etch process.
{"title":"Metal etch with HI-addition to conventional chemistry","authors":"W. Frank","doi":"10.1109/VLSIT.1995.520873","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520873","url":null,"abstract":"The photoresist selectivity is known to increase by changing from chlorine- to bromine-based etchants. Therefore, skipping to iodine-based etchants should result in further enhancement of photoresist selectivity. This is corroborated by a very high photoresist selectivity of the iodine-based etchant HI. Since HI is also the only iodine containing compound with a sufficient vapor pressure for plasma etching, HI should be the etchant of choice for a new aluminum etch process.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130686548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520847
M. Terauchi, M. Yoshimi, A. Marakoshi, Y. Ushiku
The floating-body effects, which are regarded as the most critical issues in applying Silicon-On-Insulator (SOI) devices to actual LSIs, can be suppressed by the reduction in bandgap energy in the source region. In addition to an increase in the drain breakdown voltage, the suppression of both kinks in I/sub d/-V/sub d/ characteristics and threshold voltage shift with an increase in drain voltage are achieved in sub-quarter micron Nch thin-film SOI MOSFETs.
{"title":"Suppression of the floating-body effects in SOI MOSFETs by bandgap engineering","authors":"M. Terauchi, M. Yoshimi, A. Marakoshi, Y. Ushiku","doi":"10.1109/VLSIT.1995.520847","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520847","url":null,"abstract":"The floating-body effects, which are regarded as the most critical issues in applying Silicon-On-Insulator (SOI) devices to actual LSIs, can be suppressed by the reduction in bandgap energy in the source region. In addition to an increase in the drain breakdown voltage, the suppression of both kinks in I/sub d/-V/sub d/ characteristics and threshold voltage shift with an increase in drain voltage are achieved in sub-quarter micron Nch thin-film SOI MOSFETs.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122089533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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