Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520895
M. Noguchi, T. Ozaki, M. Aoki, T. Hamamoto, M. Habu, Y. Kato, Y. Takigami, T. Shibata, T. Nakasugi, H. Niiyama, K. Tokano, Y. Saito, T. Hoshi, S. Watanabe
We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.
{"title":"0.29-/spl mu/m/sup 2/ trench cell technologies for 1G-bit DRAMs with open/folded-bit-line layout and selective growth technique","authors":"M. Noguchi, T. Ozaki, M. Aoki, T. Hamamoto, M. Habu, Y. Kato, Y. Takigami, T. Shibata, T. Nakasugi, H. Niiyama, K. Tokano, Y. Saito, T. Hoshi, S. Watanabe","doi":"10.1109/VLSIT.1995.520895","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520895","url":null,"abstract":"We present substrate-plate-trench cell technologies for 1G-bit DRAMs. With an open/folded-bit-line layout, the smallest cell area of 0.29 /spl mu/m/sup 2/ was realized for a 0.20 /spl mu/m design rule. A pause time of 4.2 s at 85/spl deg/C and an activation energy of 0.70 eV were achieved for a 0.25-/spl mu/m/spl Phi//spl times/4-/spl mu/m trench capacitor. A new Si selective epitaxial growth (SEG) technique was developed to reduce connection formation between the capacitor and transistor to one fabrication step, and also reduce a distance between the trench and gate. The gate capacitors on the SEG showed a breakdown electric field over 11 MV/cm even when the distance was less than 0.1 /spl mu/m.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126700327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520897
F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, T. Nishimura
SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.
{"title":"Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM","authors":"F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, T. Nishimura","doi":"10.1109/VLSIT.1995.520897","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520897","url":null,"abstract":"SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520859
B. Maiti, P. Tobin, Y. Okada, S. Ajuria, K. Reid, R. Hegde, V. Kaushik
Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied for the first time. This process results in a striking enhancement of both gate and substrate injection Q/sub BD/ by /spl sim/3-5X for active edge intensive capacitors in comparison to thermal oxide, N/sub 2/O and NO oxynitride. This improvement is attributed to reduction of mechanical stress at the active edge which leads to less local thinning of gate oxide at the field oxide edge and reduction of the local build-up of positive charge near the gate electrode at the isolation edges. Drive current of n- and p-MOSFETs with ReoxNO oxynitride is also compared to other dielectrics.
本文首次研究了热氧化物NO退火生长的氮化氧栅极介质的再氧化。与热氧化物、N/sub 2/O和NO氮化物相比，该工艺显著增强了有源边缘密集电容器的栅极和衬底注入Q/sub / BD/ by /spl sim/3-5X。这一改进归因于活性边缘的机械应力的减少，这导致在场氧化物边缘的栅氧化物局部变薄较少，并且减少了在隔离边缘的栅电极附近的正电荷的局部积聚。并与其它介质进行了比较。
{"title":"Reoxidized nitric oxide (ReoxNO) process and its effect on the dielectric reliability of the LOCOS edge","authors":"B. Maiti, P. Tobin, Y. Okada, S. Ajuria, K. Reid, R. Hegde, V. Kaushik","doi":"10.1109/VLSIT.1995.520859","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520859","url":null,"abstract":"Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied for the first time. This process results in a striking enhancement of both gate and substrate injection Q/sub BD/ by /spl sim/3-5X for active edge intensive capacitors in comparison to thermal oxide, N/sub 2/O and NO oxynitride. This improvement is attributed to reduction of mechanical stress at the active edge which leads to less local thinning of gate oxide at the field oxide edge and reduction of the local build-up of positive charge near the gate electrode at the isolation edges. Drive current of n- and p-MOSFETs with ReoxNO oxynitride is also compared to other dielectrics.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134523686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520842
A.V. Gelatos, B. Nguyen, K. Perry, R. Marsh, J. Peschke, S. Filipiak, E. Travis, N. Bhat, L. La, M. Thompson, T. Saaranen, P. Tobin
The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric breakdown, gate oxide interface state generation, temperature dependent reverse diode leakage, and hot carrier injection are used to demonstrate that, under standard backend processing conditions, copper does not degrade device performance.
{"title":"Copper integration into 0.5 /spl mu/m BiCMOS technology","authors":"A.V. Gelatos, B. Nguyen, K. Perry, R. Marsh, J. Peschke, S. Filipiak, E. Travis, N. Bhat, L. La, M. Thompson, T. Saaranen, P. Tobin","doi":"10.1109/VLSIT.1995.520842","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520842","url":null,"abstract":"The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric breakdown, gate oxide interface state generation, temperature dependent reverse diode leakage, and hot carrier injection are used to demonstrate that, under standard backend processing conditions, copper does not degrade device performance.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133894913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520870
M. Sharma, J. Campbell, H. Choe, C. Kuo, E. Prinz, R. Raghunathan, P. Gardner, L. Avery
The paper describes a robust scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using a novel (low voltage) zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET. The devices are implemented in state of the art, 3.3 V, 0.5 /spl mu/m feature site dual-poly, full-SALICIDE technology. The trigger and holding voltages of the described ESD protection elements are tunable over wide operating ranges and the devices trigger consistently and predictably at pre-determined values suitable for sub-micron technologies. The effectiveness of this methodology in providing ESD protection up to 15 kV is successfully demonstrated.
{"title":"An ESD protection scheme for deep sub-micron ULSI circuits","authors":"M. Sharma, J. Campbell, H. Choe, C. Kuo, E. Prinz, R. Raghunathan, P. Gardner, L. Avery","doi":"10.1109/VLSIT.1995.520870","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520870","url":null,"abstract":"The paper describes a robust scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using a novel (low voltage) zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET. The devices are implemented in state of the art, 3.3 V, 0.5 /spl mu/m feature site dual-poly, full-SALICIDE technology. The trigger and holding voltages of the described ESD protection elements are tunable over wide operating ranges and the devices trigger consistently and predictably at pre-determined values suitable for sub-micron technologies. The effectiveness of this methodology in providing ESD protection up to 15 kV is successfully demonstrated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520856
K. Fujii, K. Kikuta, T. Kikkawa
A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.
{"title":"Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering","authors":"K. Fujii, K. Kikuta, T. Kikkawa","doi":"10.1109/VLSIT.1995.520856","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520856","url":null,"abstract":"A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520861
H. Nakamura, T. Horiuchi
A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.
{"title":"A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process","authors":"H. Nakamura, T. Horiuchi","doi":"10.1109/VLSIT.1995.520861","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520861","url":null,"abstract":"A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520851
M. Saito, Y. Kudoh, Y. Homma
A new pressure-controlled two-step TEOS-O/sub 3/ CVD has been developed to provide high quality SiO/sub 2/ films with flow-like step-coverage regardless of the underlying materials. Thin films, initially deposited under a low pressure but high O/sub 3/ concentration prior to the deposition of main films under sub/atmospheric pressure (AP), have as high quality as AP-TEOS-O/sub 3/ films, and eliminate the base material effect. Gap-filling for 0.2-/spl mu/m spaces with a high aspect ratio of 3.1 has been achieved.
{"title":"Pressure-controlled two-step TEOS-O/sub 3/ CVD eliminating the base material effect","authors":"M. Saito, Y. Kudoh, Y. Homma","doi":"10.1109/VLSIT.1995.520851","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520851","url":null,"abstract":"A new pressure-controlled two-step TEOS-O/sub 3/ CVD has been developed to provide high quality SiO/sub 2/ films with flow-like step-coverage regardless of the underlying materials. Thin films, initially deposited under a low pressure but high O/sub 3/ concentration prior to the deposition of main films under sub/atmospheric pressure (AP), have as high quality as AP-TEOS-O/sub 3/ films, and eliminate the base material effect. Gap-filling for 0.2-/spl mu/m spaces with a high aspect ratio of 3.1 has been achieved.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123318291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520894
S. Takahashi, T. Onodera, Y. Hayashi, T. Kunio
A new 3-D MCM fabrication technology referred as "Vertically Connected Thin-film Chip (VCTC)" technology, has been developed. The VCTC process consists of chip thinning by CMP, the thinned-chip stacking by polyimide adhesive, and vertical interconnection formation by polyimide dry-etching and gold plating. From the SPICE simulation, short line length is a main factor to realize high-speed inter-chip communication with small delay, so the VCTC technology is effective on high-speed systems.
{"title":"A new 3-D MCM fabrication technology for high-speed chip-to-chip communication: vertically connected thin-film chip (VCTC) technology","authors":"S. Takahashi, T. Onodera, Y. Hayashi, T. Kunio","doi":"10.1109/VLSIT.1995.520894","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520894","url":null,"abstract":"A new 3-D MCM fabrication technology referred as \"Vertically Connected Thin-film Chip (VCTC)\" technology, has been developed. The VCTC process consists of chip thinning by CMP, the thinned-chip stacking by polyimide adhesive, and vertical interconnection formation by polyimide dry-etching and gold plating. From the SPICE simulation, short line length is a main factor to realize high-speed inter-chip communication with small delay, so the VCTC technology is effective on high-speed systems.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122124433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520860
D. Boulin, W. Mansfield, K. O'Connor, J. Bevk, D. Brasen, M. Cheng, R. Cirelli, S. Eshraghi, M. Green, K. Guinn, S. Hillenius, D. Ibbotson, D. Jacobson, Y.O. Kim, C. King, R. Kistler, F. Klemens, K. Krisch, A. Kornblit, J.T.-C. Lee, L. Manchanda, S. McNevin, S. Moccio, D. Monroe, K. Ng, M. O’Malley, C. Rafferty, G. Schwartz, S. Vaidya, G. Weber, L. Feldman, M. Pinto, T. Itani, T. Tounai, K. Kasama, H. Miyamoto, E. Ikawa, E. Hasagawa, A. Ishitani, H. Ito, T. Horiuchi, S. Saito, M. Nakamae
A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.
{"title":"A symmetric 0.25 /spl mu/m CMOS technology for low-power, high-performance ASIC applications using 248 nm DUV lithography","authors":"D. Boulin, W. Mansfield, K. O'Connor, J. Bevk, D. Brasen, M. Cheng, R. Cirelli, S. Eshraghi, M. Green, K. Guinn, S. Hillenius, D. Ibbotson, D. Jacobson, Y.O. Kim, C. King, R. Kistler, F. Klemens, K. Krisch, A. Kornblit, J.T.-C. Lee, L. Manchanda, S. McNevin, S. Moccio, D. Monroe, K. Ng, M. O’Malley, C. Rafferty, G. Schwartz, S. Vaidya, G. Weber, L. Feldman, M. Pinto, T. Itani, T. Tounai, K. Kasama, H. Miyamoto, E. Ikawa, E. Hasagawa, A. Ishitani, H. Ito, T. Horiuchi, S. Saito, M. Nakamae","doi":"10.1109/VLSIT.1995.520860","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520860","url":null,"abstract":"A 0.25 /spl mu/m coded feature CMOS technology has been developed for high-performance, low-power ASIC applications. Critical process features include 248 nm DUV lithography on all levels, profiled twin tubs by high energy implantation (HEI), dual TiN/polysilicon gates with low resistance on minimum size lines, rapid thermal (RT) N/sub 2/O grown 5.5 nm gate dielectrics, and planarized multi-level interconnect. Transistors are demonstrated with symmetric thresholds and excellent short-channel characteristics down to channel lengths of 0.18 /spl mu/m. Fabricated circuits operate down to <1 V supplies, with <20 ps ring oscillator gate delays achieved for 0.2 /spl mu/m gate devices, a record for stepper-based lithography with conventional resist processing.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124144502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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