Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520832
G. Inoue, S. Asakura, M. Iiri
Yield and device monitoring during the production rather than at the end of the whole processes on final chips may also be more commonly practised for the earlier detection of failures. In-situ monitoring with single wafer processing may be used for finer process control. To reduce the ever increasing cost of clean rooms including the running cost, mini environment technologies will be applied more to production in clean rooms. Material handling automation will be essential for dealing with heavy load of larger wafers. To share the higher investment for equipment and facilities, international alliances among foreign companies will be accelerated, and production environment needs to be global. Technology trends toward the year 2000 are shown. The role of CIM systems in the semiconductor industry has become increasingly important for dealing with new technologies as well as with their difficulties. Their importance and expected roles are discussed.
{"title":"Semiconductor CIM system, innovation toward the year 2000","authors":"G. Inoue, S. Asakura, M. Iiri","doi":"10.1109/VLSIT.1995.520832","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520832","url":null,"abstract":"Yield and device monitoring during the production rather than at the end of the whole processes on final chips may also be more commonly practised for the earlier detection of failures. In-situ monitoring with single wafer processing may be used for finer process control. To reduce the ever increasing cost of clean rooms including the running cost, mini environment technologies will be applied more to production in clean rooms. Material handling automation will be essential for dealing with heavy load of larger wafers. To share the higher investment for equipment and facilities, international alliances among foreign companies will be accelerated, and production environment needs to be global. Technology trends toward the year 2000 are shown. The role of CIM systems in the semiconductor industry has become increasingly important for dealing with new technologies as well as with their difficulties. Their importance and expected roles are discussed.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520859
B. Maiti, P. Tobin, Y. Okada, S. Ajuria, K. Reid, R. Hegde, V. Kaushik
Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied for the first time. This process results in a striking enhancement of both gate and substrate injection Q/sub BD/ by /spl sim/3-5X for active edge intensive capacitors in comparison to thermal oxide, N/sub 2/O and NO oxynitride. This improvement is attributed to reduction of mechanical stress at the active edge which leads to less local thinning of gate oxide at the field oxide edge and reduction of the local build-up of positive charge near the gate electrode at the isolation edges. Drive current of n- and p-MOSFETs with ReoxNO oxynitride is also compared to other dielectrics.
本文首次研究了热氧化物NO退火生长的氮化氧栅极介质的再氧化。与热氧化物、N/sub 2/O和NO氮化物相比，该工艺显著增强了有源边缘密集电容器的栅极和衬底注入Q/sub / BD/ by /spl sim/3-5X。这一改进归因于活性边缘的机械应力的减少，这导致在场氧化物边缘的栅氧化物局部变薄较少，并且减少了在隔离边缘的栅电极附近的正电荷的局部积聚。并与其它介质进行了比较。
{"title":"Reoxidized nitric oxide (ReoxNO) process and its effect on the dielectric reliability of the LOCOS edge","authors":"B. Maiti, P. Tobin, Y. Okada, S. Ajuria, K. Reid, R. Hegde, V. Kaushik","doi":"10.1109/VLSIT.1995.520859","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520859","url":null,"abstract":"Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied for the first time. This process results in a striking enhancement of both gate and substrate injection Q/sub BD/ by /spl sim/3-5X for active edge intensive capacitors in comparison to thermal oxide, N/sub 2/O and NO oxynitride. This improvement is attributed to reduction of mechanical stress at the active edge which leads to less local thinning of gate oxide at the field oxide edge and reduction of the local build-up of positive charge near the gate electrode at the isolation edges. Drive current of n- and p-MOSFETs with ReoxNO oxynitride is also compared to other dielectrics.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134523686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520897
F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, T. Nishimura
SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.
{"title":"Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM","authors":"F. Morishita, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, T. Nishimura","doi":"10.1109/VLSIT.1995.520897","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520897","url":null,"abstract":"SOI-DRAM is expected to have long data retention time because the data leakage path is limited only through a cell transistor. High speed low power operation is realized due to reduced junction capacitances. Moreover, since the capacitance ratio Cb/Cs is reduced, the read out signal amplitude increases. For these reasons SOI is well suited to low power supply voltage DRAMs. However, because SOI uses body-floating transistors for memory cells, there is a possibility that majority carriers within the floating body can cause problems. To date, only the static data retention characteristics have been reported, with nothing written about the dynamic data retention characteristics for full DRAM operation. This paper details the results of an analysis of the floating body caused leakage mechanism and its effect on dynamic data retention. A proposal is made to obtain superior dynamic data retention time.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520870
M. Sharma, J. Campbell, H. Choe, C. Kuo, E. Prinz, R. Raghunathan, P. Gardner, L. Avery
The paper describes a robust scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using a novel (low voltage) zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET. The devices are implemented in state of the art, 3.3 V, 0.5 /spl mu/m feature site dual-poly, full-SALICIDE technology. The trigger and holding voltages of the described ESD protection elements are tunable over wide operating ranges and the devices trigger consistently and predictably at pre-determined values suitable for sub-micron technologies. The effectiveness of this methodology in providing ESD protection up to 15 kV is successfully demonstrated.
{"title":"An ESD protection scheme for deep sub-micron ULSI circuits","authors":"M. Sharma, J. Campbell, H. Choe, C. Kuo, E. Prinz, R. Raghunathan, P. Gardner, L. Avery","doi":"10.1109/VLSIT.1995.520870","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520870","url":null,"abstract":"The paper describes a robust scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using a novel (low voltage) zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET. The devices are implemented in state of the art, 3.3 V, 0.5 /spl mu/m feature site dual-poly, full-SALICIDE technology. The trigger and holding voltages of the described ESD protection elements are tunable over wide operating ranges and the devices trigger consistently and predictably at pre-determined values suitable for sub-micron technologies. The effectiveness of this methodology in providing ESD protection up to 15 kV is successfully demonstrated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"349 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133104937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520842
A.V. Gelatos, B. Nguyen, K. Perry, R. Marsh, J. Peschke, S. Filipiak, E. Travis, N. Bhat, L. La, M. Thompson, T. Saaranen, P. Tobin
The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric breakdown, gate oxide interface state generation, temperature dependent reverse diode leakage, and hot carrier injection are used to demonstrate that, under standard backend processing conditions, copper does not degrade device performance.
{"title":"Copper integration into 0.5 /spl mu/m BiCMOS technology","authors":"A.V. Gelatos, B. Nguyen, K. Perry, R. Marsh, J. Peschke, S. Filipiak, E. Travis, N. Bhat, L. La, M. Thompson, T. Saaranen, P. Tobin","doi":"10.1109/VLSIT.1995.520842","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520842","url":null,"abstract":"The report describes the integration of copper into the backend of a two-level metal 0.5 /spl mu/m BiCMOS SRAM circuit. The circuit is used to evaluate the impact of copper on the device characteristics. The results of time dependent gate dielectric breakdown, gate oxide interface state generation, temperature dependent reverse diode leakage, and hot carrier injection are used to demonstrate that, under standard backend processing conditions, copper does not degrade device performance.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133894913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520861
H. Nakamura, T. Horiuchi
A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.
{"title":"A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process","authors":"H. Nakamura, T. Horiuchi","doi":"10.1109/VLSIT.1995.520861","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520861","url":null,"abstract":"A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520856
K. Fujii, K. Kikuta, T. Kikkawa
A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.
{"title":"Sub-quarter micron titanium salicide technology with in-situ silicidation using high-temperature sputtering","authors":"K. Fujii, K. Kikuta, T. Kikkawa","doi":"10.1109/VLSIT.1995.520856","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520856","url":null,"abstract":"A new titanium (Ti) salicide technology with in-situ silicidation using high-temperature sputtering has been developed. This process enhances TiSi/sub 2/ phase transition from C49 to C54 without agglomeration, which results in achieving silicidation in 0.2 /spl mu/m gates and 0.4 /spl mu/m diffusion layers. A sheet resistance less than 6/spl Omega///spl square/ can be obtained for both n/sup +/ and p/sup +/ silicide gates. CMOS transistors having 0.09 /spl mu/m effective channel length were successfully formed using the in-situ silicidation technique.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129650685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520881
X.W. Wang, Y. Shi, T. Ma, G. Cui, T. Tamagawa, J. Golz, B.L. Halpen, J. Schmitt
Theoretical calculations indicate that the tunneling currents in silicon nitride or oxynitride are greatly reduced compared to those in SiO/sub 2/ for equivalent oxide thicknesses (EOT) below 4 nm. Experimental results obtained on Jet Vapor Deposited (JVD) nitrides/oxynitrides are shown to verify the theoretical trend. These results suggest that extending the scaling limit well below 4 nm of EOT is possible with the JVD nitride.
{"title":"Extending gate dielectric scaling limit by use of nitride or oxynitride","authors":"X.W. Wang, Y. Shi, T. Ma, G. Cui, T. Tamagawa, J. Golz, B.L. Halpen, J. Schmitt","doi":"10.1109/VLSIT.1995.520881","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520881","url":null,"abstract":"Theoretical calculations indicate that the tunneling currents in silicon nitride or oxynitride are greatly reduced compared to those in SiO/sub 2/ for equivalent oxide thicknesses (EOT) below 4 nm. Experimental results obtained on Jet Vapor Deposited (JVD) nitrides/oxynitrides are shown to verify the theoretical trend. These results suggest that extending the scaling limit well below 4 nm of EOT is possible with the JVD nitride.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520889
K. Torii, H. Kawakami, K. Kushida, F. Yano, Y. Ohji
Thin films of Pb-based ferroelectric materials have attracted much attention because of the potential use as the dielectric in the storage capacitors of 1 Gb DRAMs. Sputtering, sol-gel, pulsed laser deposition, and metal organic chemical vapor deposition are widely used for ferroelectric film preparation; but there have been few reports using vacuum evaporation. This may be because lead has a low affinity for oxygen and high volatility. We can overcome these problems by employing high-concentration ozone. The thickness scaling of ferroelectric lead zirconate titanate (PZT) thin films by reactive evaporation is investigated.
{"title":"Ultra-thin fatigue free lead zirconate titanate thin films for gigabit DRAMs","authors":"K. Torii, H. Kawakami, K. Kushida, F. Yano, Y. Ohji","doi":"10.1109/VLSIT.1995.520889","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520889","url":null,"abstract":"Thin films of Pb-based ferroelectric materials have attracted much attention because of the potential use as the dielectric in the storage capacitors of 1 Gb DRAMs. Sputtering, sol-gel, pulsed laser deposition, and metal organic chemical vapor deposition are widely used for ferroelectric film preparation; but there have been few reports using vacuum evaporation. This may be because lead has a low affinity for oxygen and high volatility. We can overcome these problems by employing high-concentration ozone. The thickness scaling of ferroelectric lead zirconate titanate (PZT) thin films by reactive evaporation is investigated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520833
Z. Lemnios
SOI is an attractive technology option for low power, high performance semiconductors. A number of breakthroughs and developments are required to move the material into mainstream acceptance by manufacturers. It is too early to predict the future dominance of SOI technology. Next steps in the development of an SOI technology base are better understanding of how materials issues affect device/circuit operation, and which device design paradigms are best.
{"title":"Manufacturing technology challenges for low power electronics","authors":"Z. Lemnios","doi":"10.1109/VLSIT.1995.520833","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520833","url":null,"abstract":"SOI is an attractive technology option for low power, high performance semiconductors. A number of breakthroughs and developments are required to move the material into mainstream acceptance by manufacturers. It is too early to predict the future dominance of SOI technology. Next steps in the development of an SOI technology base are better understanding of how materials issues affect device/circuit operation, and which device design paradigms are best.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116672458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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