Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520835
T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. Momose, H. Iwai
Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.
{"title":"Silicided silicon-sidewall source and drain (S/sup 4/D) structure for high-performance 75-nm gate length pMOSFETs","authors":"T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. Momose, H. Iwai","doi":"10.1109/VLSIT.1995.520835","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520835","url":null,"abstract":"Silicided Silicon-Sidewall Source and Drain (S/sup 4/D) structures were proposed for sub-0.1 /spl mu/m gate length p-MOSFETs as the structure which can realize extremely small source and drain series resistance with small short-channel effects. By using this structure, 75 mm gate length p-MOSFETs were fabricated and very good electrical characteristics were confirmed. In this experiment, only p-MOSFETs were fabricated, but the S/sup 4/D structures are also suitable for the sub-0.1 /spl mu/m gate length CMOS devices, because, basically, the sidewall amorphous silicon is easily doped with the dopant of source and drain by source and drain implantation without prior in situ doping.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520872
M. Izawa, T. Kumihashi, Y. Ohji
Plasma etching has been widely used in fabricating ultra large-scale integrated circuits (ULSI). One etching problem, however is that the etching rate decreases with decreasing pattern width; this is called microloading. Up to now, ion shadowing microloading was suppressed by using lower gas pressure. However, as the pressure decreases, another type of microloading is caused by reactant limiting or product adsorption. Recently, we found that the etching rate was related to reactant and product surface diffusion in the adsorption process. Our model incorporating this process has shown these types of microloading decrease as the pressure increases, in contrast to ion shadowing microloading. Therefore, there must be an optimum gas pressure that minimizes microloading. We can determine this pressure using our etching model which involves an ion shadowing term. This model is applied here to Cl/sub 2/-gas Si etching and Al etching.
{"title":"An etching model to predict minimum-microloading gas pressure","authors":"M. Izawa, T. Kumihashi, Y. Ohji","doi":"10.1109/VLSIT.1995.520872","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520872","url":null,"abstract":"Plasma etching has been widely used in fabricating ultra large-scale integrated circuits (ULSI). One etching problem, however is that the etching rate decreases with decreasing pattern width; this is called microloading. Up to now, ion shadowing microloading was suppressed by using lower gas pressure. However, as the pressure decreases, another type of microloading is caused by reactant limiting or product adsorption. Recently, we found that the etching rate was related to reactant and product surface diffusion in the adsorption process. Our model incorporating this process has shown these types of microloading decrease as the pressure increases, in contrast to ion shadowing microloading. Therefore, there must be an optimum gas pressure that minimizes microloading. We can determine this pressure using our etching model which involves an ion shadowing term. This model is applied here to Cl/sub 2/-gas Si etching and Al etching.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127796457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520875
G.G. Lee, K. Fujihara, S. Kim, C. Oh, U. Chung, S.T. Ahn, M.Y. Lee
A new hot wall type rapid thermal annealing (H-RTA) technology using a vertical batch furnace has been developed. This technology provides junctions with shallow and high concentration and slip free process with high throughput. We have demonstrated that H-RTA is a promising candidate for device fabrications beyond 256 Mbit DRAM in cost as well as in performance.
{"title":"A smart batch type RTA technology for beyond 256 Mbit DRAM","authors":"G.G. Lee, K. Fujihara, S. Kim, C. Oh, U. Chung, S.T. Ahn, M.Y. Lee","doi":"10.1109/VLSIT.1995.520875","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520875","url":null,"abstract":"A new hot wall type rapid thermal annealing (H-RTA) technology using a vertical batch furnace has been developed. This technology provides junctions with shallow and high concentration and slip free process with high throughput. We have demonstrated that H-RTA is a promising candidate for device fabrications beyond 256 Mbit DRAM in cost as well as in performance.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520888
N. Tanabe, T. Matsuki, S. Saitoh, T. Takeuchi, S. Kobayashi, T. Nakajima, Y. Maejima, Y. Hayashi, K. Amanuma, T. Hase, Y. Miyasaka, T. Kunio
A ferroelectric capacitor over bit-line (F-COB) cell is proposed for high density nonvolatile ferroelectric memories (NVFRAMs). This memory cell with 0.7 /spl mu/m design rule was successfully fabricated using a newly-developed fabrication process, combining CMP and MOCVD techniques. Good ferroelectric properties of storage capacitor, having a remanent polarization of 15 /spl mu/C/cm/sup 2/ and leakage current density of 10/sup -6/ A/cm/sup 2/, have been realized without degradation in CMOS characteristics.
{"title":"A ferroelectric capacitor over bit-line (F-COB) cell for high density nonvolatile ferroelectric memories","authors":"N. Tanabe, T. Matsuki, S. Saitoh, T. Takeuchi, S. Kobayashi, T. Nakajima, Y. Maejima, Y. Hayashi, K. Amanuma, T. Hase, Y. Miyasaka, T. Kunio","doi":"10.1109/VLSIT.1995.520888","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520888","url":null,"abstract":"A ferroelectric capacitor over bit-line (F-COB) cell is proposed for high density nonvolatile ferroelectric memories (NVFRAMs). This memory cell with 0.7 /spl mu/m design rule was successfully fabricated using a newly-developed fabrication process, combining CMP and MOCVD techniques. Good ferroelectric properties of storage capacitor, having a remanent polarization of 15 /spl mu/C/cm/sup 2/ and leakage current density of 10/sup -6/ A/cm/sup 2/, have been realized without degradation in CMOS characteristics.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134103080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520877
J. Bude
Because gate currents, I/sub G/, are a sensitive measure of the high energy tail of the hot carrier distribution, understanding their origins is essential to understanding hot carrier effects in MOSFETs. To this end, the gate current of nMOSFETs designed for 0.1 /spl mu/m operation-tenth micron technology-has been investigated theoretically and experimentally. Monte Carlo transport simulations have identified a new I/sub G/ mechanism in these devices based on impact ionization feedback through the vertical fields of the drain substrate junction.
{"title":"Gate current by impact ionization feedback in sub-micron MOSFET technologies","authors":"J. Bude","doi":"10.1109/VLSIT.1995.520877","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520877","url":null,"abstract":"Because gate currents, I/sub G/, are a sensitive measure of the high energy tail of the hot carrier distribution, understanding their origins is essential to understanding hot carrier effects in MOSFETs. To this end, the gate current of nMOSFETs designed for 0.1 /spl mu/m operation-tenth micron technology-has been investigated theoretically and experimentally. Monte Carlo transport simulations have identified a new I/sub G/ mechanism in these devices based on impact ionization feedback through the vertical fields of the drain substrate junction.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134497422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520866
H. Fukuda, S. Okazaki
Critical dimension (CD) control for optical-, EB-, and X-ray lithography is analyzed. In the 0.1 to 0.2-/spl mu/m region, processing factors such as diffusion of chemical species in resist films and mask edge accuracy become dominant. These make it difficult to achieve this scale with sufficient CD control even with post-optical lithography methods.
{"title":"Analysis of critical dimension control for optical-, EB-, and X-ray lithography below the 0.2-/spl mu/m region","authors":"H. Fukuda, S. Okazaki","doi":"10.1109/VLSIT.1995.520866","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520866","url":null,"abstract":"Critical dimension (CD) control for optical-, EB-, and X-ray lithography is analyzed. In the 0.1 to 0.2-/spl mu/m region, processing factors such as diffusion of chemical species in resist films and mask edge accuracy become dominant. These make it difficult to achieve this scale with sufficient CD control even with post-optical lithography methods.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132875518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520884
D. Hisamoto, K. Umeda, Y. Nakamura, N. Kobayashi, S. Kimura, R. Nagai
This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.
{"title":"High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W","authors":"D. Hisamoto, K. Umeda, Y. Nakamura, N. Kobayashi, S. Kimura, R. Nagai","doi":"10.1109/VLSIT.1995.520884","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520884","url":null,"abstract":"This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130955454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520855
P. K. Chatterjee, R. Doering
10 years from now, we envision producing gigachips for an ever expanding electronics market at a cost per function that continues to decrease by approximately 25%/year. To meet this challenge, we must continue to pursue advanced concepts in factories and equipment that are synergistic with continuous/synchronous manufacturing. In particular, such opportunities include: larger wafers, single-wafer processing, clustering/multiprocessing, real-time process/factory control, integrated minienvironments, and standards-based modular design. In most cases, the development and implementation of such change will require new levels of cooperation among suppliers, customers, and competitors in the semiconductor industry.
{"title":"Manufacturing gigachips in the year 2005","authors":"P. K. Chatterjee, R. Doering","doi":"10.1109/VLSIT.1995.520855","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520855","url":null,"abstract":"10 years from now, we envision producing gigachips for an ever expanding electronics market at a cost per function that continues to decrease by approximately 25%/year. To meet this challenge, we must continue to pursue advanced concepts in factories and equipment that are synergistic with continuous/synchronous manufacturing. In particular, such opportunities include: larger wafers, single-wafer processing, clustering/multiprocessing, real-time process/factory control, integrated minienvironments, and standards-based modular design. In most cases, the development and implementation of such change will require new levels of cooperation among suppliers, customers, and competitors in the semiconductor industry.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115381571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520832
G. Inoue, S. Asakura, M. Iiri
Yield and device monitoring during the production rather than at the end of the whole processes on final chips may also be more commonly practised for the earlier detection of failures. In-situ monitoring with single wafer processing may be used for finer process control. To reduce the ever increasing cost of clean rooms including the running cost, mini environment technologies will be applied more to production in clean rooms. Material handling automation will be essential for dealing with heavy load of larger wafers. To share the higher investment for equipment and facilities, international alliances among foreign companies will be accelerated, and production environment needs to be global. Technology trends toward the year 2000 are shown. The role of CIM systems in the semiconductor industry has become increasingly important for dealing with new technologies as well as with their difficulties. Their importance and expected roles are discussed.
{"title":"Semiconductor CIM system, innovation toward the year 2000","authors":"G. Inoue, S. Asakura, M. Iiri","doi":"10.1109/VLSIT.1995.520832","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520832","url":null,"abstract":"Yield and device monitoring during the production rather than at the end of the whole processes on final chips may also be more commonly practised for the earlier detection of failures. In-situ monitoring with single wafer processing may be used for finer process control. To reduce the ever increasing cost of clean rooms including the running cost, mini environment technologies will be applied more to production in clean rooms. Material handling automation will be essential for dealing with heavy load of larger wafers. To share the higher investment for equipment and facilities, international alliances among foreign companies will be accelerated, and production environment needs to be global. Technology trends toward the year 2000 are shown. The role of CIM systems in the semiconductor industry has become increasingly important for dealing with new technologies as well as with their difficulties. Their importance and expected roles are discussed.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114088856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520841
H. Abiko, A. Ono, R. Ueno, S. Masuoka, S. Shishiguchi, K. Nakajima, I. Sakai
A new channel engineering combined with optimization of channel epitaxy and suppression of TED (transient enhanced diffusion) is proposed for a practical 0.15 /spl mu/m n-n gate CMOS technology. An optimized channel profile with small Vth fluctuation provides an nMOS with no reverse short channel effect and a high performance BCpMOS.
{"title":"A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technology","authors":"H. Abiko, A. Ono, R. Ueno, S. Masuoka, S. Shishiguchi, K. Nakajima, I. Sakai","doi":"10.1109/VLSIT.1995.520841","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520841","url":null,"abstract":"A new channel engineering combined with optimization of channel epitaxy and suppression of TED (transient enhanced diffusion) is proposed for a practical 0.15 /spl mu/m n-n gate CMOS technology. An optimized channel profile with small Vth fluctuation provides an nMOS with no reverse short channel effect and a high performance BCpMOS.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124268677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：