Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520852
K. Mizobuchi, K. Hamamoto, M. Utsugi, G. Dixit, S. Poarch, R.H. Havemann, C. D. Dobson, A.I. Jeffryes, P.J. Holverson, P. Rich, D. Butler, N. Rimmer, A. McGeown
A novel high pressure (60 MPa) force fill Al-plug technology has been previously shown to be suitable for sub-half micron contact and via hole filling. This paper describes the first application of the new aluminum force fill technology to actual ULSI circuits-64 Mb DRAMs and 0.35 /spl mu/m Logic devices. For both applications, improved electrical performance and superior or equivalent yield has been demonstrated for the high pressure Al-plug approach as compared with the standard hole filling process (W-plug for logic devices and W-liner for DRAMs). Full bit functional 64 Mb generation DRAMs fabricated using the new aluminum force fill technology show nominal electrical behavior with no anomalous reliability issues.
{"title":"Application of force fill Al-plug technology to 64 Mb DRAM and 0.35 /spl mu/m logic","authors":"K. Mizobuchi, K. Hamamoto, M. Utsugi, G. Dixit, S. Poarch, R.H. Havemann, C. D. Dobson, A.I. Jeffryes, P.J. Holverson, P. Rich, D. Butler, N. Rimmer, A. McGeown","doi":"10.1109/VLSIT.1995.520852","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520852","url":null,"abstract":"A novel high pressure (60 MPa) force fill Al-plug technology has been previously shown to be suitable for sub-half micron contact and via hole filling. This paper describes the first application of the new aluminum force fill technology to actual ULSI circuits-64 Mb DRAMs and 0.35 /spl mu/m Logic devices. For both applications, improved electrical performance and superior or equivalent yield has been demonstrated for the high pressure Al-plug approach as compared with the standard hole filling process (W-plug for logic devices and W-liner for DRAMs). Full bit functional 64 Mb generation DRAMs fabricated using the new aluminum force fill technology show nominal electrical behavior with no anomalous reliability issues.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122606198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520887
S. C. Sun, L. S. Wang, F. Yeh, Chi-Chun Chen
A novel gate structure with excellent electrical properties and reliability has been fabricated by in-situ rapid thermal multiprocessing. Gate oxide was grown first by low pressure rapid thermal oxidation in N/sub 2/O, followed by sequential rapid thermal chemical vapor deposition (RTCVD) of an ultrathin layer (6 nm) of nitrogen-doped polysilicon and then undoped polysilicon. Results show the suppression of boron penetration and high device reliability.
{"title":"Rapid thermal chemical vapor deposition of in-situ nitrogen-doped poly-silicon for dual gate CMOS","authors":"S. C. Sun, L. S. Wang, F. Yeh, Chi-Chun Chen","doi":"10.1109/VLSIT.1995.520887","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520887","url":null,"abstract":"A novel gate structure with excellent electrical properties and reliability has been fabricated by in-situ rapid thermal multiprocessing. Gate oxide was grown first by low pressure rapid thermal oxidation in N/sub 2/O, followed by sequential rapid thermal chemical vapor deposition (RTCVD) of an ultrathin layer (6 nm) of nitrogen-doped polysilicon and then undoped polysilicon. Results show the suppression of boron penetration and high device reliability.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127786121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520886
D. Lee, S. Joo, G. Lee, J. Moon, T. Shim, J. lee
W/TiN stack gate has been investigated as a new gate electrode in ULSI CMOSFETs. With the combination of low resistivity of W and Si-midgap workfunction of TiN, very low sheet resistance and the proper characteristics of both types of transistors could be obtained simultaneously. With the deposition of TiN film at high substrate temperature, the breakdown characteristics of gate oxide could be improved considerably. The proper condition of dry etching on this structure has been also obtained.
{"title":"Characteristics of CMOSFETs with sputter-deposited W/TiN stack gate","authors":"D. Lee, S. Joo, G. Lee, J. Moon, T. Shim, J. lee","doi":"10.1109/VLSIT.1995.520886","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520886","url":null,"abstract":"W/TiN stack gate has been investigated as a new gate electrode in ULSI CMOSFETs. With the combination of low resistivity of W and Si-midgap workfunction of TiN, very low sheet resistance and the proper characteristics of both types of transistors could be obtained simultaneously. With the deposition of TiN film at high substrate temperature, the breakdown characteristics of gate oxide could be improved considerably. The proper condition of dry etching on this structure has been also obtained.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"34 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520840
T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. Ono, H. Momose, H. Iwai
Very high gm values of intrinsic doped epitaxial channel MOSFETs compared with those of bulk MOSFETs has been experimentally confirmed for the first time. It has been found that preheating of the wafer before the UHV-CVD epitaxial growth is critically important to improve the crystal quality of the epitaxial layer and thus to obtain the high gm values. By adopting 700/spl deg/C 5 minutes preheating, a very high gm value of 630 mS/mm was obtained for a 0.1 /spl mu/m epitaxial channel n-MOSFET.
{"title":"The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 /spl mu/m epitaxial Si channel N-MOSFETs grown by UHV-CVD","authors":"T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. Ono, H. Momose, H. Iwai","doi":"10.1109/VLSIT.1995.520840","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520840","url":null,"abstract":"Very high gm values of intrinsic doped epitaxial channel MOSFETs compared with those of bulk MOSFETs has been experimentally confirmed for the first time. It has been found that preheating of the wafer before the UHV-CVD epitaxial growth is critically important to improve the crystal quality of the epitaxial layer and thus to obtain the high gm values. By adopting 700/spl deg/C 5 minutes preheating, a very high gm value of 630 mS/mm was obtained for a 0.1 /spl mu/m epitaxial channel n-MOSFET.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114659347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520853
M. Norishima, T. Matsuno, M. B. Anand, M. Murota, M. Inohara, K. Inoue, H. Ohtani, K. Miyamoto, R. Ogawa, M. Seto, C. Fukuhara, H. Shibata, M. Kakumu
Back-end-of-the line (BEOL) interconnect process integration for sub-half-micron ASIC applications with both low-cost merit and appropriately high performance is presented. Borderless and stacked contact/via structures to reduce chip size and minimization of ILD thickness without performance degradation are achieved. Blind-CMP, selective tungsten CVD, and fluorine-TEOS ILD with low dielectric constant are selected with process simplification in mind.
提出了用于亚半微米ASIC应用的低成本和高性能的后端互连工艺集成。无边界和堆叠的接触/通孔结构，以减少芯片尺寸和最小化ILD厚度，而不降低性能。盲cmp，选择性钨CVD和氟- teos ILD低介电常数的选择与工艺简化的思想。
{"title":"Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applications","authors":"M. Norishima, T. Matsuno, M. B. Anand, M. Murota, M. Inohara, K. Inoue, H. Ohtani, K. Miyamoto, R. Ogawa, M. Seto, C. Fukuhara, H. Shibata, M. Kakumu","doi":"10.1109/VLSIT.1995.520853","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520853","url":null,"abstract":"Back-end-of-the line (BEOL) interconnect process integration for sub-half-micron ASIC applications with both low-cost merit and appropriately high performance is presented. Borderless and stacked contact/via structures to reduce chip size and minimization of ILD thickness without performance degradation are achieved. Blind-CMP, selective tungsten CVD, and fluorine-TEOS ILD with low dielectric constant are selected with process simplification in mind.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116049476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520874
W. Shindo, T. Ohmi
We have shown for the first time that the use of large mass ions in low energy ion bombardment process is quite effective in low-temperature silicon epitaxy. By using Xe ions (mass=131) instead of Ar ions (mass=40), the minimum ion bombardment energy for 300/spl deg/C epitaxy has been drastically reduced from 20 eV to 7 eV, thus minimizing the formation of defects. It is also experimentally shown that the energy dose determined by the product of ion energy and ion flux is a key parameter for epitaxy that compensates for the reduction in the substrate temperature. Low-energy, high-flux, large-mass ion bombardment is the direction for further reducing the processing temperature while presenting high crystallinity of grown films.
{"title":"Low-energy large-mass ion bombardment process for low-temperature high-quality silicon epitaxy","authors":"W. Shindo, T. Ohmi","doi":"10.1109/VLSIT.1995.520874","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520874","url":null,"abstract":"We have shown for the first time that the use of large mass ions in low energy ion bombardment process is quite effective in low-temperature silicon epitaxy. By using Xe ions (mass=131) instead of Ar ions (mass=40), the minimum ion bombardment energy for 300/spl deg/C epitaxy has been drastically reduced from 20 eV to 7 eV, thus minimizing the formation of defects. It is also experimentally shown that the energy dose determined by the product of ion energy and ion flux is a key parameter for epitaxy that compensates for the reduction in the substrate temperature. Low-energy, high-flux, large-mass ion bombardment is the direction for further reducing the processing temperature while presenting high crystallinity of grown films.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122794495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520849
Y. Tosaka, K. Suzuki, T. Sugii
We found the critical /spl alpha/-particle-induced generated charge which determines the soft errors in SOI SRAMs and showed that the soft error rate in submicron SOI SRAMs without body contacts is sometimes larger than that for bulk SRAMs due to the bipolar effect. This suggests the necessity for body contacts or for other technologies in SOI SRAM structures to reduce the bipolar effect.
{"title":"/spl alpha/-particle-induced soft errors in submicron SOI SRAM","authors":"Y. Tosaka, K. Suzuki, T. Sugii","doi":"10.1109/VLSIT.1995.520849","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520849","url":null,"abstract":"We found the critical /spl alpha/-particle-induced generated charge which determines the soft errors in SOI SRAMs and showed that the soft error rate in submicron SOI SRAMs without body contacts is sometimes larger than that for bulk SRAMs due to the bipolar effect. This suggests the necessity for body contacts or for other technologies in SOI SRAM structures to reduce the bipolar effect.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116309785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520834
K. Takeuchi, T. Yamamoto, A. Furukawa, T. Tamura, K. Yoshida
High performance sub-tenth micron CMOS, exhibiting a record ring oscillator delay of 13.6 ps at 1.5 V, has been fabricated. Solid-phase diffusion from BSG was successfully utilized in CMOS fabrication for shallow p/sup +/ junction formation. To eliminate reverse short channel effect and improve punch-through immunity of nMOS, a 'channel implantation after source/drain activation' method was used. Combining these techniques, high speed CMOS operation at 0.07 /spl mu/m with acceptable stand-by leakage was obtained. WSi/sub 2//poly dual gate process without extra mask steps is also demonstrated.
{"title":"High performance sub-tenth micron CMOS using advanced boron doping and WSi/sub 2/ dual gate process","authors":"K. Takeuchi, T. Yamamoto, A. Furukawa, T. Tamura, K. Yoshida","doi":"10.1109/VLSIT.1995.520834","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520834","url":null,"abstract":"High performance sub-tenth micron CMOS, exhibiting a record ring oscillator delay of 13.6 ps at 1.5 V, has been fabricated. Solid-phase diffusion from BSG was successfully utilized in CMOS fabrication for shallow p/sup +/ junction formation. To eliminate reverse short channel effect and improve punch-through immunity of nMOS, a 'channel implantation after source/drain activation' method was used. Combining these techniques, high speed CMOS operation at 0.07 /spl mu/m with acceptable stand-by leakage was obtained. WSi/sub 2//poly dual gate process without extra mask steps is also demonstrated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126054414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520876
A. Mujtaba, S. Takagi, R. Dutton
The importance of modeling Coulombic scattering in MOS inversion layers is established by demonstrating its impact on critical design parameters such as V/sub T/ and I/sub off/. An accurate model for Coulombic scattering has been developed that, for the first time, properly accounts for 2D confinement and quantum mechanical effects in the inversion layer, thus disproving the viability of 3D classical models. In regimes where 3D models grossly over predict mobility, the new 2D model demonstrates its broad applicability by accurately reproducing experimental results over a wide range of channel dopings, substrate biases, and inversion charge densities.
{"title":"Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs","authors":"A. Mujtaba, S. Takagi, R. Dutton","doi":"10.1109/VLSIT.1995.520876","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520876","url":null,"abstract":"The importance of modeling Coulombic scattering in MOS inversion layers is established by demonstrating its impact on critical design parameters such as V/sub T/ and I/sub off/. An accurate model for Coulombic scattering has been developed that, for the first time, properly accounts for 2D confinement and quantum mechanical effects in the inversion layer, thus disproving the viability of 3D classical models. In regimes where 3D models grossly over predict mobility, the new 2D model demonstrates its broad applicability by accurately reproducing experimental results over a wide range of channel dopings, substrate biases, and inversion charge densities.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121914691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-06-06DOI: 10.1109/VLSIT.1995.520879
S. Kubicek, S. Biesemans, Q.F. Wang, K. Maex, K. De Meyer
Bulk nMOS transistors with nominal poly length of 0.12 /spl mu/m and minimum effective channel length below 0.1 /spl mu/m were fabricated. Arsenic S/D shallow extensions and optimised channel doping by Indium were used to suppress the short channel effect (SCE) as well as the reverse-SCE. E-beam lithography was used for poly level definition and an advanced Co/Ti salicidation scheme was applied to reduce the sheet resistance to below 4 /spl Omega//square for poly widths down to 0.08 /spl mu/m. Design of Experiments (DOE) was used in defining the lot splits to study the influence of technological parameters on the device performance and its sensitivity to fluctuations in process parameters.
{"title":"Sub 0.1 /spl mu/m nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity","authors":"S. Kubicek, S. Biesemans, Q.F. Wang, K. Maex, K. De Meyer","doi":"10.1109/VLSIT.1995.520879","DOIUrl":"https://doi.org/10.1109/VLSIT.1995.520879","url":null,"abstract":"Bulk nMOS transistors with nominal poly length of 0.12 /spl mu/m and minimum effective channel length below 0.1 /spl mu/m were fabricated. Arsenic S/D shallow extensions and optimised channel doping by Indium were used to suppress the short channel effect (SCE) as well as the reverse-SCE. E-beam lithography was used for poly level definition and an advanced Co/Ti salicidation scheme was applied to reduce the sheet resistance to below 4 /spl Omega//square for poly widths down to 0.08 /spl mu/m. Design of Experiments (DOE) was used in defining the lot splits to study the influence of technological parameters on the device performance and its sensitivity to fluctuations in process parameters.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"439 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120976229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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