Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636961
J. Naber, J. Griffiths, J. Salvey
A 1.2 Watt, 6 V, 60% efficient, dual bias power amplifier GaAs IC operating in the AMPS (Advanced Mobile Phone service) band of 824 MHz to 849 MHz has been demonstrated. The IC is a two stage, class AB biased amplifier that has 24 dB of power gain. The input return loss is 12 dB over the band. The IC is packaged in a SOIC 16-pin plastic package that measures 30 mm/sup 2/.
{"title":"A 1.2 W, 60% efficient power amplifier IC for commercial applications","authors":"J. Naber, J. Griffiths, J. Salvey","doi":"10.1109/GAAS.1994.636961","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636961","url":null,"abstract":"A 1.2 Watt, 6 V, 60% efficient, dual bias power amplifier GaAs IC operating in the AMPS (Advanced Mobile Phone service) band of 824 MHz to 849 MHz has been demonstrated. The IC is a two stage, class AB biased amplifier that has 24 dB of power gain. The input return loss is 12 dB over the band. The IC is packaged in a SOIC 16-pin plastic package that measures 30 mm/sup 2/.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116977932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636912
M. Funabashi, K. Ohata, K. Onda, K. Hosoya, T. Inoue, M. Kuzuhara, K. Kanckawa, Y. Kobayashi
This paper reports a high performance V-band MMIC dielectric resonator oscillator (DRO). The DRO utilizing a 0.15 /spl mu/m gate AlGaAs/InGaAs heterojunction FET has exhibited stabilized oscillation with low phase noise of -88 dBc/Hz at 100 kHz off-carrier and the output power of 3.7 dBm at 55.135 GHz. The oscillation frequency stability of -1.9 ppm//spl deg/C was obtained with a dielectric resonator of +3.3 ppm//spl deg/C temperature coefficient.
{"title":"A V-band AlGaAs/InGaAs heterojunction FET MMIC dielectric resonator oscillator","authors":"M. Funabashi, K. Ohata, K. Onda, K. Hosoya, T. Inoue, M. Kuzuhara, K. Kanckawa, Y. Kobayashi","doi":"10.1109/GAAS.1994.636912","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636912","url":null,"abstract":"This paper reports a high performance V-band MMIC dielectric resonator oscillator (DRO). The DRO utilizing a 0.15 /spl mu/m gate AlGaAs/InGaAs heterojunction FET has exhibited stabilized oscillation with low phase noise of -88 dBc/Hz at 100 kHz off-carrier and the output power of 3.7 dBm at 55.135 GHz. The oscillation frequency stability of -1.9 ppm//spl deg/C was obtained with a dielectric resonator of +3.3 ppm//spl deg/C temperature coefficient.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117046131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636915
P. Katzin, V. Aparin
We describe the design and measured performance of active, tunable GaAs MMIC band-pass filters and matched closed-loop MMIC control circuits, both fabricated using a standard 1 /spl mu/m foundry process. Separate, 3-section filter circuits covered the 1.34-2.2 GHz and 1.84-2.7 GHz bands, with -3 dB bandwidths of 91/spl plusmn/7 MHz and 123/spl plusmn/12 MHz, respectively, and mean pass-band insertion losses of 0 dB at each tuning frequency. The control circuits generate filter tuning and Q-control bias voltages by tracking a sub-harmonic reference signal. This circuit automatically maintains the filter insertion loss to within /spl plusmn/0.5 dB over more than a 1.3:1 frequency-tuning range, and regulates the center-frequency and insertion loss to within better than /spl plusmn/1.2 MHz and /spl plusmn/0.3 dB over a temperature range of -50/spl deg/C to +75/spl deg/C.
{"title":"Active, self-adjusting L-S band MMIC filters","authors":"P. Katzin, V. Aparin","doi":"10.1109/GAAS.1994.636915","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636915","url":null,"abstract":"We describe the design and measured performance of active, tunable GaAs MMIC band-pass filters and matched closed-loop MMIC control circuits, both fabricated using a standard 1 /spl mu/m foundry process. Separate, 3-section filter circuits covered the 1.34-2.2 GHz and 1.84-2.7 GHz bands, with -3 dB bandwidths of 91/spl plusmn/7 MHz and 123/spl plusmn/12 MHz, respectively, and mean pass-band insertion losses of 0 dB at each tuning frequency. The control circuits generate filter tuning and Q-control bias voltages by tracking a sub-harmonic reference signal. This circuit automatically maintains the filter insertion loss to within /spl plusmn/0.5 dB over more than a 1.3:1 frequency-tuning range, and regulates the center-frequency and insertion loss to within better than /spl plusmn/1.2 MHz and /spl plusmn/0.3 dB over a temperature range of -50/spl deg/C to +75/spl deg/C.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123967771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636973
S. Feng, J. Sauerer, D. Seitzer
The paper presents design considerations and implementation of analog components, including an operational amplifier, latched comparator, 1 bit D/A converter and second-order modulator, for a fully differential delta-sigma modulation oversampling A/D converter in a 0.5 /spl mu/m GaAs E/D HEMT technology. On-wafer measurements demonstrate that the second-order modulator achieves a 60 dB dynamic range at a Nyquist conversion rate of 5.0 MHz with a sampling frequency of 500 MHz.
{"title":"Implementation of GaAs E/D HEMT analog components for oversampling analog/digital conversion","authors":"S. Feng, J. Sauerer, D. Seitzer","doi":"10.1109/GAAS.1994.636973","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636973","url":null,"abstract":"The paper presents design considerations and implementation of analog components, including an operational amplifier, latched comparator, 1 bit D/A converter and second-order modulator, for a fully differential delta-sigma modulation oversampling A/D converter in a 0.5 /spl mu/m GaAs E/D HEMT technology. On-wafer measurements demonstrate that the second-order modulator achieves a 60 dB dynamic range at a Nyquist conversion rate of 5.0 MHz with a sampling frequency of 500 MHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129857208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636944
S. Nakajima, G. Ishii, Y. Saito, N. Kuwata, T. Fukuzawa, K. Koike, H. Nishizawa
A manufacturable self-aligned LDD GaAs MESFET process called SRD has been developed. In this process, we controlled the fabrication conditions from lot to lot. Excellent control of the device characteristics not only across the wafer but also from wafer to wafer is obtained. The controllability of Vth is within /spl plusmn/50 mV. The standard deviation of Vth across the 3-in wafer is less than 30 mV for 0.5 /spl mu/m devices. In addition, other parameters such as g/sub m/, g/sub d/ are also well controlled within /spl plusmn/7% (Max-Min).
{"title":"Manufacturability of dummy-gate self-aligned LDD GaAs MESFETs for high volume production","authors":"S. Nakajima, G. Ishii, Y. Saito, N. Kuwata, T. Fukuzawa, K. Koike, H. Nishizawa","doi":"10.1109/GAAS.1994.636944","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636944","url":null,"abstract":"A manufacturable self-aligned LDD GaAs MESFET process called SRD has been developed. In this process, we controlled the fabrication conditions from lot to lot. Excellent control of the device characteristics not only across the wafer but also from wafer to wafer is obtained. The controllability of Vth is within /spl plusmn/50 mV. The standard deviation of Vth across the 3-in wafer is less than 30 mV for 0.5 /spl mu/m devices. In addition, other parameters such as g/sub m/, g/sub d/ are also well controlled within /spl plusmn/7% (Max-Min).","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"36 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129340362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636948
Jong-Lam Lee, J. Mun, Hae-cheon Kim, Jae Jin Lee, Hyung‐Moo Park, S. Park
A state-of-the-art GaAs power MESFET operating at a drain bias of 2.3 V has been developed using the low-high doped channel structure. The device has 0.8-/spl mu/m gate length and 21-mm gate width. The power performance tested at a 2.3 V drain bias under 900 MHz operation frequency was output power of 31.3-dBm with 11.3-dB gain and 69-percent power-added efficiency. A third-order intercept point was evaluated to be 50.7-dBm. A Linearity Figure-of-Merit of 55.6 was recorded for 21-mm-wide FET.
{"title":"2.3 V operation GaAs power MESFET with 68% power-added efficiency","authors":"Jong-Lam Lee, J. Mun, Hae-cheon Kim, Jae Jin Lee, Hyung‐Moo Park, S. Park","doi":"10.1109/GAAS.1994.636948","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636948","url":null,"abstract":"A state-of-the-art GaAs power MESFET operating at a drain bias of 2.3 V has been developed using the low-high doped channel structure. The device has 0.8-/spl mu/m gate length and 21-mm gate width. The power performance tested at a 2.3 V drain bias under 900 MHz operation frequency was output power of 31.3-dBm with 11.3-dB gain and 69-percent power-added efficiency. A third-order intercept point was evaluated to be 50.7-dBm. A Linearity Figure-of-Merit of 55.6 was recorded for 21-mm-wide FET.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636981
Y. Kohno, H. Matsubayashi, M. Komaru, H. Takano, O. Ishihara, S. Mitsui
Drain current frequency dispersions (gate-lag) in GaAs MESFETs have been investigated and a novel surface trap model is proposed which reveals the mechanism of gate-lag. Assuming two kinds of surface traps with a delay time of 28 msec and 5 msec, the fitting curve agrees with the measured drain current transients. The dependence of gate-lag on various operating bias conditions such as pulse period, applied pulse voltage, and drain bias has been also observed. Furthermore, it is confirmed that the double recessed structure with the inner recess depth of 500 /spl Aring/ is available for the reduction of gate-lag.
{"title":"Modeling and suppression of the surface trap effect on drain current frequency dispersions in GaAs MESFETs","authors":"Y. Kohno, H. Matsubayashi, M. Komaru, H. Takano, O. Ishihara, S. Mitsui","doi":"10.1109/GAAS.1994.636981","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636981","url":null,"abstract":"Drain current frequency dispersions (gate-lag) in GaAs MESFETs have been investigated and a novel surface trap model is proposed which reveals the mechanism of gate-lag. Assuming two kinds of surface traps with a delay time of 28 msec and 5 msec, the fitting curve agrees with the measured drain current transients. The dependence of gate-lag on various operating bias conditions such as pulse period, applied pulse voltage, and drain bias has been also observed. Furthermore, it is confirmed that the double recessed structure with the inner recess depth of 500 /spl Aring/ is available for the reduction of gate-lag.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636984
K. Nishihori, K. Ishida, Y. Kitaura, N. Uchitomi
The effect of attachment for chip-mounting upon the thermal resistance of GaAs power FET modules has been experimentally investigated. The thermal resistance was evaluated by electrical method, which is related to the temperature dependence of Schottky-barrier in the GaAs MESFETs. The thermal resistance of low-cost epoxy-mounted modules was found to be almost the same as that of AuSn-mounted ones for a chip-thickness of 250 /spl mu/m. Applicable expression has also been presented for optimizing thermal design of power MMICs, suggesting that the optimum chip thickness depends on the thermal conductivity of attachment material.
{"title":"GaAs MMIC thermal analysis for epoxy-mount compared with AuSn-mount","authors":"K. Nishihori, K. Ishida, Y. Kitaura, N. Uchitomi","doi":"10.1109/GAAS.1994.636984","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636984","url":null,"abstract":"The effect of attachment for chip-mounting upon the thermal resistance of GaAs power FET modules has been experimentally investigated. The thermal resistance was evaluated by electrical method, which is related to the temperature dependence of Schottky-barrier in the GaAs MESFETs. The thermal resistance of low-cost epoxy-mounted modules was found to be almost the same as that of AuSn-mounted ones for a chip-thickness of 250 /spl mu/m. Applicable expression has also been presented for optimizing thermal design of power MMICs, suggesting that the optimum chip thickness depends on the thermal conductivity of attachment material.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133818596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636913
L. Kushner, G. V. Andrews, W. White, J. Delaney, M. Vernon, M. Harris, David A. Whitmire
An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz.
{"title":"An 800 MHz monolithic GaAs HBT serrodyne modulator","authors":"L. Kushner, G. V. Andrews, W. White, J. Delaney, M. Vernon, M. Harris, David A. Whitmire","doi":"10.1109/GAAS.1994.636913","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636913","url":null,"abstract":"An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636905
N. Cheung
Gives a survey of the ongoing gigabit testbeds in the U.S. and other countries. This is followed by a review of the recent progress in SONET- and ATM-based gigabit networking technologies, and a projection of the technology trends in the near future. The author also discusses the potential opportunities and challenges of migrating the ongoing experimental gigabit testbeds to an ubiquitous and highly reliable National Information Infrastructure.
{"title":"Gigabit networking technologies and beyond","authors":"N. Cheung","doi":"10.1109/GAAS.1994.636905","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636905","url":null,"abstract":"Gives a survey of the ongoing gigabit testbeds in the U.S. and other countries. This is followed by a review of the recent progress in SONET- and ATM-based gigabit networking technologies, and a projection of the technology trends in the near future. The author also discusses the potential opportunities and challenges of migrating the ongoing experimental gigabit testbeds to an ubiquitous and highly reliable National Information Infrastructure.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122011754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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