Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636965
K. Murata, T. Otsuji, E. Sano, M. Ohhata, M. Togashi, M. Suzuki
This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.
{"title":"A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 /spl mu/m GaAs MESFET","authors":"K. Murata, T. Otsuji, E. Sano, M. Ohhata, M. Togashi, M. Suzuki","doi":"10.1109/GAAS.1994.636965","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636965","url":null,"abstract":"This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116925258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636983
F. Yamada, A. Oki, D. Streit, Y. Saito, A. R. Coulson, W.C. Atwood, E. Rezek
We report the world's first lifetest results of a monolithic integrated circuit fabricated using GaAs/AlGaAs Heterojunction Bipolar Transistor (HBT) technology. The Successive Detection Logarithmic Amplifier (SDLA) was used as the standard evaluation circuit (SEC) to evaluate the HBT process. Results of a three temperature constant stress lifetest projects a median-time-to-failure (MTF) of >10/sup 7/ hours at 125/spl deg/C junction temperature with an activation energy (Ea) of 1.4 eV and log-sigma (/spl sigma/) of 0.7. Failure criteria were based on RF and DC characteristics of the SDLA. Failure mode is also discussed. This study establishes GaAs/AlGaAs HBT technology as a mature and reliable process technology.
{"title":"Reliability of a high performance monolithic IC fabricated using a production GaAs/AlGaAs HBT process","authors":"F. Yamada, A. Oki, D. Streit, Y. Saito, A. R. Coulson, W.C. Atwood, E. Rezek","doi":"10.1109/GAAS.1994.636983","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636983","url":null,"abstract":"We report the world's first lifetest results of a monolithic integrated circuit fabricated using GaAs/AlGaAs Heterojunction Bipolar Transistor (HBT) technology. The Successive Detection Logarithmic Amplifier (SDLA) was used as the standard evaluation circuit (SEC) to evaluate the HBT process. Results of a three temperature constant stress lifetest projects a median-time-to-failure (MTF) of >10/sup 7/ hours at 125/spl deg/C junction temperature with an activation energy (Ea) of 1.4 eV and log-sigma (/spl sigma/) of 0.7. Failure criteria were based on RF and DC characteristics of the SDLA. Failure mode is also discussed. This study establishes GaAs/AlGaAs HBT technology as a mature and reliable process technology.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636997
T. Enoki, Takashi Kobayashi, Y. Ishii
This paper reports device technologies for 0.1-/spl mu/m-gate-InP-based HEMTs developed at our laboratory for ultra-high speed ICs. Key developments include a non-alloyed ohmic contact and a T-shaped gate process for high reproducibility and uniformity. As examples of their application to ICs, a 50 GHz low-noise amplifier with NF of 2.6 dB and a 60-GHz bandwidth distributed baseband amplifier with a flat gain of 9 dB are described. Also discussed is the use of a recess-etch stopper to further improve the reproducibility of the gate recess.
{"title":"Device technologies for InP-based HEMTs and their application to ICs","authors":"T. Enoki, Takashi Kobayashi, Y. Ishii","doi":"10.1109/GAAS.1994.636997","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636997","url":null,"abstract":"This paper reports device technologies for 0.1-/spl mu/m-gate-InP-based HEMTs developed at our laboratory for ultra-high speed ICs. Key developments include a non-alloyed ohmic contact and a T-shaped gate process for high reproducibility and uniformity. As examples of their application to ICs, a 50 GHz low-noise amplifier with NF of 2.6 dB and a 60-GHz bandwidth distributed baseband amplifier with a flat gain of 9 dB are described. Also discussed is the use of a recess-etch stopper to further improve the reproducibility of the gate recess.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636903
J. Cazaux
Fifteen years after their first demonstration, MMIC's are now rapidly conquering the world of space electronics. The driving forces behind MMIC development have been miniaturization, cost reduction and higher reliability. MMIC's have first been introduced into GEO Telecommunication satellites with a new generation of compact channel amplifier (CAMP). Receiver and solid state power amplifiers (SSPA) are following. After the first convincing demonstrations, MMIC's have now become an absolute necessity for turning into reality future satellites with active antennas, observation radars or future systems such as LEO constellations.
{"title":"MMIC's for space-borne systems: status and prospects","authors":"J. Cazaux","doi":"10.1109/GAAS.1994.636903","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636903","url":null,"abstract":"Fifteen years after their first demonstration, MMIC's are now rapidly conquering the world of space electronics. The driving forces behind MMIC development have been miniaturization, cost reduction and higher reliability. MMIC's have first been introduced into GEO Telecommunication satellites with a new generation of compact channel amplifier (CAMP). Receiver and solid state power amplifiers (SSPA) are following. After the first convincing demonstrations, MMIC's have now become an absolute necessity for turning into reality future satellites with active antennas, observation radars or future systems such as LEO constellations.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636979
C. Hanson, H. Fu, M. Golio
Characterization data, theoretical developments, and the design and reliability impact of three-terminal breakdown is reported. Surface states are shown empirically to play a significant role in breakdown voltage mechanisms. It is illustrated that charge trapping phenomena can dominate the temperature coefficient of the breakdown voltage making analogies to diode characteristics invalid.
{"title":"Three-terminal breakdown effects in power MESFETs","authors":"C. Hanson, H. Fu, M. Golio","doi":"10.1109/GAAS.1994.636979","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636979","url":null,"abstract":"Characterization data, theoretical developments, and the design and reliability impact of three-terminal breakdown is reported. Surface states are shown empirically to play a significant role in breakdown voltage mechanisms. It is illustrated that charge trapping phenomena can dominate the temperature coefficient of the breakdown voltage making analogies to diode characteristics invalid.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129966624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636992
K. Kobayashi, R. Kasody, A. Oki, G. Dow, B. Allen, D. Streit
A Schottky diode double-double balanced mixer with 10 dB conversion loss and >60 dB LO-IF isolation has been achieved using AlGaAs/GaAs HBTs. The HBT Schottky mixer converts a 6-10 GHz RF signal down to a 2-6 GHz IF band with a fixed LO of 10 dBm at 12 GHz. The IP3 is as high as 11 dBm at this LO drive level. An up-conversion loss of <10 dB was also measured with an IP3 of as much as 12 dBm at midband. The Schottky diodes were constructed by making a Schottky contact to the HBT MBE N/sup -/ collector layer. The resulting Schottky diodes obtain a cut-off frequency of 1 THz and an ideality factor=1.05. The same HBT process yields an f/sub T/ and f/sub max/ of 23 GHz and 50 GHz, respectively, for a 2 /spl mu/m emitter width Self-Aligned Base Ohmic Metal HBT. The work in this paper represents the first double-double balanced HBT Schottky diode mixer demonstration and achieves superior performance to a previously published double-double balanced X-band MESFET Schottky mixer.
{"title":"A double-double balanced HBT Schottky diode broadband mixer at X-band","authors":"K. Kobayashi, R. Kasody, A. Oki, G. Dow, B. Allen, D. Streit","doi":"10.1109/GAAS.1994.636992","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636992","url":null,"abstract":"A Schottky diode double-double balanced mixer with 10 dB conversion loss and >60 dB LO-IF isolation has been achieved using AlGaAs/GaAs HBTs. The HBT Schottky mixer converts a 6-10 GHz RF signal down to a 2-6 GHz IF band with a fixed LO of 10 dBm at 12 GHz. The IP3 is as high as 11 dBm at this LO drive level. An up-conversion loss of <10 dB was also measured with an IP3 of as much as 12 dBm at midband. The Schottky diodes were constructed by making a Schottky contact to the HBT MBE N/sup -/ collector layer. The resulting Schottky diodes obtain a cut-off frequency of 1 THz and an ideality factor=1.05. The same HBT process yields an f/sub T/ and f/sub max/ of 23 GHz and 50 GHz, respectively, for a 2 /spl mu/m emitter width Self-Aligned Base Ohmic Metal HBT. The work in this paper represents the first double-double balanced HBT Schottky diode mixer demonstration and achieves superior performance to a previously published double-double balanced X-band MESFET Schottky mixer.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117190799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636966
K. Pedrotti, F. Zucca, P. Zampardi, K. Nary, S. Beccue, K. Runge, D. Meeker, J. Penny, K. C. Wang
Current research on next generation Wavelength Division Multiplexed (WDM) all optical networks has identified the need for arrays of laser driver circuits and arrays of receivers, clock recovery, and decision circuits. This paper reports on the development of two AlGaAs-GaAs HBT-based circuits: an eight-channel laser driver array and four-channel signal regeneration array including the limiting amplifier, clock recovery, and decision functions one intended for operation at 155 Mb/s. Subcircuits of the clock recovery array have been verified as suitable for use up to 2.488 Gb/s. >
{"title":"Hbt Transmitter and Data Regenerator Arrays for Wdm Optical Communications Application","authors":"K. Pedrotti, F. Zucca, P. Zampardi, K. Nary, S. Beccue, K. Runge, D. Meeker, J. Penny, K. C. Wang","doi":"10.1109/GAAS.1994.636966","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636966","url":null,"abstract":"Current research on next generation Wavelength Division Multiplexed (WDM) all optical networks has identified the need for arrays of laser driver circuits and arrays of receivers, clock recovery, and decision circuits. This paper reports on the development of two AlGaAs-GaAs HBT-based circuits: an eight-channel laser driver array and four-channel signal regeneration array including the limiting amplifier, clock recovery, and decision functions one intended for operation at 155 Mb/s. Subcircuits of the clock recovery array have been verified as suitable for use up to 2.488 Gb/s. >","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126164353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636998
K. Hur, R. A. McTaggart, T. Kazior
A Cl/sub 2/:HBr:BCl/sub 3/:Ar-based reactive ion etch process capable of producing high resolution via holes in InP has been developed. Tapered sidewall profiles are obtained using this process as a result of controlled photoresist mask erosion at an optimized etch condition. To demonstrate feasibility of this process for millimeter wave device applications, single-doped AlInAs/GaInAs/InP HEMTs with individually grounded source finger vias have been fabricated.
{"title":"High resolution InP via holes for millimeter wave device applications","authors":"K. Hur, R. A. McTaggart, T. Kazior","doi":"10.1109/GAAS.1994.636998","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636998","url":null,"abstract":"A Cl/sub 2/:HBr:BCl/sub 3/:Ar-based reactive ion etch process capable of producing high resolution via holes in InP has been developed. Tapered sidewall profiles are obtained using this process as a result of controlled photoresist mask erosion at an optimized etch condition. To demonstrate feasibility of this process for millimeter wave device applications, single-doped AlInAs/GaInAs/InP HEMTs with individually grounded source finger vias have been fabricated.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125819713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636974
K. Nary, S. Beccue, R. Nubling, R. Pierson, Keh-Chung Wang, P. Zampardi, A. Jayaraman
We have successfully demonstrated one-bit, second-order delta-sigma modulators in a 50 GHz (F/sub t/) AlGaAs/GaAs heterojunction bipolar transistor process. The integrated modulator, consisting of a low-pass single bit modulator, clock generators and output buffers, has attained an SNR of 37 dB at a sample rate of 2 Gs/s for an oversampling ratio of 20. The circuit dissipates 1.92 W. To our knowledge, these are the first reported HBT delta sigma modulators.
{"title":"Second order /spl Delta//spl Sigma/ modulators using AlGaAs/GaAs HBTS","authors":"K. Nary, S. Beccue, R. Nubling, R. Pierson, Keh-Chung Wang, P. Zampardi, A. Jayaraman","doi":"10.1109/GAAS.1994.636974","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636974","url":null,"abstract":"We have successfully demonstrated one-bit, second-order delta-sigma modulators in a 50 GHz (F/sub t/) AlGaAs/GaAs heterojunction bipolar transistor process. The integrated modulator, consisting of a low-pass single bit modulator, clock generators and output buffers, has attained an SNR of 37 dB at a sample rate of 2 Gs/s for an oversampling ratio of 20. The circuit dissipates 1.92 W. To our knowledge, these are the first reported HBT delta sigma modulators.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131381627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636950
Y. Kohno, T. Kunii, T. Oku, R. Hattori, J. Udomoto, M. Komaru, K. Yajima, A. Inoue, K. Itoh, H. Takano, O. Ishihara, S. Mitsui
We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.
{"title":"K-band high gain and high reliability GaAs power FET with sub-half micron WSi/Au T-shaped gate","authors":"Y. Kohno, T. Kunii, T. Oku, R. Hattori, J. Udomoto, M. Komaru, K. Yajima, A. Inoue, K. Itoh, H. Takano, O. Ishihara, S. Mitsui","doi":"10.1109/GAAS.1994.636950","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636950","url":null,"abstract":"We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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