Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636932
T. Saito, N. Hidaka, Y. Ohashi, Y. Aoki
Using InGaP-InGaAs-GaAs technology, we designed, fabricated, and evaluated a 60-GHz fully integrated HEMT-based MMIC receiver. The receiver consists of a four-stage low-noise amplifier (LNA) and a single-balanced active-gate mixer, a 60 GHz local oscillator (LO), and a buffer amplifier for the LO. The HEMTs in the receiver have gates 0.1 /spl mu/m long and 100 /spl mu/m wide. The receiver had a conversion gain of greater than 17 dB from 60.2 GHz to 62.3 GHz, and the maximum conversion gain was 20 dB at 62.2 GHz. The noise figure of the receiver was less than 6 db for IF frequencies between 100 MHz and 1 GHz for a 61.536 GHz LO, and the minimum noise figure was 49 dB at 1 GHz IF.
{"title":"60-GHz HEMT-based MMIC receiver with on-chip LO","authors":"T. Saito, N. Hidaka, Y. Ohashi, Y. Aoki","doi":"10.1109/GAAS.1994.636932","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636932","url":null,"abstract":"Using InGaP-InGaAs-GaAs technology, we designed, fabricated, and evaluated a 60-GHz fully integrated HEMT-based MMIC receiver. The receiver consists of a four-stage low-noise amplifier (LNA) and a single-balanced active-gate mixer, a 60 GHz local oscillator (LO), and a buffer amplifier for the LO. The HEMTs in the receiver have gates 0.1 /spl mu/m long and 100 /spl mu/m wide. The receiver had a conversion gain of greater than 17 dB from 60.2 GHz to 62.3 GHz, and the maximum conversion gain was 20 dB at 62.2 GHz. The noise figure of the receiver was less than 6 db for IF frequencies between 100 MHz and 1 GHz for a 61.536 GHz LO, and the minimum noise figure was 49 dB at 1 GHz IF.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115514771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636972
J. Jensen, A. Cosand, W. Stanchina, R. Walden, T. Lui, Y. Brown, M. Montes, K. Elliott, C. Kirkpatrick
For high resolution analog circuits we have developed a double heterostructure bipolar transistor (DHBT) technology using InP as the collector material. Our baseline DHBTs have demonstrated current gain /spl beta/, early voltage V/sub A/, f/sub T/, and f/sub max/ of 55, 100 V, 70 GHz, and 60 GHz, respectively. We have implemented an analog cell library to build high resolution /spl Delta//spl Sigma/ modulator circuits in this technology. We have used the cell library to demonstrate a first order modulator and to verify the design of these analog cells. At a sample rate of 4 GSPS and an OSR equal to 32 (i.e., input bandwidth of 62.5 MHz) the first order modulator demonstrated an SNR of 40.3 dB. This first order modulator operates using /spl plusmn/5 V power supplies and dissipates 572 mW.
{"title":"Double heterostructure InP HBT technology for high resolution A/D converters","authors":"J. Jensen, A. Cosand, W. Stanchina, R. Walden, T. Lui, Y. Brown, M. Montes, K. Elliott, C. Kirkpatrick","doi":"10.1109/GAAS.1994.636972","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636972","url":null,"abstract":"For high resolution analog circuits we have developed a double heterostructure bipolar transistor (DHBT) technology using InP as the collector material. Our baseline DHBTs have demonstrated current gain /spl beta/, early voltage V/sub A/, f/sub T/, and f/sub max/ of 55, 100 V, 70 GHz, and 60 GHz, respectively. We have implemented an analog cell library to build high resolution /spl Delta//spl Sigma/ modulator circuits in this technology. We have used the cell library to demonstrate a first order modulator and to verify the design of these analog cells. At a sample rate of 4 GSPS and an OSR equal to 32 (i.e., input bandwidth of 62.5 MHz) the first order modulator demonstrated an SNR of 40.3 dB. This first order modulator operates using /spl plusmn/5 V power supplies and dissipates 572 mW.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129361651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636963
Y. Matsuoka, E. Sano
We developed IC-oriented high-performance AlGaAs/GaAs heterostructure bipolar transistors (HBTs). The parasitic effects of the HBTs are reduced by a self-aligned process technology characterized by a technique for making a base-metal-overlaid (BMO) structure, and the electron transit time in the HBTs is decreased by the novel collector structure of a "ballistic collection transistors with a launcher (LBCT)". The BMO-LBCT with a relatively thin collector had a cutoff frequency f/sub T/ of 171 GHz. By modifying collector thickness and using Pt-Ti-Pt-Au as the base ohmic metal, the maximum oscillation frequency f/sub max/ reached 148 GHz with a 114 GHz f/sub T/. Moreover, an MOCVD-grown highly-carbon-doped structure had an f/sub max/ of 192 GHz while still having an f/sub T/ more than 100 GHz. Using BMO-LBCTs, we successfully fabricated high-speed ICs: a 2:1 multiplexer with retiming D-type flip-flops that operates error-free at 19 Gbit/s, selector IC that operates at 40 Gbit/s, a divided-by-four dynamic frequency divider that functions up to 50 GHz, and a broadband preamplifier with a high gain of 16.8 dB and 3-dB-down bandwidth of 40 GHz.
{"title":"High-speed AlGaAs/GaAs HBTs and their applications to 40-Gbit/s-class ICs","authors":"Y. Matsuoka, E. Sano","doi":"10.1109/GAAS.1994.636963","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636963","url":null,"abstract":"We developed IC-oriented high-performance AlGaAs/GaAs heterostructure bipolar transistors (HBTs). The parasitic effects of the HBTs are reduced by a self-aligned process technology characterized by a technique for making a base-metal-overlaid (BMO) structure, and the electron transit time in the HBTs is decreased by the novel collector structure of a \"ballistic collection transistors with a launcher (LBCT)\". The BMO-LBCT with a relatively thin collector had a cutoff frequency f/sub T/ of 171 GHz. By modifying collector thickness and using Pt-Ti-Pt-Au as the base ohmic metal, the maximum oscillation frequency f/sub max/ reached 148 GHz with a 114 GHz f/sub T/. Moreover, an MOCVD-grown highly-carbon-doped structure had an f/sub max/ of 192 GHz while still having an f/sub T/ more than 100 GHz. Using BMO-LBCTs, we successfully fabricated high-speed ICs: a 2:1 multiplexer with retiming D-type flip-flops that operates error-free at 19 Gbit/s, selector IC that operates at 40 Gbit/s, a divided-by-four dynamic frequency divider that functions up to 50 GHz, and a broadband preamplifier with a high gain of 16.8 dB and 3-dB-down bandwidth of 40 GHz.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115160256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636907
A. Ignatiev, C. Horton, M. Sterling, R. Sega, A. Bensaoula, A. Freundlich, S. Pei
GaAs films, both silicon doped and undoped, have been deposited by Molecular Beam Epitaxy (MBE) in Low Earth Orbit (LEO) in an ultra vacuum environment created by the Wake Shield Facility (WSF). The WSF is a 12 foot diameter stainless steel disk that sweeps out a volume of space thus creating an ultra vacuum in its wake. It was developed specifically to take advantage of the ultra vacuum for the deposition of thin film materials. The WSF was flown for the first time on STS-60 in February, 1994. The mission objectives were to measure the unique wake vacuum environment formed by the Wake Shield, and to epitaxially deposit GaAs thin films. In this paper we describe the films deposited and report on the characterization performed to date. Films were deposited in two basic structures. The first structure consisted of undoped GaAs films of thicknesses ranging from 2 to 4 /spl mu/m with a thin (/spl ap/200 mn) highly silicon doped layer (n/spl ap/5/spl times/10/sup 17//cc) on top. This is basically a metal-semiconductor field effect transistor (MESFET) structure. The second structure was a lightly silicon doped GaAs film (n/spl ap/5/spl times/10/sup 15//cc). We have obtained Photoluminescence (PL), Secondary Ion Mass Spectrometry (SIMS) and X-Ray diffraction data on selected films. The data indicate nominal quality single crystal films with oxygen and carbon contamination. The source of the contamination and further characterization are discussed.
采用分子束外延(MBE)技术，在低地球轨道(LEO)的超真空环境中制备了掺杂和未掺杂的砷化镓薄膜。WSF是一个直径12英尺的不锈钢圆盘，可以扫出一定体积的空间，从而在其尾迹中产生超真空。它是专门为利用超真空沉积薄膜材料而开发的。WSF于1994年2月首次在STS-60上飞行。任务目标是测量尾流屏蔽形成的独特的尾流真空环境，并外延沉积GaAs薄膜。在本文中，我们描述了沉积的薄膜，并报告了迄今为止所进行的表征。薄膜沉积成两种基本结构。第一种结构由厚度为2 ~ 4 /spl μ m的未掺杂GaAs薄膜组成，薄膜上有薄层(/spl μ m /200 mn)高硅掺杂层(n/spl μ m /5/spl倍/10/sup 17//cc)。这基本上是一个金属半导体场效应晶体管(MESFET)结构。第二种结构是轻硅掺杂的GaAs膜(n/spl /5/spl × /10/sup / 15//cc)。我们获得了所选薄膜的光致发光(PL)、二次离子质谱(SIMS)和x射线衍射数据。数据表明，标称质量单晶膜与氧和碳污染。讨论了污染的来源和进一步的表征。
{"title":"Advanced III-V materials processing in the vacuum of space","authors":"A. Ignatiev, C. Horton, M. Sterling, R. Sega, A. Bensaoula, A. Freundlich, S. Pei","doi":"10.1109/GAAS.1994.636907","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636907","url":null,"abstract":"GaAs films, both silicon doped and undoped, have been deposited by Molecular Beam Epitaxy (MBE) in Low Earth Orbit (LEO) in an ultra vacuum environment created by the Wake Shield Facility (WSF). The WSF is a 12 foot diameter stainless steel disk that sweeps out a volume of space thus creating an ultra vacuum in its wake. It was developed specifically to take advantage of the ultra vacuum for the deposition of thin film materials. The WSF was flown for the first time on STS-60 in February, 1994. The mission objectives were to measure the unique wake vacuum environment formed by the Wake Shield, and to epitaxially deposit GaAs thin films. In this paper we describe the films deposited and report on the characterization performed to date. Films were deposited in two basic structures. The first structure consisted of undoped GaAs films of thicknesses ranging from 2 to 4 /spl mu/m with a thin (/spl ap/200 mn) highly silicon doped layer (n/spl ap/5/spl times/10/sup 17//cc) on top. This is basically a metal-semiconductor field effect transistor (MESFET) structure. The second structure was a lightly silicon doped GaAs film (n/spl ap/5/spl times/10/sup 15//cc). We have obtained Photoluminescence (PL), Secondary Ion Mass Spectrometry (SIMS) and X-Ray diffraction data on selected films. The data indicate nominal quality single crystal films with oxygen and carbon contamination. The source of the contamination and further characterization are discussed.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117013153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636982
K. Kunihiro, Y. Ohno
A large-signal HJFET model is developed for deep-trap induced drain-current transient behaviors based on two-dimensional device simulations. In the model, electron capture and emission processes for deep traps are replaced by the currents flowing through a diode and a resistor, which are physically deduced from SRH statistics. The model accurately describes the bias and time dependent nonlinear-characteristics of trapping effects. The influence of the trapping effects on RF switching is also discussed.
{"title":"An equivalent circuit model for deep-trap induced drain-current transient behaviors in HJFETs","authors":"K. Kunihiro, Y. Ohno","doi":"10.1109/GAAS.1994.636982","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636982","url":null,"abstract":"A large-signal HJFET model is developed for deep-trap induced drain-current transient behaviors based on two-dimensional device simulations. In the model, electron capture and emission processes for deep traps are replaced by the currents flowing through a diode and a resistor, which are physically deduced from SRH statistics. The model accurately describes the bias and time dependent nonlinear-characteristics of trapping effects. The influence of the trapping effects on RF switching is also discussed.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132437675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636962
T. Quach, J. Staudinger
A low cost commercial, high performance two stage GaAs MESFET power amplifier has been developed for the 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band targeting portable wireless LAN applications. The amplifier is housed in a low cost plastic surface mount package, making it well suited for insertion into low profile PCM/CIA formats. Measured performance has demonstrated 24 dBm output power with greater than 65% power added efficiency when operated in gain compression with a 5 volt supply. Harmonic rejection greater than 18 dBc and 30 dBc is achieved on 2nd and 3rd order harmonics, respectively. On chip bias and power level control circuitry allows adjusting the output power level over a 20 dBc range with a single analog control voltage. Stringent cost goals are achieved by limiting chip size, choosing inexpensive plastic packaging, and by selecting an appropriate amplifier topology which places some components off chip.
{"title":"A high efficiency commercial GaAs MESFET power amplifier for PCM/CIA applications at 2.45 GHz","authors":"T. Quach, J. Staudinger","doi":"10.1109/GAAS.1994.636962","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636962","url":null,"abstract":"A low cost commercial, high performance two stage GaAs MESFET power amplifier has been developed for the 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band targeting portable wireless LAN applications. The amplifier is housed in a low cost plastic surface mount package, making it well suited for insertion into low profile PCM/CIA formats. Measured performance has demonstrated 24 dBm output power with greater than 65% power added efficiency when operated in gain compression with a 5 volt supply. Harmonic rejection greater than 18 dBc and 30 dBc is achieved on 2nd and 3rd order harmonics, respectively. On chip bias and power level control circuitry allows adjusting the output power level over a 20 dBc range with a single analog control voltage. Stringent cost goals are achieved by limiting chip size, choosing inexpensive plastic packaging, and by selecting an appropriate amplifier topology which places some components off chip.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132663990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636968
Y. Yamauchi, K. Nagata, T. Makimura, O. Nakajima, H. Ito, T. Ishibashi
We have developed a high-output-voltage monolithically integrated driver circuit for an external optical modulator using InGaP/GaAs HBTs with a collector breakdown voltage, BVceo, of 14 V. The driver circuit consists of an input buffer stage, two differential gain stages, an emitter-follower prefinal stage, and a final differential stage. The circuit operates stably with output signal voltage of 5.5 V at up to 12 Gb/s with a single-phase ECL-level input signal. Error-free operation is confirmed from the NRZ 2/sup 23/-1 PN pattern obtained at 10 Gb/s.
{"title":"10 Gb/s monolithic optical modulator driver with high output voltage of 5 V using InGaP/GaAs HBTs","authors":"Y. Yamauchi, K. Nagata, T. Makimura, O. Nakajima, H. Ito, T. Ishibashi","doi":"10.1109/GAAS.1994.636968","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636968","url":null,"abstract":"We have developed a high-output-voltage monolithically integrated driver circuit for an external optical modulator using InGaP/GaAs HBTs with a collector breakdown voltage, BVceo, of 14 V. The driver circuit consists of an input buffer stage, two differential gain stages, an emitter-follower prefinal stage, and a final differential stage. The circuit operates stably with output signal voltage of 5.5 V at up to 12 Gb/s with a single-phase ECL-level input signal. Error-free operation is confirmed from the NRZ 2/sup 23/-1 PN pattern obtained at 10 Gb/s.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115423034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636964
Y. Kuriyama, T. Sugiyama, S. Hongo, J. Akagi, K. Tsuda, N. Iizuka, M. Obara
We report a master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBTs. The operation of this IC was confirmed up to 40 GHz, which is the highest speed in flip-flop circuits including static dividers.
{"title":"A 40 GHz D-type flip-flop using AlGaAs/GaAs HBTs","authors":"Y. Kuriyama, T. Sugiyama, S. Hongo, J. Akagi, K. Tsuda, N. Iizuka, M. Obara","doi":"10.1109/GAAS.1994.636964","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636964","url":null,"abstract":"We report a master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBTs. The operation of this IC was confirmed up to 40 GHz, which is the highest speed in flip-flop circuits including static dividers.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114788055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636989
K. Kobayashi, A. Oki
A direct-coupled low noise amplifier with less than 2.5 dB noise figure up to 4.3 GHz has been demonstrated using 2 /spl mu/m emitter-width GaAs HBTs. A noise figure of 2.2-2.5 dB and a nominal gain of 33 dB has been achieved with a 4.3 GHz 3-dB bandwidth. A low power consumption version obtained a noise figure of 3.0-3.1 dB, a gain of 24 dB, and a bandwidth of 4.5 GHz while consuming only 64 mW of dc power through a 5 volt supply. The HBT amplifier chips are miniature in size, 0.27/spl times/0.3 mm/sup 2/, and can yield over 25000 die per 3-inch GaAs wafer at a cost well under $1 per die, making them suitable for high volume low cost commercial applications. These amplifiers benchmark the lowest noise figures reported for an HBT amplifier and are comparable to commercially available state-of-the-art silicon bipolar LNAs, but with more than four times the frequency bandwidth performance.
{"title":"Sub-2.5 dB noise figure GaAs HBT direct-coupled LNAs for high volume commercial applications to 6 GHz","authors":"K. Kobayashi, A. Oki","doi":"10.1109/GAAS.1994.636989","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636989","url":null,"abstract":"A direct-coupled low noise amplifier with less than 2.5 dB noise figure up to 4.3 GHz has been demonstrated using 2 /spl mu/m emitter-width GaAs HBTs. A noise figure of 2.2-2.5 dB and a nominal gain of 33 dB has been achieved with a 4.3 GHz 3-dB bandwidth. A low power consumption version obtained a noise figure of 3.0-3.1 dB, a gain of 24 dB, and a bandwidth of 4.5 GHz while consuming only 64 mW of dc power through a 5 volt supply. The HBT amplifier chips are miniature in size, 0.27/spl times/0.3 mm/sup 2/, and can yield over 25000 die per 3-inch GaAs wafer at a cost well under $1 per die, making them suitable for high volume low cost commercial applications. These amplifiers benchmark the lowest noise figures reported for an HBT amplifier and are comparable to commercially available state-of-the-art silicon bipolar LNAs, but with more than four times the frequency bandwidth performance.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636952
Y. Notani, Y. Nakajima, Y. Ohta, Y. Mitsui, M. Nakayama, S. Murakami, S. Orisaka, O. Ishihara, S. Mitsui
A novel packaging technology using a multi-layer Tape Automated Bonding (TAB) tape was developed for a GaAs multi-chip module to be employed in radio units of mobile telephones. The microwave properties of the multi-layer TAB tape were first evaluated using a ring resonator and a through-line. Then, the TAB tape was applied to a 900 MHz-band high power amplifier. It consists of two MMIC chips and an output matching circuit formed on the TAB tape. The amplifier module delivered a saturated output power of 31.6 dBm with a power added efficiency of 54.9% at 933 MHz with a supply voltage Vdd of 3.3 V. These results suggest that the TAB tape assembly has a high potentiality for realizing a thin and light weight RF unit in mobile communication terminals with low cost.
{"title":"GaAs multi-chip power amplifier module using a multi-layer TAB tape","authors":"Y. Notani, Y. Nakajima, Y. Ohta, Y. Mitsui, M. Nakayama, S. Murakami, S. Orisaka, O. Ishihara, S. Mitsui","doi":"10.1109/GAAS.1994.636952","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636952","url":null,"abstract":"A novel packaging technology using a multi-layer Tape Automated Bonding (TAB) tape was developed for a GaAs multi-chip module to be employed in radio units of mobile telephones. The microwave properties of the multi-layer TAB tape were first evaluated using a ring resonator and a through-line. Then, the TAB tape was applied to a 900 MHz-band high power amplifier. It consists of two MMIC chips and an output matching circuit formed on the TAB tape. The amplifier module delivered a saturated output power of 31.6 dBm with a power added efficiency of 54.9% at 933 MHz with a supply voltage Vdd of 3.3 V. These results suggest that the TAB tape assembly has a high potentiality for realizing a thin and light weight RF unit in mobile communication terminals with low cost.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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