Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636985
D. Dawson
This paper addresses the thermal management issues associated with fabricating microwave power devices. Thermal management of microwave devices includes: modeling thermal resistance with techniques such as Green's function/method of images, conformal map, finite element, spectral domain, and Fourier series; measurement techniques such as improved IR, self heating, laser probing, and direct thermocouple measurement; and layout and fabrication alternatives such as silicon substrates, shunt metal paths, and selective thinning that allow smaller form factors while maintaining or reducing thermal resistance. Examples of several device layout and fabrication approaches (MESFET, HBT, PHEMT) show how high frequency performance and low thermal resistance can be part of the unit cell design.
{"title":"Thermal modeling, measurements and design considerations of GaAs microwave devices","authors":"D. Dawson","doi":"10.1109/GAAS.1994.636985","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636985","url":null,"abstract":"This paper addresses the thermal management issues associated with fabricating microwave power devices. Thermal management of microwave devices includes: modeling thermal resistance with techniques such as Green's function/method of images, conformal map, finite element, spectral domain, and Fourier series; measurement techniques such as improved IR, self heating, laser probing, and direct thermocouple measurement; and layout and fabrication alternatives such as silicon substrates, shunt metal paths, and selective thinning that allow smaller form factors while maintaining or reducing thermal resistance. Examples of several device layout and fabrication approaches (MESFET, HBT, PHEMT) show how high frequency performance and low thermal resistance can be part of the unit cell design.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115483807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636975
G. Rohmer, J. Sauerer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider
A feedforward T/H was developed as past of a 200 MSps/10 bit successive approximation ADC using a 0.3 /spl mu/m AlGaAs-HEMT process. This T/H is able to operate up to a clock frequency of 3 GHz and reaches a THD/spl ges/60 dB up to the Nyquist frequency of the ADC at the nominal clock frequency of 800 MHz. This was realized using a special circuit structure with a signal path and a reference path and a new diode bridge switch with an additional auxiliary bridge.
{"title":"An 800 MSps track and hold using a 0.3 /spl mu/m AlGaAs-HEMT-technology","authors":"G. Rohmer, J. Sauerer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider","doi":"10.1109/GAAS.1994.636975","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636975","url":null,"abstract":"A feedforward T/H was developed as past of a 200 MSps/10 bit successive approximation ADC using a 0.3 /spl mu/m AlGaAs-HEMT process. This T/H is able to operate up to a clock frequency of 3 GHz and reaches a THD/spl ges/60 dB up to the Nyquist frequency of the ADC at the nominal clock frequency of 800 MHz. This was realized using a special circuit structure with a signal path and a reference path and a new diode bridge switch with an additional auxiliary bridge.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115712548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636938
D. Hollmann, R. Heilig, G. Baumann
A millimeter-wave GaAs HEMT MMIC distributed mixer covering the RF frequency range from 10 to 50 GHz with IF frequencies from several MHz to 5 GHz was developed. The active devices are AlGaAs-GaAs HEMTs with a gatelength of 0.2 /spl mu/m and a gatewidth of 2/spl times/25 /spl mu/m. The conversion gain of the mixer is better than -3 dB over the frequency range at an LO power of less than 5 dBm without IF amplification. The RF and the LO signals are fed through an active distributed combiner with 2 dB gain and LO to RF port isolation of 20 dB. The size of the single mixer is 1.5/spl times/1 mm/sup 2/ and of the combiner including bias networks is 2/spl times/1 mm/sup 2/. An integrated broadband mixer chip including the LO and RF combiner was fabricated with a size of 4/spl times/1 mm/sup 2/.
{"title":"A monolithic broadband 10-50 GHz distributed HEMT mixer including active LO-RF combiner","authors":"D. Hollmann, R. Heilig, G. Baumann","doi":"10.1109/GAAS.1994.636938","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636938","url":null,"abstract":"A millimeter-wave GaAs HEMT MMIC distributed mixer covering the RF frequency range from 10 to 50 GHz with IF frequencies from several MHz to 5 GHz was developed. The active devices are AlGaAs-GaAs HEMTs with a gatelength of 0.2 /spl mu/m and a gatewidth of 2/spl times/25 /spl mu/m. The conversion gain of the mixer is better than -3 dB over the frequency range at an LO power of less than 5 dBm without IF amplification. The RF and the LO signals are fed through an active distributed combiner with 2 dB gain and LO to RF port isolation of 20 dB. The size of the single mixer is 1.5/spl times/1 mm/sup 2/ and of the combiner including bias networks is 2/spl times/1 mm/sup 2/. An integrated broadband mixer chip including the LO and RF combiner was fabricated with a size of 4/spl times/1 mm/sup 2/.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"88 22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126316272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636958
Kwang-Jun Youn, Jeon-Wook Yang, Chang-Seok Lee, Min-Kun Kim, S. Kang, Seong-Su Park, Dong-Goo Kim, Chul Soon Park, I. Hwang, Hyung‐Moo Park, S. Park
A 1.5 V operating GaAs 2/spl sim/9 GHz ultrawide-band MMIC amplifier for portable wireless LAN, microwave link and satellite communication applications has been developed. This amplifier has 16/spl plusmn/1 dB gain and more than 10 dB input and output return loss in the 2/spl sim/9 GHz frequency range with 118 mA operating current. Measured 1-dB compression power is 13 dBm at 0 dBm input power and minimum noise figure is 4.8 dB. When operated at 3 V and 128 mA, this amplifier has up to 18/spl plusmn/1 dB gain, 18 dBm 1-dB compression power, more than 10 dB return loss and 4.9 dB minimum noise figure.
{"title":"1.5 V ultrawide-band GaAs monolithic amplifier for portable wireless LAN and satellite communication applications","authors":"Kwang-Jun Youn, Jeon-Wook Yang, Chang-Seok Lee, Min-Kun Kim, S. Kang, Seong-Su Park, Dong-Goo Kim, Chul Soon Park, I. Hwang, Hyung‐Moo Park, S. Park","doi":"10.1109/GAAS.1994.636958","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636958","url":null,"abstract":"A 1.5 V operating GaAs 2/spl sim/9 GHz ultrawide-band MMIC amplifier for portable wireless LAN, microwave link and satellite communication applications has been developed. This amplifier has 16/spl plusmn/1 dB gain and more than 10 dB input and output return loss in the 2/spl sim/9 GHz frequency range with 118 mA operating current. Measured 1-dB compression power is 13 dBm at 0 dBm input power and minimum noise figure is 4.8 dB. When operated at 3 V and 128 mA, this amplifier has up to 18/spl plusmn/1 dB gain, 18 dBm 1-dB compression power, more than 10 dB return loss and 4.9 dB minimum noise figure.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126485930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636943
T.M. Smith
This paper describes TriQuint's yield improvement efforts and results for our ion implanted, recessed-gate, MESFET IC processes. It discusses how we approached fab line yield improvement, the techniques that were utilized, some of the lessons learned, and the results achieved from 1989 to present.
{"title":"Wafer fab line yield improvement at TriQuint semiconductor","authors":"T.M. Smith","doi":"10.1109/GAAS.1994.636943","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636943","url":null,"abstract":"This paper describes TriQuint's yield improvement efforts and results for our ion implanted, recessed-gate, MESFET IC processes. It discusses how we approached fab line yield improvement, the techniques that were utilized, some of the lessons learned, and the results achieved from 1989 to present.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125951608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636922
H. Yamada, M. Tunotani, F. Kaneyama, S. Seki
2.5 Gb/s 8/spl times/8 self-routing switch LSIs have been developed for the asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. This switching system consists of three LSIs using a 0.5 /spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells, a "NEMAWASHI" network LSI for previously detecting the cells with the same output port address, and a demultiplexer LSI for converting the cells from the switching network into the eight streams per a channel. These LSIs are mounted in a 520 pin multi-chip module package. The number of total logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and the throughput is 20.8 Gb/s.
{"title":"2.5 Gb/s 8/spl times/8 self-routing switch GaAs LSIs for ATM switching systems","authors":"H. Yamada, M. Tunotani, F. Kaneyama, S. Seki","doi":"10.1109/GAAS.1994.636922","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636922","url":null,"abstract":"2.5 Gb/s 8/spl times/8 self-routing switch LSIs have been developed for the asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. This switching system consists of three LSIs using a 0.5 /spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells, a \"NEMAWASHI\" network LSI for previously detecting the cells with the same output port address, and a demultiplexer LSI for converting the cells from the switching network into the eight streams per a channel. These LSIs are mounted in a 520 pin multi-chip module package. The number of total logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and the throughput is 20.8 Gb/s.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636996
J. Putnam, M. Fukuda, P. Staecker, Y. Yun
This paper presents the design, fabrication, and performance of a 94 GHz monolithic PIN diode SPDT switch. The switch uses a vertical PIN diode structure to achieve insertion loss of 1.0 dB and isolation greater than 30 dB at 94 GHz, The circuits were fabricated on semi-insulating GaAs wafers with MOCVD grown p+, i, and n+ layers. An AlGaAs layer was used as an etch stop in the fabrication of the backside via hole. Measurements were made in a fixture containing transitions from WR-10 waveguide to quartz microstrip and from the quartz microstrip to the MMIC chip.
{"title":"A 94 GHz monolithic switch with a vertical PIN diode structure","authors":"J. Putnam, M. Fukuda, P. Staecker, Y. Yun","doi":"10.1109/GAAS.1994.636996","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636996","url":null,"abstract":"This paper presents the design, fabrication, and performance of a 94 GHz monolithic PIN diode SPDT switch. The switch uses a vertical PIN diode structure to achieve insertion loss of 1.0 dB and isolation greater than 30 dB at 94 GHz, The circuits were fabricated on semi-insulating GaAs wafers with MOCVD grown p+, i, and n+ layers. An AlGaAs layer was used as an etch stop in the fabrication of the backside via hole. Measurements were made in a fixture containing transitions from WR-10 waveguide to quartz microstrip and from the quartz microstrip to the MMIC chip.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129563265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636935
Huei Wang, R. Lai, M. Biedenbender, G. Dow, B. Allen
A monolithic W-band push-pull two-stage power amplifier has been developed using 0.1 pm AlGaAs-InGaAs-GaAs pseudomorphic T-gate power HEMT technology. This novel design utilizes the push-pull scheme to take the advantage of a virtual ground in a push-pull HEMT device pair which eliminates the via hole inductance, and improves the power amplifier performance at millimeter-wave frequency. The measurement results show that a small signal gain of 12 dB, an output power of 19.4 dBm, and a power added efficiency of 13.3% have been achieved at 90 GHz, and presents state-of-the-art performance for a monolithic power amplifiers at this frequency. To our knowledge, this is the first reported monolithic push-pull amplifier at millimeter-wave frequencies.
{"title":"A novel W-band monolithic push-pull power amplifier","authors":"Huei Wang, R. Lai, M. Biedenbender, G. Dow, B. Allen","doi":"10.1109/GAAS.1994.636935","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636935","url":null,"abstract":"A monolithic W-band push-pull two-stage power amplifier has been developed using 0.1 pm AlGaAs-InGaAs-GaAs pseudomorphic T-gate power HEMT technology. This novel design utilizes the push-pull scheme to take the advantage of a virtual ground in a push-pull HEMT device pair which eliminates the via hole inductance, and improves the power amplifier performance at millimeter-wave frequency. The measurement results show that a small signal gain of 12 dB, an output power of 19.4 dBm, and a power added efficiency of 13.3% have been achieved at 90 GHz, and presents state-of-the-art performance for a monolithic power amplifiers at this frequency. To our knowledge, this is the first reported monolithic push-pull amplifier at millimeter-wave frequencies.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636976
K. Poulton, K. Knudsen, J. Corcoran, K. C. Wang, R. Nubling, R. Pierson, M. Chang, P. Asbeck, R. Huang
A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADC's measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.
{"title":"A 6-bit, 4 GSa/s ADC fabricated in a GaAs HBT process","authors":"K. Poulton, K. Knudsen, J. Corcoran, K. C. Wang, R. Nubling, R. Pierson, M. Chang, P. Asbeck, R. Huang","doi":"10.1109/GAAS.1994.636976","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636976","url":null,"abstract":"A GaAs-AlGaAs Heterojunction Bipolar Transistor (HBT) process was developed to meet the speed, gain and yield requirements for Analog to Digital Converters (ADCs). A 6-bit, 4 GSa/s (4 giga-samples per second) ADC was designed and fabricated in this process. The standard HBT used has an emitter area of 1.4/spl times/3.0 /spl mu/m; it has current gain of over 70 at I/sub c/=1 mA and f/sub T/ and f/sub MAX/ of over 50 GHz at I/sub c/=4 mA. The process also includes Schottky diodes, thin-film NiCr resistors, MIM capacitors and three levels of metal interconnect. The ADC uses an analog folding architecture to reduce transistor count and power well below that of a straight 6-bit flash ADC. It includes an on-chip track-and-hold (T/H) circuit and Gray-encoded digital outputs for best immunity to dynamic errors. The ADC's measured differential nonlinearity is less than /spl plusmn/0.5 LSB and its integral nonlinearity is less than /spl plusmn/0.8 LSB. It has a resolution bandwidth (the frequency at which effective bits has dropped by 0.5 bits) of 2.4 GHz at 3 GSa/s and 1.8 GHz at 4 GSa/s, higher than any ADC published to date. The chip operates at up to 6.5 GSa/s, but linearity at that clock rate is much worse.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127900302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-16DOI: 10.1109/GAAS.1994.636930
P. Hills
Transport in the UK and most other European countries, during the latter half of this century, has been dominated by the growth of private car ownership. All the attendant problems of congestion, pollution and accidents are conspiring to undermine the huge personal and social benefits that individuals and households derive from car ownership and use. Nor has this process run its full course; the UK Department of Transport in its National Road Traffic Forecasts (NRTF) foresee the possibility of the total annual vehicle-kms more than doubling between now and the year 2030, before some kind of "saturation" in car-use might be reached. The extent to which these forecasts are reflecting the powerful economic forces that determine future traffic demand or are themselves driven by current transport policy is the subject of much debate. More radical policies, such as tolling inter-urban motorways, congestion-pricing and traffic-calming in urban areas and encouraging the spread of tele-commuting could modify and reshape future travel-demands substantially, with significant implications for daily life. Throughout this transport "informatics" revolution, the Transport Operations Research Group (TORG) at the University of Newcastle upon Tyne has played a leading role. In particular, TORG has acted as the prime contractor in a 16-partner European project called ADEPT (Automatic Debiting and Electronic Payment for Transport), financed by the EC DRIVE programme. This is described and plans for future research outlined.
{"title":"Developments in transport telematics in Europe. The case of automatic debiting at speed","authors":"P. Hills","doi":"10.1109/GAAS.1994.636930","DOIUrl":"https://doi.org/10.1109/GAAS.1994.636930","url":null,"abstract":"Transport in the UK and most other European countries, during the latter half of this century, has been dominated by the growth of private car ownership. All the attendant problems of congestion, pollution and accidents are conspiring to undermine the huge personal and social benefits that individuals and households derive from car ownership and use. Nor has this process run its full course; the UK Department of Transport in its National Road Traffic Forecasts (NRTF) foresee the possibility of the total annual vehicle-kms more than doubling between now and the year 2030, before some kind of \"saturation\" in car-use might be reached. The extent to which these forecasts are reflecting the powerful economic forces that determine future traffic demand or are themselves driven by current transport policy is the subject of much debate. More radical policies, such as tolling inter-urban motorways, congestion-pricing and traffic-calming in urban areas and encouraging the spread of tele-commuting could modify and reshape future travel-demands substantially, with significant implications for daily life. Throughout this transport \"informatics\" revolution, the Transport Operations Research Group (TORG) at the University of Newcastle upon Tyne has played a leading role. In particular, TORG has acted as the prime contractor in a 16-partner European project called ADEPT (Automatic Debiting and Electronic Payment for Transport), financed by the EC DRIVE programme. This is described and plans for future research outlined.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116354248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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