Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830416
Dong-Jin Chang, S. Ryu
An on-chip background skew calibration technique for time-interleaved (TI) ADCs with relative-prime rotation (RPR) based autocorrelation computation is presented, with which more flexible choice of number of channels and no residual skew accumulation are realized. An 8 × TI 10b 1.4GS/s prototype ADC with fully on-chip calibration achieves an SNDR of 48.2dB at over Nyquist input and a FoM of 33 fJ/c-s in 28-nm FDSOI. The on-chip calibration circuitry takes only 24% of the ADC-core power consumption.
提出了一种基于相对素旋转(RPR)自相关计算的时间交错(TI) adc的片上背景偏度校准技术，该技术可以更灵活地选择通道数，且不存在残余偏度积累。采用全片上校准的8 × TI 10b 1.4GS/s原型ADC在Nyquist输入下的SNDR为48.2dB，在28纳米FDSOI中FoM为33 fJ/c-s。片上校准电路仅占adc核心功耗的24%。
{"title":"A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs","authors":"Dong-Jin Chang, S. Ryu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830416","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830416","url":null,"abstract":"An on-chip background skew calibration technique for time-interleaved (TI) ADCs with relative-prime rotation (RPR) based autocorrelation computation is presented, with which more flexible choice of number of channels and no residual skew accumulation are realized. An 8 × TI 10b 1.4GS/s prototype ADC with fully on-chip calibration achieves an SNDR of 48.2dB at over Nyquist input and a FoM of 33 fJ/c-s in 28-nm FDSOI. The on-chip calibration circuitry takes only 24% of the ADC-core power consumption.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124225151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830462
H. Chiang, J. Wang, Kuan‐Heng Lin, C. Nien, J. Wu, K.-Y. Hsiang, Chih-Piao Chuu, Y.-W. Chen, X. W. Zhang, C. Liu, Tahui Wang, C. -. Wang, M. Lee, M. Chang, C. Chang, T. C. Chen
For the first time, we demonstrate Ferroelectric Tunneling Junctions (FTJs) with both (a) 10-year retention time projected from measured data and (b) robust endurance (> 108 cycles) with the on-off ratio >10× by inserting a 1.8nm Al2O3 interfacial layer (IL) into the FTJs. Compared with Metal-Ferroelectric-Metal (MFM) FTJs, higher orthorhombic phase (~6×) was verified by physical analyses and first-principles calculations in our proposed Metal-Ferroelectric-IL-Metal (MFIM) FTJs, resulting in the remanent polarization (2Pr) which improves the retention and the on-off ratio significantly.
通过在铁电隧道结(ftj)中插入1.8nm的Al2O3界面层(IL)，我们首次展示了铁电隧道结(ftj)具有(a)根据测量数据预测的10年保留时间和(b)稳健的耐久性(> 108次循环)和>10倍的通断比。通过物理分析和第一性原理计算，与金属-铁电-铁电-金属(MFM) ftj相比，我们提出的金属-铁电-铁电- il -金属(MFIM) ftj具有更高的正交相(~ 6x)，导致剩余极化(2Pr)，显著提高了保持率和通断比。
{"title":"Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array","authors":"H. Chiang, J. Wang, Kuan‐Heng Lin, C. Nien, J. Wu, K.-Y. Hsiang, Chih-Piao Chuu, Y.-W. Chen, X. W. Zhang, C. Liu, Tahui Wang, C. -. Wang, M. Lee, M. Chang, C. Chang, T. C. Chen","doi":"10.1109/vlsitechnologyandcir46769.2022.9830462","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830462","url":null,"abstract":"For the first time, we demonstrate Ferroelectric Tunneling Junctions (FTJs) with both (a) 10-year retention time projected from measured data and (b) robust endurance (> 108 cycles) with the on-off ratio >10× by inserting a 1.8nm Al2O3 interfacial layer (IL) into the FTJs. Compared with Metal-Ferroelectric-Metal (MFM) FTJs, higher orthorhombic phase (~6×) was verified by physical analyses and first-principles calculations in our proposed Metal-Ferroelectric-IL-Metal (MFIM) FTJs, resulting in the remanent polarization (2Pr) which improves the retention and the on-off ratio significantly.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"18 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830265
Seok-Hee Lee
Innovation in the memory semiconductor industry has continued to provide a number of key solutions to address the challenges of ever-changing, data-driven computing. However, besides the demand for high performance, low power, low cost, and high capacity, there is also an increasing demand for more smart functionalities in or near memory to minimize the data movement.In this paper, we will share our vision of memory innovation. First, we begin the journey with memory extension, in which the conventional scaling in both DRAM and NAND can be pushed further to defy the device scaling limits. Then, the journey will ultimately lead to the memory-centric transformation. The memory-centric transformation has just begun with PIM (Processing-In-Memory) and is expected to evolve by bringing memory and logic closer together with advanced packaging techniques in order to achieve optimal system performance.In addition, new solutions enabled by new interfaces such as CXL (Compute Express Link) will be introduced to enhance the current value proposition of the memory technology.Last but not least, our endeavors as a responsible member of the global community will be introduced. Our ongoing efforts are focused on reducing carbon emissions, water usage, and power consumption in all our products and manufacturing processes.SK hynix truly believes that the journey of Memory would only be possible when the ICT industry as a whole embraces open innovation to create a better and more sustainable world.
{"title":"The Rise of Memory in the Ever-Changing AI Era – From Memory to More-Than-Memory","authors":"Seok-Hee Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830265","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830265","url":null,"abstract":"Innovation in the memory semiconductor industry has continued to provide a number of key solutions to address the challenges of ever-changing, data-driven computing. However, besides the demand for high performance, low power, low cost, and high capacity, there is also an increasing demand for more smart functionalities in or near memory to minimize the data movement.In this paper, we will share our vision of memory innovation. First, we begin the journey with memory extension, in which the conventional scaling in both DRAM and NAND can be pushed further to defy the device scaling limits. Then, the journey will ultimately lead to the memory-centric transformation. The memory-centric transformation has just begun with PIM (Processing-In-Memory) and is expected to evolve by bringing memory and logic closer together with advanced packaging techniques in order to achieve optimal system performance.In addition, new solutions enabled by new interfaces such as CXL (Compute Express Link) will be introduced to enhance the current value proposition of the memory technology.Last but not least, our endeavors as a responsible member of the global community will be introduced. Our ongoing efforts are focused on reducing carbon emissions, water usage, and power consumption in all our products and manufacturing processes.SK hynix truly believes that the journey of Memory would only be possible when the ICT industry as a whole embraces open innovation to create a better and more sustainable world.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115854684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830220
Haiwen Xu, R. Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong
For the first time, we have developed a novel growth technique of Si1-xGex having active boron (B) doping concentration (NA) higher than 2×1021 cm-3. We achieve (1) uniform B doping and Ge composition in the epi-growth direction, (2) excellent uniformities in Si1-xGex thickness and resistivity across the entire 300 mm wafer, (3) an ultra-low as-deposited specific contact resistivity (ρc) of 5.1×10-10 Ω-cm2 on the sample with the highest NA of 2.5×1021 cm-3, and (4) successful selective growth on the advanced 3D structures with excellent conformality and thickness controllability.
{"title":"300 mm Wafer-scale In-situ CVD Growth Achieving 5.1×10-10 Ω-cm2 P-Type Contact Resistivity: Record 2.5×1021 cm-3 Active Doping and Demonstration on Highly-Scaled 3D Structures","authors":"Haiwen Xu, R. Khazaka, Jishen Zhang, Zijie Zheng, Yue Chen, Xiao Gong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830220","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830220","url":null,"abstract":"For the first time, we have developed a novel growth technique of Si<inf>1-x</inf>Ge<inf>x</inf> having active boron (B) doping concentration (N<inf>A</inf>) higher than 2×10<sup>21</sup> cm<sup>-3</sup>. We achieve (1) uniform B doping and Ge composition in the epi-growth direction, (2) excellent uniformities in Si<inf>1-x</inf>Ge<inf>x</inf> thickness and resistivity across the entire 300 mm wafer, (3) an ultra-low as-deposited specific contact resistivity (ρ<inf>c</inf>) of 5.1×10<sup>-10</sup> Ω-cm<sup>2</sup> on the sample with the highest N<inf>A</inf> of 2.5×10<sup>21</sup> cm<sup>-3</sup>, and (4) successful selective growth on the advanced 3D structures with excellent conformality and thickness controllability.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830447
S. Su, E. Chen, T. Hung, Mengyao Li, G. Pitner, Chao-Ching Cheng, Han Wang, J. Cai, H. P. Wong, I. Radu
Low-dimensional materials (LDMs) such as two-dimensional transition metal dichalcogenides (2D TMDs) and carbon nanotubes (CNTs) have the potential to be the channel material in extremely scaled CMOS transistors. Based on current hardware data, the design space for contacted-gate pitch (CGP) scaled transistors is explored for these materials. The ON current, sources of leakage which limit OFF current, and CGP scaling potential are analyzed by separately considering effects from shrinking the gate length, contact length, and extension length. Doping of LDM is the main challenge to reduce contact and extension resistance for scaled transistors. Experimental control of p-type doping of 2D is reported as an example of doping impact.
{"title":"Perspective on Low-dimensional Channel Materials for Extremely Scaled CMOS","authors":"S. Su, E. Chen, T. Hung, Mengyao Li, G. Pitner, Chao-Ching Cheng, Han Wang, J. Cai, H. P. Wong, I. Radu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830447","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830447","url":null,"abstract":"Low-dimensional materials (LDMs) such as two-dimensional transition metal dichalcogenides (2D TMDs) and carbon nanotubes (CNTs) have the potential to be the channel material in extremely scaled CMOS transistors. Based on current hardware data, the design space for contacted-gate pitch (CGP) scaled transistors is explored for these materials. The ON current, sources of leakage which limit OFF current, and CGP scaling potential are analyzed by separately considering effects from shrinking the gate length, contact length, and extension length. Doping of LDM is the main challenge to reduce contact and extension resistance for scaled transistors. Experimental control of p-type doping of 2D is reported as an example of doping impact.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131007288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830277
Ben Keller, Rangharajan Venkatesan, Steve Dai, S. Tell, B. Zimmer, W. Dally, C. T. Gray, Brucek Khailany
We present a deep neural network (DNN) accelerator designed for efficient execution of transformer-based DNNs, which have become ubiquitous for natural language processing tasks. DNN inference accelerators often employ specialized hardware techniques such as reduced precision to improve energy efficiency, but many of these techniques result in catastrophic accuracy loss on transformers. The proposed accelerator supports per-vector scaled quantization and approximate softmax to enable the use of 4-bit arithmetic with little accuracy loss. The 5nm prototype achieves 95.6 TOPS/W in benchmarking and 1711 inferences/s/W with only 0.7% accuracy loss on BERT, demonstrating a practical accelerator design for energy-efficient inference with transformers.
{"title":"A 17–95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm","authors":"Ben Keller, Rangharajan Venkatesan, Steve Dai, S. Tell, B. Zimmer, W. Dally, C. T. Gray, Brucek Khailany","doi":"10.1109/vlsitechnologyandcir46769.2022.9830277","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830277","url":null,"abstract":"We present a deep neural network (DNN) accelerator designed for efficient execution of transformer-based DNNs, which have become ubiquitous for natural language processing tasks. DNN inference accelerators often employ specialized hardware techniques such as reduced precision to improve energy efficiency, but many of these techniques result in catastrophic accuracy loss on transformers. The proposed accelerator supports per-vector scaled quantization and approximate softmax to enable the use of 4-bit arithmetic with little accuracy loss. The 5nm prototype achieves 95.6 TOPS/W in benchmarking and 1711 inferences/s/W with only 0.7% accuracy loss on BERT, demonstrating a practical accelerator design for energy-efficient inference with transformers.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127911321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830492
P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.
{"title":"PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch","authors":"P. Schuddinck, F. M. Bufler, Y. Xiang, A. Farokhnejad, G. Mirabelli, A. Vandooren, B. Chehab, A. Gupta, C. Neve, G. Hellings, J. Ryckaert","doi":"10.1109/vlsitechnologyandcir46769.2022.9830492","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830492","url":null,"abstract":"We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124684005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830400
A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi
3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.
{"title":"Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections","authors":"A. Vandooren, N. Parihar, J. Franco, R. Loo, H. Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, A. Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, L. Van-Jodin, G. Besnard, C. Neve, Bich-Yen Nguyen, I. Radu, E. Litta, N. Horiguchi","doi":"10.1109/vlsitechnologyandcir46769.2022.9830400","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830400","url":null,"abstract":"3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830469
Ji-Seon Paek, Jeongkwan Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee
This paper presents fully integrated 2x2 MIMO dual-band CMOS power amplifiers with a simultaneous multiple PA supply voltage modulation technique using a switched-capacitor (SC)-based single inductor multiple output (SIMO) DC-DC converter. For 802.11ax MCS11 160/40MHz signals, the designed A/G-band CMOS PAs using the proposed supply modulation scheme achieve -40dB EVM at 15.7/18.5dBm output power and save 340/334mW of dc power consumption compared to 3.3V fixed supply voltage PA, respectively.
{"title":"Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation Technique","authors":"Ji-Seon Paek, Jeongkwan Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee","doi":"10.1109/vlsitechnologyandcir46769.2022.9830469","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830469","url":null,"abstract":"This paper presents fully integrated 2x2 MIMO dual-band CMOS power amplifiers with a simultaneous multiple PA supply voltage modulation technique using a switched-capacitor (SC)-based single inductor multiple output (SIMO) DC-DC converter. For 802.11ax MCS11 160/40MHz signals, the designed A/G-band CMOS PAs using the proposed supply modulation scheme achieve -40dB EVM at 15.7/18.5dBm output power and save 340/334mW of dc power consumption compared to 3.3V fixed supply voltage PA, respectively.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126975192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830350
Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kaiyang Wang, Yan Wang
This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.
{"title":"A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP","authors":"Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kaiyang Wang, Yan Wang","doi":"10.1109/vlsitechnologyandcir46769.2022.9830350","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830350","url":null,"abstract":"This work presents a packaged 90-to-96GHz 16-Element transceiver phased array. It is constructed using 4-channel silicon beamformers in 65nm CMOS process, external power amplifiers (PAs) and low noise amplifiers in 100nm GaN process as well as Vivaldi antennas on a tsm-ds3 based printed circuit board (PCB). A transformer-and coupled-line-based 8-to-1 power combine technique is proposed in the silicon beamformer to achieve a measured Psat of +18.8dBm with an OP1dB of +15.8dBm and a peak PAE of 14.8% in CMOS. With external GaN PAs, the 16-Element transceiver phased array demonstrates a measured 26° 3-dB beamwidth, +51dBm peak EIRP at Psat and the ability to scan to ±30° in all planes.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125925635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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