This work developed a compact model of the stackable vertical Channel-All-Around (CAA) IGZO FETs, based on carrier trapping dynamics and (inner/outer) surface potential of a cylindrical channel shell. It is calibrated to fabricated devices with geometric effects (e.g., asymmetry Source/Drain (S/D) to Gate (G) overlaps) on turn-on voltage (Von). Besides, temperature (T) effects on Von, leakage current and non-linear contacts were considered from 233 K to 393 K, and such degradation effects contribute to time-zero instability (TZI) on DRAM retention performance. To further understand time dependent reliability (i.e., bias-temperature-instability, BTI), an abnormal PBTI with negative Von shift is studied from the perspective of device physics and is more pronounced than NBTI. By incorporating TZI and BTI in capacitor-less DRAMs, it enables a reliability-aware design technology co-optimization flow characterizing weak cells for scalability of BEOL-compatible 3D integration.
{"title":"Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability","authors":"Jingrui Guo, Ying Sun, Lingfei Wang, Xinlv Duan, Kailiang Huang, Zhaogui Wang, Junxiao Feng, Qian Chen, Shijie Huang, Lihua Xu, Di Geng, Guangfan Jiao, Shihui Yin, Zhengbo Wang, Weiliang Jing, Ling Li, Ming Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830482","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830482","url":null,"abstract":"This work developed a compact model of the stackable vertical Channel-All-Around (CAA) IGZO FETs, based on carrier trapping dynamics and (inner/outer) surface potential of a cylindrical channel shell. It is calibrated to fabricated devices with geometric effects (e.g., asymmetry Source/Drain (S/D) to Gate (G) overlaps) on turn-on voltage (Von). Besides, temperature (T) effects on Von, leakage current and non-linear contacts were considered from 233 K to 393 K, and such degradation effects contribute to time-zero instability (TZI) on DRAM retention performance. To further understand time dependent reliability (i.e., bias-temperature-instability, BTI), an abnormal PBTI with negative Von shift is studied from the perspective of device physics and is more pronounced than NBTI. By incorporating TZI and BTI in capacitor-less DRAMs, it enables a reliability-aware design technology co-optimization flow characterizing weak cells for scalability of BEOL-compatible 3D integration.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120880995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830235
Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao
We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.
{"title":"A 0.4mm3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip Antenna","authors":"Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao","doi":"10.1109/vlsitechnologyandcir46769.2022.9830235","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830235","url":null,"abstract":"We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830509
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, J. Melchert, Gedeon Nyengele, Maxwell Strange, Kecheng Zhang, Ankita Nayak, Jeff Setter, James J. Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, S. Richardson, Rick Bahr, Christopher Torng, M. Horowitz, Priyanka Raina
Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications such as machine learning (ML), image processing, and computer vision. It achieves a peak energy efficiency of 538.0 INT16 GOPS/W and 483.3 BFloat16 GFLOPS/W. We maximize CGRA utilization and minimize reconfigurability overhead through (1) dynamic partial reconfiguration of the CGRA that enables higher resource utilization by allowing multiple applications to run at once, (2) efficient streaming memory controllers supporting affine access patterns, and (3) low-overhead transcendental and complex arithmetic operations. Compared to a CPU, a GPU, and an FPGA, Amber achieves up to 3902x, 152x, and 88x better energy-delay product (EDP).
{"title":"Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra","authors":"Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, J. Melchert, Gedeon Nyengele, Maxwell Strange, Kecheng Zhang, Ankita Nayak, Jeff Setter, James J. Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, S. Richardson, Rick Bahr, Christopher Torng, M. Horowitz, Priyanka Raina","doi":"10.1109/vlsitechnologyandcir46769.2022.9830509","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830509","url":null,"abstract":"Amber is a system-on-chip (SoC) with a coarse-grained reconfigurable array (CGRA) for acceleration of dense linear algebra applications such as machine learning (ML), image processing, and computer vision. It achieves a peak energy efficiency of 538.0 INT16 GOPS/W and 483.3 BFloat16 GFLOPS/W. We maximize CGRA utilization and minimize reconfigurability overhead through (1) dynamic partial reconfiguration of the CGRA that enables higher resource utilization by allowing multiple applications to run at once, (2) efficient streaming memory controllers supporting affine access patterns, and (3) low-overhead transcendental and complex arithmetic operations. Compared to a CPU, a GPU, and an FPGA, Amber achieves up to 3902x, 152x, and 88x better energy-delay product (EDP).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830456
Inhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck
Providing performance-and-power optimized SRAM compiler with wide a range of operating voltages and configurations is a major challenge in advanced technologies. In this paper, the Row Auto-Tracking Write Assist (RATWA) and Voltage Auto-Tracking Pulse Generator (VATPG) are proposed to overcome major two issues in the SRAM compiler. The RATWA efficiently controls the strength of write assist under various types of SRAM RPB (Rows Per Bitline), and it demonstrates a 7% dynamic power improvement, especially at 64 RPB. The VATPG adaptively adjusts the gate level of the tracking circuit and shows a stable read margin across a wide range of voltages, up to 22% SRAM read speed improvement, and 9% dynamic power saving at higher voltage ranges.
{"title":"4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits","authors":"Inhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck","doi":"10.1109/vlsitechnologyandcir46769.2022.9830456","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830456","url":null,"abstract":"Providing performance-and-power optimized SRAM compiler with wide a range of operating voltages and configurations is a major challenge in advanced technologies. In this paper, the Row Auto-Tracking Write Assist (RATWA) and Voltage Auto-Tracking Pulse Generator (VATPG) are proposed to overcome major two issues in the SRAM compiler. The RATWA efficiently controls the strength of write assist under various types of SRAM RPB (Rows Per Bitline), and it demonstrates a 7% dynamic power improvement, especially at 64 RPB. The VATPG adaptively adjusts the gate level of the tracking circuit and shows a stable read margin across a wide range of voltages, up to 22% SRAM read speed improvement, and 9% dynamic power saving at higher voltage ranges.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128908298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830464
Gyeong-Gu Kang, Ji-Hun Lee, Se-un Shin, G. Cho, Hyunsik Kim
In this paper, a boost-oriented single-inductor dual-output (BO-SIDO) step-up/down DC-DC converter is presented. The BO-SIDO design enables only 1×RON conduction in all inductor-current paths, improving power efficiency. While regulating the heavy-loaded boost output, the seamless buck conversion can be embedded adaptively to the buck load. The chip was fabricated in 0.5-μm CMOS, and it achieved 96.6% peak efficiency and maximum output power of 5.6W.
{"title":"A 5.6W-Power 96.6%-Efficiency Boost-Oriented SIDO Step-Up/Down DC-DC Converter Embedding Buck Conversion with an Energy-Balancing Capacitor","authors":"Gyeong-Gu Kang, Ji-Hun Lee, Se-un Shin, G. Cho, Hyunsik Kim","doi":"10.1109/vlsitechnologyandcir46769.2022.9830464","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830464","url":null,"abstract":"In this paper, a boost-oriented single-inductor dual-output (BO-SIDO) step-up/down DC-DC converter is presented. The BO-SIDO design enables only 1×RON conduction in all inductor-current paths, improving power efficiency. While regulating the heavy-loaded boost output, the seamless buck conversion can be embedded adaptively to the buck load. The chip was fabricated in 0.5-μm CMOS, and it achieved 96.6% peak efficiency and maximum output power of 5.6W.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130276513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830202
Cheng Chen, Joonseok Yang, Hui Wang, Zhidong Cao, Siavash Kananian, Kevin Chen, A. Poon
This work presents a penny-sized 1.2-gram (battery included) wearable wireless EEG recorder for continuous long-term mental health monitoring. Each device has two 12-bit Σ-Δ ADCs with 9.4-bit peak ENOB. With 12-channel FDMA transmitter (TX) in the 902-928MHz ISM band, concurrent untethered recording can be achieved at 24 sites. 90µW power consumption enables month-long battery life with a size-10 hearing-aid battery. System functionality has been validated by comparing with clinical-grade instrument in measurements of both eye-closed alpha wave and event-related potential (ERP).
{"title":"A 90-μW Penny-Sized 1.2-gram Wireless EEG Recorder with 12-Channel FDMA Transmitter for Month-Long Continuous Mental Health Monitoring","authors":"Cheng Chen, Joonseok Yang, Hui Wang, Zhidong Cao, Siavash Kananian, Kevin Chen, A. Poon","doi":"10.1109/vlsitechnologyandcir46769.2022.9830202","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830202","url":null,"abstract":"This work presents a penny-sized 1.2-gram (battery included) wearable wireless EEG recorder for continuous long-term mental health monitoring. Each device has two 12-bit Σ-Δ ADCs with 9.4-bit peak ENOB. With 12-channel FDMA transmitter (TX) in the 902-928MHz ISM band, concurrent untethered recording can be achieved at 24 sites. 90µW power consumption enables month-long battery life with a size-10 hearing-aid battery. System functionality has been validated by comparing with clinical-grade instrument in measurements of both eye-closed alpha wave and event-related potential (ERP).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830507
Hyunsub Norbert Rie, Chang-Soo Yoon, J. Byun, Sucheol Lee, Garam Kim, J. Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, M. Jung, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, E. Shin, Hyuk-Jun Kwon, Youngdon Choi, J. Choi, Hyungjong Ko
This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce channel power consumption. Direct 4-tap decision feedback equalizer (DFE) with timing calibrated reset-less slicer at receiver (RX) and asymmetric bidirectional T-coil are employed to achieve the highest data-rate among the state-of-the-art DRAM I/Os. The prototype chip is fabricated in mimicked 10-nm class DRAM process using 28-nm CMOS. At sub-1V VDDQL, measured TX common eye window is 0.31UI. Measured RX shmoo has total of 162 pass ticks, each tick with the size of 5mV * 1ps and BER under 10-6. The total energy efficiency of 2.02pJ/b was achieved.
{"title":"A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application","authors":"Hyunsub Norbert Rie, Chang-Soo Yoon, J. Byun, Sucheol Lee, Garam Kim, J. Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, M. Jung, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, E. Shin, Hyuk-Jun Kwon, Youngdon Choi, J. Choi, Hyungjong Ko","doi":"10.1109/vlsitechnologyandcir46769.2022.9830507","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830507","url":null,"abstract":"This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce channel power consumption. Direct 4-tap decision feedback equalizer (DFE) with timing calibrated reset-less slicer at receiver (RX) and asymmetric bidirectional T-coil are employed to achieve the highest data-rate among the state-of-the-art DRAM I/Os. The prototype chip is fabricated in mimicked 10-nm class DRAM process using 28-nm CMOS. At sub-1V VDDQL, measured TX common eye window is 0.31UI. Measured RX shmoo has total of 162 pass ticks, each tick with the size of 5mV * 1ps and BER under 10-6. The total energy efficiency of 2.02pJ/b was achieved.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830310
Wenxuan Sun, Woyu Zhang, Jie Yu, Yi Li, Zeyu Guo, Jinru Lai, Danian Dong, Xu Zheng, Fei Wang, Shaoyang Fan, Xiaoxin Xu, Dashan Shang, Meilin Liu
In this work, we realized a three-dimensional (3D) reservoir computing (RC) by utilizing the I-V nonlinearity and short-term memory of the dynamic memristor in 4-layer vertical array. The cycle-to-cycle variation of the dynamic reservoir is improved by parallel memristor configuration. The dimensionality of the reservoir space is increased by input strategy design. After the hardware-software co-optimization, the proposed 3D RC system exhibits high recognition accuracy (90%), low energy consumption (~0.78 pJ /operation), and high area efficiency (5.12 TOPS/mm2).
{"title":"3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm2) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing","authors":"Wenxuan Sun, Woyu Zhang, Jie Yu, Yi Li, Zeyu Guo, Jinru Lai, Danian Dong, Xu Zheng, Fei Wang, Shaoyang Fan, Xiaoxin Xu, Dashan Shang, Meilin Liu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830310","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830310","url":null,"abstract":"In this work, we realized a three-dimensional (3D) reservoir computing (RC) by utilizing the I-V nonlinearity and short-term memory of the dynamic memristor in 4-layer vertical array. The cycle-to-cycle variation of the dynamic reservoir is improved by parallel memristor configuration. The dimensionality of the reservoir space is increased by input strategy design. After the hardware-software co-optimization, the proposed 3D RC system exhibits high recognition accuracy (90%), low energy consumption (~0.78 pJ /operation), and high area efficiency (5.12 TOPS/mm2).","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125385579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830184
H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. Cho, K. Rim, S. Kwon
We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV2) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (Vmin) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV2. For the first time, we have demonstrated Vmin of 1-fin F/F same as 2-fin one and 27% CV2 reduction with keeping speed at a constant leakage.
{"title":"Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint","authors":"H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H. Cho, K. Rim, S. Kwon","doi":"10.1109/vlsitechnologyandcir46769.2022.9830184","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830184","url":null,"abstract":"We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV<sup>2</sup>) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (V<inf>min</inf>) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV<sup>2</sup>. For the first time, we have demonstrated V<inf>min</inf> of 1-fin F/F same as 2-fin one and 27% CV<sup>2</sup> reduction with keeping speed at a constant leakage.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126625174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830467
Kyunghyun Son, Dongjae Shin, Jisan Lee, Bongyong Jang, Dongsik Shim, H. Byun, Chang-Bum Lee, Yongchul Cho, Tatsuhiro Otsuka, C. Shin, Inoh Hwang, Eunkyung Lee, Kyoungho Ha, H. Choo
We have implemented a compact, highly accurate light detection and ranging (LiDAR) module using our III/V-on-Si optical phased array (OPA). Our module measures only 1.4 liter in volume, and we demonstrated 20-m ranging and 10-m 3D imaging with 1-cm accuracy under 100-klx bright sunlight. The accuracy was improved by 300% from our previous work [1] by employing sub-binning-based digital signal processing (DSP). The small size and its robust 3D depth-sensing performance promise strong commercial viability.
{"title":"Palm-sized LiDAR module with III/V-on-Si optical phased array","authors":"Kyunghyun Son, Dongjae Shin, Jisan Lee, Bongyong Jang, Dongsik Shim, H. Byun, Chang-Bum Lee, Yongchul Cho, Tatsuhiro Otsuka, C. Shin, Inoh Hwang, Eunkyung Lee, Kyoungho Ha, H. Choo","doi":"10.1109/vlsitechnologyandcir46769.2022.9830467","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830467","url":null,"abstract":"We have implemented a compact, highly accurate light detection and ranging (LiDAR) module using our III/V-on-Si optical phased array (OPA). Our module measures only 1.4 liter in volume, and we demonstrated 20-m ranging and 10-m 3D imaging with 1-cm accuracy under 100-klx bright sunlight. The accuracy was improved by 300% from our previous work [1] by employing sub-binning-based digital signal processing (DSP). The small size and its robust 3D depth-sensing performance promise strong commercial viability.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123016934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：